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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-03 16:28:14 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-03 16:28:14 -0400
commitd6748066ad0e8b2514545998f8367ebb3906f299 (patch)
treef7a9bfd764a8fb781aeda0ef2249afbab42dddf7 /arch/mips/alchemy
parentf04c045f8ce69c22bda9d99eb927276b776135fc (diff)
parent3ba1e543ab4b02640d396098f2f6a199560d5f2d (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits) MIPS: O32: Provide definition of registers ta0 .. ta3. MIPS: perf: Add Octeon support for hardware perf. MIPS: perf: Add support for 64-bit perf counters. MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: Add probes for more Octeon II CPUs. MIPS: Add more CPU identifiers for Octeon II CPUs. MIPS: XLR, XLS: Add comment for smp setup MIPS: JZ4740: GPIO: Check correct IRQ in demux handler MIPS: JZ4740: GPIO: Simplify IRQ demuxer MIPS: JZ4740: Use generic irq chip MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep MIPS: Alchemy: Redo PCI as platform driver MIPS: Alchemy: more base address cleanup MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: abstract USB block control register access ... Fix up trivial conflicts in: arch/mips/alchemy/devboards/db1x00/platform.c drivers/ide/Kconfig drivers/mmc/host/au1xmmc.c drivers/video/Kconfig sound/mips/Kconfig
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/Kconfig50
-rw-r--r--arch/mips/alchemy/common/Makefile6
-rw-r--r--arch/mips/alchemy/common/dbdma.c203
-rw-r--r--arch/mips/alchemy/common/dma.c72
-rw-r--r--arch/mips/alchemy/common/gpiolib.c (renamed from arch/mips/alchemy/common/gpiolib-au1000.c)35
-rw-r--r--arch/mips/alchemy/common/pci.c104
-rw-r--r--arch/mips/alchemy/common/platform.c370
-rw-r--r--arch/mips/alchemy/common/power.c46
-rw-r--r--arch/mips/alchemy/common/setup.c6
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c153
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c28
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c198
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c49
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c190
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c33
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c71
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c6
-rw-r--r--arch/mips/alchemy/devboards/pb1550/platform.c119
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c12
-rw-r--r--arch/mips/alchemy/gpr/platform.c47
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c40
-rw-r--r--arch/mips/alchemy/mtx-1/platform.c62
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c8
-rw-r--r--arch/mips/alchemy/xxs1500/platform.c12
24 files changed, 1019 insertions, 901 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2ccfd4a135bc..2a68be6a1b97 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -18,20 +18,20 @@ config MIPS_MTX1
18 bool "4G Systems MTX-1 board" 18 bool "4G Systems MTX-1 board"
19 select DMA_NONCOHERENT 19 select DMA_NONCOHERENT
20 select HW_HAS_PCI 20 select HW_HAS_PCI
21 select SOC_AU1500 21 select ALCHEMY_GPIOINT_AU1000
22 select SYS_SUPPORTS_LITTLE_ENDIAN 22 select SYS_SUPPORTS_LITTLE_ENDIAN
23 select SYS_HAS_EARLY_PRINTK 23 select SYS_HAS_EARLY_PRINTK
24 24
25config MIPS_BOSPORUS 25config MIPS_BOSPORUS
26 bool "Alchemy Bosporus board" 26 bool "Alchemy Bosporus board"
27 select SOC_AU1500 27 select ALCHEMY_GPIOINT_AU1000
28 select DMA_NONCOHERENT 28 select DMA_NONCOHERENT
29 select SYS_SUPPORTS_LITTLE_ENDIAN 29 select SYS_SUPPORTS_LITTLE_ENDIAN
30 select SYS_HAS_EARLY_PRINTK 30 select SYS_HAS_EARLY_PRINTK
31 31
32config MIPS_DB1000 32config MIPS_DB1000
33 bool "Alchemy DB1000 board" 33 bool "Alchemy DB1000 board"
34 select SOC_AU1000 34 select ALCHEMY_GPIOINT_AU1000
35 select DMA_NONCOHERENT 35 select DMA_NONCOHERENT
36 select HW_HAS_PCI 36 select HW_HAS_PCI
37 select SYS_SUPPORTS_LITTLE_ENDIAN 37 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -39,14 +39,14 @@ config MIPS_DB1000
39 39
40config MIPS_DB1100 40config MIPS_DB1100
41 bool "Alchemy DB1100 board" 41 bool "Alchemy DB1100 board"
42 select SOC_AU1100 42 select ALCHEMY_GPIOINT_AU1000
43 select DMA_NONCOHERENT 43 select DMA_NONCOHERENT
44 select SYS_SUPPORTS_LITTLE_ENDIAN 44 select SYS_SUPPORTS_LITTLE_ENDIAN
45 select SYS_HAS_EARLY_PRINTK 45 select SYS_HAS_EARLY_PRINTK
46 46
47config MIPS_DB1200 47config MIPS_DB1200
48 bool "Alchemy DB1200 board" 48 bool "Alchemy DB1200 board"
49 select SOC_AU1200 49 select ALCHEMY_GPIOINT_AU1000
50 select DMA_COHERENT 50 select DMA_COHERENT
51 select MIPS_DISABLE_OBSOLETE_IDE 51 select MIPS_DISABLE_OBSOLETE_IDE
52 select SYS_SUPPORTS_LITTLE_ENDIAN 52 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -54,7 +54,7 @@ config MIPS_DB1200
54 54
55config MIPS_DB1500 55config MIPS_DB1500
56 bool "Alchemy DB1500 board" 56 bool "Alchemy DB1500 board"
57 select SOC_AU1500 57 select ALCHEMY_GPIOINT_AU1000
58 select DMA_NONCOHERENT 58 select DMA_NONCOHERENT
59 select HW_HAS_PCI 59 select HW_HAS_PCI
60 select MIPS_DISABLE_OBSOLETE_IDE 60 select MIPS_DISABLE_OBSOLETE_IDE
@@ -64,7 +64,7 @@ config MIPS_DB1500
64 64
65config MIPS_DB1550 65config MIPS_DB1550
66 bool "Alchemy DB1550 board" 66 bool "Alchemy DB1550 board"
67 select SOC_AU1550 67 select ALCHEMY_GPIOINT_AU1000
68 select HW_HAS_PCI 68 select HW_HAS_PCI
69 select DMA_NONCOHERENT 69 select DMA_NONCOHERENT
70 select MIPS_DISABLE_OBSOLETE_IDE 70 select MIPS_DISABLE_OBSOLETE_IDE
@@ -74,13 +74,13 @@ config MIPS_DB1550
74config MIPS_MIRAGE 74config MIPS_MIRAGE
75 bool "Alchemy Mirage board" 75 bool "Alchemy Mirage board"
76 select DMA_NONCOHERENT 76 select DMA_NONCOHERENT
77 select SOC_AU1500 77 select ALCHEMY_GPIOINT_AU1000
78 select SYS_SUPPORTS_LITTLE_ENDIAN 78 select SYS_SUPPORTS_LITTLE_ENDIAN
79 select SYS_HAS_EARLY_PRINTK 79 select SYS_HAS_EARLY_PRINTK
80 80
81config MIPS_PB1000 81config MIPS_PB1000
82 bool "Alchemy PB1000 board" 82 bool "Alchemy PB1000 board"
83 select SOC_AU1000 83 select ALCHEMY_GPIOINT_AU1000
84 select DMA_NONCOHERENT 84 select DMA_NONCOHERENT
85 select HW_HAS_PCI 85 select HW_HAS_PCI
86 select SWAP_IO_SPACE 86 select SWAP_IO_SPACE
@@ -89,7 +89,7 @@ config MIPS_PB1000
89 89
90config MIPS_PB1100 90config MIPS_PB1100
91 bool "Alchemy PB1100 board" 91 bool "Alchemy PB1100 board"
92 select SOC_AU1100 92 select ALCHEMY_GPIOINT_AU1000
93 select DMA_NONCOHERENT 93 select DMA_NONCOHERENT
94 select HW_HAS_PCI 94 select HW_HAS_PCI
95 select SWAP_IO_SPACE 95 select SWAP_IO_SPACE
@@ -98,7 +98,7 @@ config MIPS_PB1100
98 98
99config MIPS_PB1200 99config MIPS_PB1200
100 bool "Alchemy PB1200 board" 100 bool "Alchemy PB1200 board"
101 select SOC_AU1200 101 select ALCHEMY_GPIOINT_AU1000
102 select DMA_NONCOHERENT 102 select DMA_NONCOHERENT
103 select MIPS_DISABLE_OBSOLETE_IDE 103 select MIPS_DISABLE_OBSOLETE_IDE
104 select SYS_SUPPORTS_LITTLE_ENDIAN 104 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -106,7 +106,7 @@ config MIPS_PB1200
106 106
107config MIPS_PB1500 107config MIPS_PB1500
108 bool "Alchemy PB1500 board" 108 bool "Alchemy PB1500 board"
109 select SOC_AU1500 109 select ALCHEMY_GPIOINT_AU1000
110 select DMA_NONCOHERENT 110 select DMA_NONCOHERENT
111 select HW_HAS_PCI 111 select HW_HAS_PCI
112 select SYS_SUPPORTS_LITTLE_ENDIAN 112 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -114,7 +114,7 @@ config MIPS_PB1500
114 114
115config MIPS_PB1550 115config MIPS_PB1550
116 bool "Alchemy PB1550 board" 116 bool "Alchemy PB1550 board"
117 select SOC_AU1550 117 select ALCHEMY_GPIOINT_AU1000
118 select DMA_NONCOHERENT 118 select DMA_NONCOHERENT
119 select HW_HAS_PCI 119 select HW_HAS_PCI
120 select MIPS_DISABLE_OBSOLETE_IDE 120 select MIPS_DISABLE_OBSOLETE_IDE
@@ -124,13 +124,13 @@ config MIPS_PB1550
124config MIPS_XXS1500 124config MIPS_XXS1500
125 bool "MyCable XXS1500 board" 125 bool "MyCable XXS1500 board"
126 select DMA_NONCOHERENT 126 select DMA_NONCOHERENT
127 select SOC_AU1500 127 select ALCHEMY_GPIOINT_AU1000
128 select SYS_SUPPORTS_LITTLE_ENDIAN 128 select SYS_SUPPORTS_LITTLE_ENDIAN
129 select SYS_HAS_EARLY_PRINTK 129 select SYS_HAS_EARLY_PRINTK
130 130
131config MIPS_GPR 131config MIPS_GPR
132 bool "Trapeze ITS GPR board" 132 bool "Trapeze ITS GPR board"
133 select SOC_AU1550 133 select ALCHEMY_GPIOINT_AU1000
134 select HW_HAS_PCI 134 select HW_HAS_PCI
135 select DMA_NONCOHERENT 135 select DMA_NONCOHERENT
136 select MIPS_DISABLE_OBSOLETE_IDE 136 select MIPS_DISABLE_OBSOLETE_IDE
@@ -138,23 +138,3 @@ config MIPS_GPR
138 select SYS_HAS_EARLY_PRINTK 138 select SYS_HAS_EARLY_PRINTK
139 139
140endchoice 140endchoice
141
142config SOC_AU1000
143 bool
144 select ALCHEMY_GPIOINT_AU1000
145
146config SOC_AU1100
147 bool
148 select ALCHEMY_GPIOINT_AU1000
149
150config SOC_AU1500
151 bool
152 select ALCHEMY_GPIOINT_AU1000
153
154config SOC_AU1550
155 bool
156 select ALCHEMY_GPIOINT_AU1000
157
158config SOC_AU1200
159 bool
160 select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 27811fe341d6..811ece7b22e3 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -12,9 +12,5 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
12 12
13# optional gpiolib support 13# optional gpiolib support
14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
15 ifeq ($(CONFIG_GPIOLIB),y) 15 obj-$(CONFIG_GPIOLIB) += gpiolib.o
16 obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
17 endif
18endif 16endif
19
20obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 3a5abb54d505..0e63ee487d6d 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -40,8 +40,6 @@
40#include <asm/mach-au1x00/au1000.h> 40#include <asm/mach-au1x00/au1000.h>
41#include <asm/mach-au1x00/au1xxx_dbdma.h> 41#include <asm/mach-au1x00/au1xxx_dbdma.h>
42 42
43#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
44
45/* 43/*
46 * The Descriptor Based DMA supports up to 16 channels. 44 * The Descriptor Based DMA supports up to 16 channels.
47 * 45 *
@@ -62,120 +60,96 @@ static dbdma_global_t *dbdma_gptr =
62 (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR); 60 (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
63static int dbdma_initialized; 61static int dbdma_initialized;
64 62
65static dbdev_tab_t dbdev_tab[] = { 63static dbdev_tab_t *dbdev_tab;
66#ifdef CONFIG_SOC_AU1550 64
65static dbdev_tab_t au1550_dbdev_tab[] __initdata = {
67 /* UARTS */ 66 /* UARTS */
68 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, 67 { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
69 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, 68 { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
70 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, 69 { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
71 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, 70 { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
72 71
73 /* EXT DMA */ 72 /* EXT DMA */
74 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, 73 { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
75 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, 74 { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
76 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, 75 { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
77 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, 76 { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
78 77
79 /* USB DEV */ 78 /* USB DEV */
80 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, 79 { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
81 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, 80 { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
82 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, 81 { AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
83 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, 82 { AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
84 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, 83 { AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
85 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, 84 { AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
86 85
87 /* PSC 0 */ 86 /* PSCs */
88 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, 87 { AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
89 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, 88 { AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
90 89 { AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
91 /* PSC 1 */ 90 { AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
92 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, 91 { AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
93 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, 92 { AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
94 93 { AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
95 /* PSC 2 */ 94 { AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
96 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, 95
97 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, 96 { AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
98 97 { AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
99 /* PSC 3 */
100 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
101 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
102
103 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
104 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
105 98
106 /* MAC 0 */ 99 /* MAC 0 */
107 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 100 { AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
108 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 101 { AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
109 102
110 /* MAC 1 */ 103 /* MAC 1 */
111 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 104 { AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
112 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 105 { AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
113
114#endif /* CONFIG_SOC_AU1550 */
115 106
116#ifdef CONFIG_SOC_AU1200 107 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
117 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, 108 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
118 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, 109};
119 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
120 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
121
122 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
123 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
124 110
125 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 111static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
126 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 112 { AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
127 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 113 { AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
128 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 114 { AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
115 { AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
129 116
130 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, 117 { AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
131 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, 118 { AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
132 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
133 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
134 119
135 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, 120 { AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
136 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, 121 { AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
122 { AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
123 { AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
137 124
138 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, 125 { AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
139 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, 126 { AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
140 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 127 { AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
128 { AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
141 129
142 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, 130 { AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
143 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, 131 { AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
144 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
145 132
146 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, 133 { AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
147 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, 134 { AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
148 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, 135 { AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 136 { AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
137 { AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
138 { AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
150 139
151 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 140 { AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
141 { AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
142 { AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
143 { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
152 144
153#endif /* CONFIG_SOC_AU1200 */ 145 { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
154 146
155 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 147 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
156 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
157
158 /* Provide 16 user definable device types */
159 { ~0, 0, 0, 0, 0, 0, 0 },
160 { ~0, 0, 0, 0, 0, 0, 0 },
161 { ~0, 0, 0, 0, 0, 0, 0 },
162 { ~0, 0, 0, 0, 0, 0, 0 },
163 { ~0, 0, 0, 0, 0, 0, 0 },
164 { ~0, 0, 0, 0, 0, 0, 0 },
165 { ~0, 0, 0, 0, 0, 0, 0 },
166 { ~0, 0, 0, 0, 0, 0, 0 },
167 { ~0, 0, 0, 0, 0, 0, 0 },
168 { ~0, 0, 0, 0, 0, 0, 0 },
169 { ~0, 0, 0, 0, 0, 0, 0 },
170 { ~0, 0, 0, 0, 0, 0, 0 },
171 { ~0, 0, 0, 0, 0, 0, 0 },
172 { ~0, 0, 0, 0, 0, 0, 0 },
173 { ~0, 0, 0, 0, 0, 0, 0 },
174 { ~0, 0, 0, 0, 0, 0, 0 },
175}; 149};
176 150
177#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) 151/* 32 predefined plus 32 custom */
178 152#define DBDEV_TAB_SIZE 64
179 153
180static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 154static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
181 155
@@ -1028,38 +1002,43 @@ static struct syscore_ops alchemy_dbdma_syscore_ops = {
1028 .resume = alchemy_dbdma_resume, 1002 .resume = alchemy_dbdma_resume,
1029}; 1003};
1030 1004
1031static int __init au1xxx_dbdma_init(void) 1005static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
1032{ 1006{
1033 int irq_nr, ret; 1007 int ret;
1008
1009 dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);
1010 if (!dbdev_tab)
1011 return -ENOMEM;
1012
1013 memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));
1014 for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
1015 dbdev_tab[ret].dev_id = ~0;
1034 1016
1035 dbdma_gptr->ddma_config = 0; 1017 dbdma_gptr->ddma_config = 0;
1036 dbdma_gptr->ddma_throttle = 0; 1018 dbdma_gptr->ddma_throttle = 0;
1037 dbdma_gptr->ddma_inten = 0xffff; 1019 dbdma_gptr->ddma_inten = 0xffff;
1038 au_sync(); 1020 au_sync();
1039 1021
1040 switch (alchemy_get_cputype()) { 1022 ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",
1041 case ALCHEMY_CPU_AU1550: 1023 (void *)dbdma_gptr);
1042 irq_nr = AU1550_DDMA_INT;
1043 break;
1044 case ALCHEMY_CPU_AU1200:
1045 irq_nr = AU1200_DDMA_INT;
1046 break;
1047 default:
1048 return -ENODEV;
1049 }
1050
1051 ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
1052 "Au1xxx dbdma", (void *)dbdma_gptr);
1053 if (ret) 1024 if (ret)
1054 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); 1025 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1055 else { 1026 else {
1056 dbdma_initialized = 1; 1027 dbdma_initialized = 1;
1057 printk(KERN_INFO "Alchemy DBDMA initialized\n");
1058 register_syscore_ops(&alchemy_dbdma_syscore_ops); 1028 register_syscore_ops(&alchemy_dbdma_syscore_ops);
1059 } 1029 }
1060 1030
1061 return ret; 1031 return ret;
1062} 1032}
1063subsys_initcall(au1xxx_dbdma_init);
1064 1033
1065#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 1034static int __init alchemy_dbdma_init(void)
1035{
1036 switch (alchemy_get_cputype()) {
1037 case ALCHEMY_CPU_AU1550:
1038 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
1039 case ALCHEMY_CPU_AU1200:
1040 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
1041 }
1042 return 0;
1043}
1044subsys_initcall(alchemy_dbdma_init);
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 347980e79a89..9b624e2c0fcf 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -40,8 +40,6 @@
40#include <asm/mach-au1x00/au1000.h> 40#include <asm/mach-au1x00/au1000.h>
41#include <asm/mach-au1x00/au1000_dma.h> 41#include <asm/mach-au1x00/au1000_dma.h>
42 42
43#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
44 defined(CONFIG_SOC_AU1100)
45/* 43/*
46 * A note on resource allocation: 44 * A note on resource allocation:
47 * 45 *
@@ -88,12 +86,12 @@ static const struct dma_dev {
88 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ 86 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
89 { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ 87 { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
90 { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ 88 { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
91 { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ 89 { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
92 { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ 90 { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
93 { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ 91 { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
94 { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ 92 { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
95 { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ 93 { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
96 { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ 94 { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
97 /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ 95 /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
98 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ 96 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
99 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ 97 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
@@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str,
170 const struct dma_dev *dev; 168 const struct dma_dev *dev;
171 int i, ret; 169 int i, ret;
172 170
173#if defined(CONFIG_SOC_AU1100) 171 if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
174 if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) 172 if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
175 return -EINVAL; 173 return -EINVAL;
176#else 174 } else {
177 if (dev_id < 0 || dev_id >= DMA_NUM_DEV) 175 if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
178 return -EINVAL; 176 return -EINVAL;
179#endif 177 }
180 178
181 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) 179 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
182 if (au1000_dma_table[i].dev_id < 0) 180 if (au1000_dma_table[i].dev_id < 0)
@@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma);
239 237
240static int __init au1000_dma_init(void) 238static int __init au1000_dma_init(void)
241{ 239{
242 int base, i; 240 int base, i;
243 241
244 switch (alchemy_get_cputype()) { 242 switch (alchemy_get_cputype()) {
245 case ALCHEMY_CPU_AU1000: 243 case ALCHEMY_CPU_AU1000:
246 base = AU1000_DMA_INT_BASE; 244 base = AU1000_DMA_INT_BASE;
247 break; 245 break;
248 case ALCHEMY_CPU_AU1500: 246 case ALCHEMY_CPU_AU1500:
249 base = AU1500_DMA_INT_BASE; 247 base = AU1500_DMA_INT_BASE;
250 break; 248 break;
251 case ALCHEMY_CPU_AU1100: 249 case ALCHEMY_CPU_AU1100:
252 base = AU1100_DMA_INT_BASE; 250 base = AU1100_DMA_INT_BASE;
253 break; 251 break;
254 default: 252 default:
255 goto out; 253 goto out;
256 } 254 }
257 255
258 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) 256 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
259 au1000_dma_table[i].irq = base + i; 257 au1000_dma_table[i].irq = base + i;
260 258
261 printk(KERN_INFO "Alchemy DMA initialized\n"); 259 printk(KERN_INFO "Alchemy DMA initialized\n");
262 260
263out: 261out:
264 return 0; 262 return 0;
265} 263}
266arch_initcall(au1000_dma_init); 264arch_initcall(au1000_dma_init);
267
268#endif /* AU1000 AU1500 AU1100 */
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib.c
index c8e1a94d4a95..91fb4d9e30fd 100644
--- a/arch/mips/alchemy/common/gpiolib-au1000.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> 2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0. 3 * GPIOLIB support for Alchemy chips.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -23,18 +23,18 @@
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 * 24 *
25 * Notes : 25 * Notes :
26 * au1000 SoC have only one GPIO block : GPIO1 26 * This file must ONLY be built when CONFIG_GPIOLIB=y and
27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
28 * au1000 SoC have only one GPIO block : GPIO1
29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
28 */ 30 */
29 31
32#include <linux/init.h>
30#include <linux/kernel.h> 33#include <linux/kernel.h>
31#include <linux/module.h> 34#include <linux/module.h>
32#include <linux/types.h> 35#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h> 36#include <linux/gpio.h>
35 37#include <asm/mach-au1x00/gpio-au1000.h>
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h>
38 38
39static int gpio2_get(struct gpio_chip *chip, unsigned offset) 39static int gpio2_get(struct gpio_chip *chip, unsigned offset)
40{ 40{
@@ -115,12 +115,19 @@ struct gpio_chip alchemy_gpio_chip[] = {
115 }, 115 },
116}; 116};
117 117
118static int __init alchemy_gpiolib_init(void) 118static int __init alchemy_gpiochip_init(void)
119{ 119{
120 gpiochip_add(&alchemy_gpio_chip[0]); 120 int ret = 0;
121 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000) 121
122 gpiochip_add(&alchemy_gpio_chip[1]); 122 switch (alchemy_get_cputype()) {
123 123 case ALCHEMY_CPU_AU1000:
124 return 0; 124 ret = gpiochip_add(&alchemy_gpio_chip[0]);
125 break;
126 case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
127 ret = gpiochip_add(&alchemy_gpio_chip[0]);
128 ret |= gpiochip_add(&alchemy_gpio_chip[1]);
129 break;
130 }
131 return ret;
125} 132}
126arch_initcall(alchemy_gpiolib_init); 133arch_initcall(alchemy_gpiochip_init);
diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c
deleted file mode 100644
index 7866cf50cf99..000000000000
--- a/arch/mips/alchemy/common/pci.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Alchemy/AMD Au1x00 PCI support.
4 *
5 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 *
10 * Support for all devices (greater than 16) added by David Gathright.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#include <linux/pci.h>
34#include <linux/kernel.h>
35#include <linux/init.h>
36
37#include <asm/mach-au1x00/au1000.h>
38
39/* TBD */
40static struct resource pci_io_resource = {
41 .start = PCI_IO_START,
42 .end = PCI_IO_END,
43 .name = "PCI IO space",
44 .flags = IORESOURCE_IO
45};
46
47static struct resource pci_mem_resource = {
48 .start = PCI_MEM_START,
49 .end = PCI_MEM_END,
50 .name = "PCI memory space",
51 .flags = IORESOURCE_MEM
52};
53
54extern struct pci_ops au1x_pci_ops;
55
56static struct pci_controller au1x_controller = {
57 .pci_ops = &au1x_pci_ops,
58 .io_resource = &pci_io_resource,
59 .mem_resource = &pci_mem_resource,
60};
61
62#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
63static unsigned long virt_io_addr;
64#endif
65
66static int __init au1x_pci_setup(void)
67{
68 extern void au1x_pci_cfg_init(void);
69
70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
73
74 if (!virt_io_addr) {
75 printk(KERN_ERR "Unable to ioremap pci space\n");
76 return 1;
77 }
78 au1x_controller.io_map_base = virt_io_addr;
79
80#ifdef CONFIG_DMA_NONCOHERENT
81 {
82 /*
83 * Set the NC bit in controller for Au1500 pre-AC silicon
84 */
85 u32 prid = read_c0_prid();
86
87 if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
88 au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
89 Au1500_PCI_CFG);
90 printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
91 }
92 }
93#endif
94
95 set_io_port_base(virt_io_addr);
96#endif
97
98 au1x_pci_cfg_init();
99
100 register_pci_controller(&au1x_controller);
101 return 0;
102}
103
104arch_initcall(au1x_pci_setup);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index f72c48d4804c..c8e5d72a5826 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -18,7 +18,7 @@
18#include <linux/serial_8250.h> 18#include <linux/serial_8250.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20 20
21#include <asm/mach-au1x00/au1xxx.h> 21#include <asm/mach-au1x00/au1000.h>
22#include <asm/mach-au1x00/au1xxx_dbdma.h> 22#include <asm/mach-au1x00/au1xxx_dbdma.h>
23#include <asm/mach-au1x00/au1100_mmc.h> 23#include <asm/mach-au1x00/au1100_mmc.h>
24#include <asm/mach-au1x00/au1xxx_eth.h> 24#include <asm/mach-au1x00/au1xxx_eth.h>
@@ -111,270 +111,87 @@ static void __init alchemy_setup_uarts(int ctype)
111 printk(KERN_INFO "Alchemy: failed to register UARTs\n"); 111 printk(KERN_INFO "Alchemy: failed to register UARTs\n");
112} 112}
113 113
114/* OHCI (USB full speed host controller) */
115static struct resource au1xxx_usb_ohci_resources[] = {
116 [0] = {
117 .start = USB_OHCI_BASE,
118 .end = USB_OHCI_BASE + USB_OHCI_LEN - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 [1] = {
122 .start = FOR_PLATFORM_C_USB_HOST_INT,
123 .end = FOR_PLATFORM_C_USB_HOST_INT,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128/* The dmamask must be set for OHCI to work */
129static u64 ohci_dmamask = DMA_BIT_MASK(32);
130
131static struct platform_device au1xxx_usb_ohci_device = {
132 .name = "au1xxx-ohci",
133 .id = 0,
134 .dev = {
135 .dma_mask = &ohci_dmamask,
136 .coherent_dma_mask = DMA_BIT_MASK(32),
137 },
138 .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
139 .resource = au1xxx_usb_ohci_resources,
140};
141
142/*** AU1100 LCD controller ***/
143
144#ifdef CONFIG_FB_AU1100
145static struct resource au1100_lcd_resources[] = {
146 [0] = {
147 .start = LCD_PHYS_ADDR,
148 .end = LCD_PHYS_ADDR + 0x800 - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = AU1100_LCD_INT,
153 .end = AU1100_LCD_INT,
154 .flags = IORESOURCE_IRQ,
155 }
156};
157
158static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
159
160static struct platform_device au1100_lcd_device = {
161 .name = "au1100-lcd",
162 .id = 0,
163 .dev = {
164 .dma_mask = &au1100_lcd_dmamask,
165 .coherent_dma_mask = DMA_BIT_MASK(32),
166 },
167 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
168 .resource = au1100_lcd_resources,
169};
170#endif
171
172#ifdef CONFIG_SOC_AU1200
173/* EHCI (USB high speed host controller) */
174static struct resource au1xxx_usb_ehci_resources[] = {
175 [0] = {
176 .start = USB_EHCI_BASE,
177 .end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = AU1200_USB_INT,
182 .end = AU1200_USB_INT,
183 .flags = IORESOURCE_IRQ,
184 },
185};
186
187static u64 ehci_dmamask = DMA_BIT_MASK(32);
188
189static struct platform_device au1xxx_usb_ehci_device = {
190 .name = "au1xxx-ehci",
191 .id = 0,
192 .dev = {
193 .dma_mask = &ehci_dmamask,
194 .coherent_dma_mask = DMA_BIT_MASK(32),
195 },
196 .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
197 .resource = au1xxx_usb_ehci_resources,
198};
199
200/* Au1200 UDC (USB gadget controller) */
201static struct resource au1xxx_usb_gdt_resources[] = {
202 [0] = {
203 .start = USB_UDC_BASE,
204 .end = USB_UDC_BASE + USB_UDC_LEN - 1,
205 .flags = IORESOURCE_MEM,
206 },
207 [1] = {
208 .start = AU1200_USB_INT,
209 .end = AU1200_USB_INT,
210 .flags = IORESOURCE_IRQ,
211 },
212};
213
214static u64 udc_dmamask = DMA_BIT_MASK(32);
215 114
216static struct platform_device au1xxx_usb_gdt_device = { 115/* The dmamask must be set for OHCI/EHCI to work */
217 .name = "au1xxx-udc", 116static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
218 .id = 0, 117static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
219 .dev = {
220 .dma_mask = &udc_dmamask,
221 .coherent_dma_mask = DMA_BIT_MASK(32),
222 },
223 .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
224 .resource = au1xxx_usb_gdt_resources,
225};
226 118
227/* Au1200 UOC (USB OTG controller) */ 119static unsigned long alchemy_ohci_data[][2] __initdata = {
228static struct resource au1xxx_usb_otg_resources[] = { 120 [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
229 [0] = { 121 [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
230 .start = USB_UOC_BASE, 122 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
231 .end = USB_UOC_BASE + USB_UOC_LEN - 1, 123 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
232 .flags = IORESOURCE_MEM, 124 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
233 },
234 [1] = {
235 .start = AU1200_USB_INT,
236 .end = AU1200_USB_INT,
237 .flags = IORESOURCE_IRQ,
238 },
239}; 125};
240 126
241static u64 uoc_dmamask = DMA_BIT_MASK(32); 127static unsigned long alchemy_ehci_data[][2] __initdata = {
242 128 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
243static struct platform_device au1xxx_usb_otg_device = {
244 .name = "au1xxx-uoc",
245 .id = 0,
246 .dev = {
247 .dma_mask = &uoc_dmamask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
249 },
250 .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
251 .resource = au1xxx_usb_otg_resources,
252}; 129};
253 130
254static struct resource au1200_lcd_resources[] = { 131static int __init _new_usbres(struct resource **r, struct platform_device **d)
255 [0] = { 132{
256 .start = LCD_PHYS_ADDR, 133 *r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
257 .end = LCD_PHYS_ADDR + 0x800 - 1, 134 if (!*r)
258 .flags = IORESOURCE_MEM, 135 return -ENOMEM;
259 }, 136 *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
260 [1] = { 137 if (!*d) {
261 .start = AU1200_LCD_INT, 138 kfree(*r);
262 .end = AU1200_LCD_INT, 139 return -ENOMEM;
263 .flags = IORESOURCE_IRQ,
264 } 140 }
265};
266
267static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
268
269static struct platform_device au1200_lcd_device = {
270 .name = "au1200-lcd",
271 .id = 0,
272 .dev = {
273 .dma_mask = &au1200_lcd_dmamask,
274 .coherent_dma_mask = DMA_BIT_MASK(32),
275 },
276 .num_resources = ARRAY_SIZE(au1200_lcd_resources),
277 .resource = au1200_lcd_resources,
278};
279 141
280static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 142 (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
143 (*d)->num_resources = 2;
144 (*d)->resource = *r;
281 145
282extern struct au1xmmc_platform_data au1xmmc_platdata[2]; 146 return 0;
147}
283 148
284static struct resource au1200_mmc0_resources[] = { 149static void __init alchemy_setup_usb(int ctype)
285 [0] = { 150{
286 .start = AU1100_SD0_PHYS_ADDR, 151 struct resource *res;
287 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 152 struct platform_device *pdev;
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = AU1200_SD_INT,
292 .end = AU1200_SD_INT,
293 .flags = IORESOURCE_IRQ,
294 },
295 [2] = {
296 .start = DSCR_CMD0_SDMS_TX0,
297 .end = DSCR_CMD0_SDMS_TX0,
298 .flags = IORESOURCE_DMA,
299 },
300 [3] = {
301 .start = DSCR_CMD0_SDMS_RX0,
302 .end = DSCR_CMD0_SDMS_RX0,
303 .flags = IORESOURCE_DMA,
304 }
305};
306 153
307static struct platform_device au1200_mmc0_device = { 154 /* setup OHCI0. Every variant has one */
308 .name = "au1xxx-mmc", 155 if (_new_usbres(&res, &pdev))
309 .id = 0, 156 return;
310 .dev = {
311 .dma_mask = &au1xxx_mmc_dmamask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 .platform_data = &au1xmmc_platdata[0],
314 },
315 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
316 .resource = au1200_mmc0_resources,
317};
318 157
319#ifndef CONFIG_MIPS_DB1200 158 res[0].start = alchemy_ohci_data[ctype][0];
320static struct resource au1200_mmc1_resources[] = { 159 res[0].end = res[0].start + 0x100 - 1;
321 [0] = { 160 res[0].flags = IORESOURCE_MEM;
322 .start = AU1100_SD1_PHYS_ADDR, 161 res[1].start = alchemy_ohci_data[ctype][1];
323 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 162 res[1].end = res[1].start;
324 .flags = IORESOURCE_MEM, 163 res[1].flags = IORESOURCE_IRQ;
325 }, 164 pdev->name = "au1xxx-ohci";
326 [1] = { 165 pdev->id = 0;
327 .start = AU1200_SD_INT, 166 pdev->dev.dma_mask = &alchemy_ohci_dmamask;
328 .end = AU1200_SD_INT, 167
329 .flags = IORESOURCE_IRQ, 168 if (platform_device_register(pdev))
330 }, 169 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
331 [2] = { 170
332 .start = DSCR_CMD0_SDMS_TX1, 171
333 .end = DSCR_CMD0_SDMS_TX1, 172 /* setup EHCI0: Au1200 */
334 .flags = IORESOURCE_DMA, 173 if (ctype == ALCHEMY_CPU_AU1200) {
335 }, 174 if (_new_usbres(&res, &pdev))
336 [3] = { 175 return;
337 .start = DSCR_CMD0_SDMS_RX1, 176
338 .end = DSCR_CMD0_SDMS_RX1, 177 res[0].start = alchemy_ehci_data[ctype][0];
339 .flags = IORESOURCE_DMA, 178 res[0].end = res[0].start + 0x100 - 1;
179 res[0].flags = IORESOURCE_MEM;
180 res[1].start = alchemy_ehci_data[ctype][1];
181 res[1].end = res[1].start;
182 res[1].flags = IORESOURCE_IRQ;
183 pdev->name = "au1xxx-ehci";
184 pdev->id = 0;
185 pdev->dev.dma_mask = &alchemy_ehci_dmamask;
186
187 if (platform_device_register(pdev))
188 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
340 } 189 }
341}; 190}
342
343static struct platform_device au1200_mmc1_device = {
344 .name = "au1xxx-mmc",
345 .id = 1,
346 .dev = {
347 .dma_mask = &au1xxx_mmc_dmamask,
348 .coherent_dma_mask = DMA_BIT_MASK(32),
349 .platform_data = &au1xmmc_platdata[1],
350 },
351 .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
352 .resource = au1200_mmc1_resources,
353};
354#endif /* #ifndef CONFIG_MIPS_DB1200 */
355#endif /* #ifdef CONFIG_SOC_AU1200 */
356
357/* All Alchemy demoboards with I2C have this #define in their headers */
358#ifdef SMBUS_PSC_BASE
359static struct resource pbdb_smbus_resources[] = {
360 {
361 .start = CPHYSADDR(SMBUS_PSC_BASE),
362 .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
363 .flags = IORESOURCE_MEM,
364 },
365};
366
367static struct platform_device pbdb_smbus_device = {
368 .name = "au1xpsc_smbus",
369 .id = 0, /* bus number */
370 .num_resources = ARRAY_SIZE(pbdb_smbus_resources),
371 .resource = pbdb_smbus_resources,
372};
373#endif
374 191
375/* Macro to help defining the Ethernet MAC resources */ 192/* Macro to help defining the Ethernet MAC resources */
376#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */ 193#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
377#define MAC_RES(_base, _enable, _irq) \ 194#define MAC_RES(_base, _enable, _irq, _macdma) \
378 { \ 195 { \
379 .start = _base, \ 196 .start = _base, \
380 .end = _base + 0xffff, \ 197 .end = _base + 0xffff, \
@@ -389,28 +206,37 @@ static struct platform_device pbdb_smbus_device = {
389 .start = _irq, \ 206 .start = _irq, \
390 .end = _irq, \ 207 .end = _irq, \
391 .flags = IORESOURCE_IRQ \ 208 .flags = IORESOURCE_IRQ \
209 }, \
210 { \
211 .start = _macdma, \
212 .end = _macdma + 0x1ff, \
213 .flags = IORESOURCE_MEM, \
392 } 214 }
393 215
394static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = { 216static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
395 [ALCHEMY_CPU_AU1000] = { 217 [ALCHEMY_CPU_AU1000] = {
396 MAC_RES(AU1000_MAC0_PHYS_ADDR, 218 MAC_RES(AU1000_MAC0_PHYS_ADDR,
397 AU1000_MACEN_PHYS_ADDR, 219 AU1000_MACEN_PHYS_ADDR,
398 AU1000_MAC0_DMA_INT) 220 AU1000_MAC0_DMA_INT,
221 AU1000_MACDMA0_PHYS_ADDR)
399 }, 222 },
400 [ALCHEMY_CPU_AU1500] = { 223 [ALCHEMY_CPU_AU1500] = {
401 MAC_RES(AU1500_MAC0_PHYS_ADDR, 224 MAC_RES(AU1500_MAC0_PHYS_ADDR,
402 AU1500_MACEN_PHYS_ADDR, 225 AU1500_MACEN_PHYS_ADDR,
403 AU1500_MAC0_DMA_INT) 226 AU1500_MAC0_DMA_INT,
227 AU1000_MACDMA0_PHYS_ADDR)
404 }, 228 },
405 [ALCHEMY_CPU_AU1100] = { 229 [ALCHEMY_CPU_AU1100] = {
406 MAC_RES(AU1000_MAC0_PHYS_ADDR, 230 MAC_RES(AU1000_MAC0_PHYS_ADDR,
407 AU1000_MACEN_PHYS_ADDR, 231 AU1000_MACEN_PHYS_ADDR,
408 AU1100_MAC0_DMA_INT) 232 AU1100_MAC0_DMA_INT,
233 AU1000_MACDMA0_PHYS_ADDR)
409 }, 234 },
410 [ALCHEMY_CPU_AU1550] = { 235 [ALCHEMY_CPU_AU1550] = {
411 MAC_RES(AU1000_MAC0_PHYS_ADDR, 236 MAC_RES(AU1000_MAC0_PHYS_ADDR,
412 AU1000_MACEN_PHYS_ADDR, 237 AU1000_MACEN_PHYS_ADDR,
413 AU1550_MAC0_DMA_INT) 238 AU1550_MAC0_DMA_INT,
239 AU1000_MACDMA0_PHYS_ADDR)
414 }, 240 },
415}; 241};
416 242
@@ -429,17 +255,20 @@ static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
429 [ALCHEMY_CPU_AU1000] = { 255 [ALCHEMY_CPU_AU1000] = {
430 MAC_RES(AU1000_MAC1_PHYS_ADDR, 256 MAC_RES(AU1000_MAC1_PHYS_ADDR,
431 AU1000_MACEN_PHYS_ADDR + 4, 257 AU1000_MACEN_PHYS_ADDR + 4,
432 AU1000_MAC1_DMA_INT) 258 AU1000_MAC1_DMA_INT,
259 AU1000_MACDMA1_PHYS_ADDR)
433 }, 260 },
434 [ALCHEMY_CPU_AU1500] = { 261 [ALCHEMY_CPU_AU1500] = {
435 MAC_RES(AU1500_MAC1_PHYS_ADDR, 262 MAC_RES(AU1500_MAC1_PHYS_ADDR,
436 AU1500_MACEN_PHYS_ADDR + 4, 263 AU1500_MACEN_PHYS_ADDR + 4,
437 AU1500_MAC1_DMA_INT) 264 AU1500_MAC1_DMA_INT,
265 AU1000_MACDMA1_PHYS_ADDR)
438 }, 266 },
439 [ALCHEMY_CPU_AU1550] = { 267 [ALCHEMY_CPU_AU1550] = {
440 MAC_RES(AU1000_MAC1_PHYS_ADDR, 268 MAC_RES(AU1000_MAC1_PHYS_ADDR,
441 AU1000_MACEN_PHYS_ADDR + 4, 269 AU1000_MACEN_PHYS_ADDR + 4,
442 AU1550_MAC1_DMA_INT) 270 AU1550_MAC1_DMA_INT,
271 AU1000_MACDMA1_PHYS_ADDR)
443 }, 272 },
444}; 273};
445 274
@@ -521,36 +350,15 @@ static void __init alchemy_setup_macs(int ctype)
521 } 350 }
522} 351}
523 352
524static struct platform_device *au1xxx_platform_devices[] __initdata = {
525 &au1xxx_usb_ohci_device,
526#ifdef CONFIG_FB_AU1100
527 &au1100_lcd_device,
528#endif
529#ifdef CONFIG_SOC_AU1200
530 &au1xxx_usb_ehci_device,
531 &au1xxx_usb_gdt_device,
532 &au1xxx_usb_otg_device,
533 &au1200_lcd_device,
534 &au1200_mmc0_device,
535#ifndef CONFIG_MIPS_DB1200
536 &au1200_mmc1_device,
537#endif
538#endif
539#ifdef SMBUS_PSC_BASE
540 &pbdb_smbus_device,
541#endif
542};
543
544static int __init au1xxx_platform_init(void) 353static int __init au1xxx_platform_init(void)
545{ 354{
546 int err, ctype = alchemy_get_cputype(); 355 int ctype = alchemy_get_cputype();
547 356
548 alchemy_setup_uarts(ctype); 357 alchemy_setup_uarts(ctype);
549 alchemy_setup_macs(ctype); 358 alchemy_setup_macs(ctype);
359 alchemy_setup_usb(ctype);
550 360
551 err = platform_add_devices(au1xxx_platform_devices, 361 return 0;
552 ARRAY_SIZE(au1xxx_platform_devices));
553 return err;
554} 362}
555 363
556arch_initcall(au1xxx_platform_init); 364arch_initcall(au1xxx_platform_init);
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index b86324a42601..bdd6651e9a4f 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -37,8 +37,6 @@
37#include <asm/uaccess.h> 37#include <asm/uaccess.h>
38#include <asm/mach-au1x00/au1000.h> 38#include <asm/mach-au1x00/au1000.h>
39 39
40#ifdef CONFIG_PM
41
42/* 40/*
43 * We need to save/restore a bunch of core registers that are 41 * We need to save/restore a bunch of core registers that are
44 * either volatile or reset to some state across a processor sleep. 42 * either volatile or reset to some state across a processor sleep.
@@ -49,7 +47,6 @@
49 * We only have to save/restore registers that aren't otherwise 47 * We only have to save/restore registers that aren't otherwise
50 * done as part of a driver pm_* function. 48 * done as part of a driver pm_* function.
51 */ 49 */
52static unsigned int sleep_usb[2];
53static unsigned int sleep_sys_clocks[5]; 50static unsigned int sleep_sys_clocks[5];
54static unsigned int sleep_sys_pinfunc; 51static unsigned int sleep_sys_pinfunc;
55static unsigned int sleep_static_memctlr[4][3]; 52static unsigned int sleep_static_memctlr[4][3];
@@ -57,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3];
57 54
58static void save_core_regs(void) 55static void save_core_regs(void)
59{ 56{
60#ifndef CONFIG_SOC_AU1200
61 /* Shutdown USB host/device. */
62 sleep_usb[0] = au_readl(USB_HOST_CONFIG);
63
64 /* There appears to be some undocumented reset register.... */
65 au_writel(0, 0xb0100004);
66 au_sync();
67 au_writel(0, USB_HOST_CONFIG);
68 au_sync();
69
70 sleep_usb[1] = au_readl(USBD_ENABLE);
71 au_writel(0, USBD_ENABLE);
72 au_sync();
73
74#else /* AU1200 */
75
76 /* enable access to OTG mmio so we can save OTG CAP/MUX.
77 * FIXME: write an OTG driver and move this stuff there!
78 */
79 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
80 au_sync();
81 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
82 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
83#endif
84
85 /* Clocks and PLLs. */ 57 /* Clocks and PLLs. */
86 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); 58 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
87 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); 59 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
@@ -125,22 +97,6 @@ static void restore_core_regs(void)
125 au_writel(sleep_sys_pinfunc, SYS_PINFUNC); 97 au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
126 au_sync(); 98 au_sync();
127 99
128#ifndef CONFIG_SOC_AU1200
129 au_writel(sleep_usb[0], USB_HOST_CONFIG);
130 au_writel(sleep_usb[1], USBD_ENABLE);
131 au_sync();
132#else
133 /* enable access to OTG memory */
134 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
135 au_sync();
136
137 /* restore OTG caps and port mux. */
138 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
139 au_sync();
140 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
141 au_sync();
142#endif
143
144 /* Restore the static memory controller configuration. */ 100 /* Restore the static memory controller configuration. */
145 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 101 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
146 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); 102 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
@@ -174,5 +130,3 @@ void au_sleep(void)
174 130
175 restore_core_regs(); 131 restore_core_regs();
176} 132}
177
178#endif /* CONFIG_PM */
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1b887c868417..37ffd997c616 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -73,8 +73,8 @@ void __init plat_mem_setup(void)
73/* This routine should be valid for all Au1x based boards */ 73/* This routine should be valid for all Au1x based boards */
74phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 74phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
75{ 75{
76 u32 start = (u32)Au1500_PCI_MEM_START; 76 unsigned long start = ALCHEMY_PCI_MEMWIN_START;
77 u32 end = (u32)Au1500_PCI_MEM_END; 77 unsigned long end = ALCHEMY_PCI_MEMWIN_END;
78 78
79 /* Don't fixup 36-bit addresses */ 79 /* Don't fixup 36-bit addresses */
80 if ((phys_addr >> 32) != 0) 80 if ((phys_addr >> 32) != 0)
@@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
82 82
83 /* Check for PCI memory window */ 83 /* Check for PCI memory window */
84 if (phys_addr >= start && (phys_addr + size - 1) <= end) 84 if (phys_addr >= start && (phys_addr + size - 1) <= end)
85 return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START); 85 return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
86 86
87 /* default nop */ 87 /* default nop */
88 return phys_addr; 88 return phys_addr;
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index dda090bf74e6..c61867c93c4a 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -213,7 +213,12 @@ static struct resource db1200_ide_res[] = {
213 .start = DB1200_IDE_INT, 213 .start = DB1200_IDE_INT,
214 .end = DB1200_IDE_INT, 214 .end = DB1200_IDE_INT,
215 .flags = IORESOURCE_IRQ, 215 .flags = IORESOURCE_IRQ,
216 } 216 },
217 [2] = {
218 .start = AU1200_DSCR_CMD0_DMA_REQ1,
219 .end = AU1200_DSCR_CMD0_DMA_REQ1,
220 .flags = IORESOURCE_DMA,
221 },
217}; 222};
218 223
219static u64 ide_dmamask = DMA_BIT_MASK(32); 224static u64 ide_dmamask = DMA_BIT_MASK(32);
@@ -328,23 +333,85 @@ static struct led_classdev db1200_mmc_led = {
328 .brightness_set = db1200_mmcled_set, 333 .brightness_set = db1200_mmcled_set,
329}; 334};
330 335
331/* needed by arch/mips/alchemy/common/platform.c */ 336static struct au1xmmc_platform_data db1200mmc_platdata = {
332struct au1xmmc_platform_data au1xmmc_platdata[] = { 337 .cd_setup = db1200_mmc_cd_setup,
338 .set_power = db1200_mmc_set_power,
339 .card_inserted = db1200_mmc_card_inserted,
340 .card_readonly = db1200_mmc_card_readonly,
341 .led = &db1200_mmc_led,
342};
343
344static struct resource au1200_mmc0_resources[] = {
333 [0] = { 345 [0] = {
334 .cd_setup = db1200_mmc_cd_setup, 346 .start = AU1100_SD0_PHYS_ADDR,
335 .set_power = db1200_mmc_set_power, 347 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
336 .card_inserted = db1200_mmc_card_inserted, 348 .flags = IORESOURCE_MEM,
337 .card_readonly = db1200_mmc_card_readonly, 349 },
338 .led = &db1200_mmc_led, 350 [1] = {
351 .start = AU1200_SD_INT,
352 .end = AU1200_SD_INT,
353 .flags = IORESOURCE_IRQ,
354 },
355 [2] = {
356 .start = AU1200_DSCR_CMD0_SDMS_TX0,
357 .end = AU1200_DSCR_CMD0_SDMS_TX0,
358 .flags = IORESOURCE_DMA,
359 },
360 [3] = {
361 .start = AU1200_DSCR_CMD0_SDMS_RX0,
362 .end = AU1200_DSCR_CMD0_SDMS_RX0,
363 .flags = IORESOURCE_DMA,
364 }
365};
366
367static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
368
369static struct platform_device db1200_mmc0_dev = {
370 .name = "au1xxx-mmc",
371 .id = 0,
372 .dev = {
373 .dma_mask = &au1xxx_mmc_dmamask,
374 .coherent_dma_mask = DMA_BIT_MASK(32),
375 .platform_data = &db1200mmc_platdata,
376 },
377 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
378 .resource = au1200_mmc0_resources,
379};
380
381/**********************************************************************/
382
383static struct resource au1200_lcd_res[] = {
384 [0] = {
385 .start = AU1200_LCD_PHYS_ADDR,
386 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
387 .flags = IORESOURCE_MEM,
388 },
389 [1] = {
390 .start = AU1200_LCD_INT,
391 .end = AU1200_LCD_INT,
392 .flags = IORESOURCE_IRQ,
393 }
394};
395
396static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
397
398static struct platform_device au1200_lcd_dev = {
399 .name = "au1200-lcd",
400 .id = 0,
401 .dev = {
402 .dma_mask = &au1200_lcd_dmamask,
403 .coherent_dma_mask = DMA_BIT_MASK(32),
339 }, 404 },
405 .num_resources = ARRAY_SIZE(au1200_lcd_res),
406 .resource = au1200_lcd_res,
340}; 407};
341 408
342/**********************************************************************/ 409/**********************************************************************/
343 410
344static struct resource au1200_psc0_res[] = { 411static struct resource au1200_psc0_res[] = {
345 [0] = { 412 [0] = {
346 .start = PSC0_PHYS_ADDR, 413 .start = AU1550_PSC0_PHYS_ADDR,
347 .end = PSC0_PHYS_ADDR + 0x000fffff, 414 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
348 .flags = IORESOURCE_MEM, 415 .flags = IORESOURCE_MEM,
349 }, 416 },
350 [1] = { 417 [1] = {
@@ -353,13 +420,13 @@ static struct resource au1200_psc0_res[] = {
353 .flags = IORESOURCE_IRQ, 420 .flags = IORESOURCE_IRQ,
354 }, 421 },
355 [2] = { 422 [2] = {
356 .start = DSCR_CMD0_PSC0_TX, 423 .start = AU1200_DSCR_CMD0_PSC0_TX,
357 .end = DSCR_CMD0_PSC0_TX, 424 .end = AU1200_DSCR_CMD0_PSC0_TX,
358 .flags = IORESOURCE_DMA, 425 .flags = IORESOURCE_DMA,
359 }, 426 },
360 [3] = { 427 [3] = {
361 .start = DSCR_CMD0_PSC0_RX, 428 .start = AU1200_DSCR_CMD0_PSC0_RX,
362 .end = DSCR_CMD0_PSC0_RX, 429 .end = AU1200_DSCR_CMD0_PSC0_RX,
363 .flags = IORESOURCE_DMA, 430 .flags = IORESOURCE_DMA,
364 }, 431 },
365}; 432};
@@ -401,8 +468,8 @@ static struct platform_device db1200_spi_dev = {
401 468
402static struct resource au1200_psc1_res[] = { 469static struct resource au1200_psc1_res[] = {
403 [0] = { 470 [0] = {
404 .start = PSC1_PHYS_ADDR, 471 .start = AU1550_PSC1_PHYS_ADDR,
405 .end = PSC1_PHYS_ADDR + 0x000fffff, 472 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
406 .flags = IORESOURCE_MEM, 473 .flags = IORESOURCE_MEM,
407 }, 474 },
408 [1] = { 475 [1] = {
@@ -411,13 +478,13 @@ static struct resource au1200_psc1_res[] = {
411 .flags = IORESOURCE_IRQ, 478 .flags = IORESOURCE_IRQ,
412 }, 479 },
413 [2] = { 480 [2] = {
414 .start = DSCR_CMD0_PSC1_TX, 481 .start = AU1200_DSCR_CMD0_PSC1_TX,
415 .end = DSCR_CMD0_PSC1_TX, 482 .end = AU1200_DSCR_CMD0_PSC1_TX,
416 .flags = IORESOURCE_DMA, 483 .flags = IORESOURCE_DMA,
417 }, 484 },
418 [3] = { 485 [3] = {
419 .start = DSCR_CMD0_PSC1_RX, 486 .start = AU1200_DSCR_CMD0_PSC1_RX,
420 .end = DSCR_CMD0_PSC1_RX, 487 .end = AU1200_DSCR_CMD0_PSC1_RX,
421 .flags = IORESOURCE_DMA, 488 .flags = IORESOURCE_DMA,
422 }, 489 },
423}; 490};
@@ -449,6 +516,8 @@ static struct platform_device db1200_audiodma_dev = {
449static struct platform_device *db1200_devs[] __initdata = { 516static struct platform_device *db1200_devs[] __initdata = {
450 NULL, /* PSC0, selected by S6.8 */ 517 NULL, /* PSC0, selected by S6.8 */
451 &db1200_ide_dev, 518 &db1200_ide_dev,
519 &db1200_mmc0_dev,
520 &au1200_lcd_dev,
452 &db1200_eth_dev, 521 &db1200_eth_dev,
453 &db1200_rtc_dev, 522 &db1200_rtc_dev,
454 &db1200_nand_dev, 523 &db1200_nand_dev,
@@ -526,32 +595,28 @@ static int __init db1200_dev_init(void)
526 595
527 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 596 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
528 __raw_writel(PSC_SEL_CLK_SERCLK, 597 __raw_writel(PSC_SEL_CLK_SERCLK,
529 (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 598 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
530 wmb(); 599 wmb();
531 600
532 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 601 db1x_register_pcmcia_socket(
533 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 602 AU1000_PCMCIA_ATTR_PHYS_ADDR,
534 PCMCIA_MEM_PHYS_ADDR, 603 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
535 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 604 AU1000_PCMCIA_MEM_PHYS_ADDR,
536 PCMCIA_IO_PHYS_ADDR, 605 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
537 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 606 AU1000_PCMCIA_IO_PHYS_ADDR,
538 DB1200_PC0_INT, 607 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
539 DB1200_PC0_INSERT_INT, 608 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
540 /*DB1200_PC0_STSCHG_INT*/0, 609 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
541 DB1200_PC0_EJECT_INT, 610
542 0); 611 db1x_register_pcmcia_socket(
543 612 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
544 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 613 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
545 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 614 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
546 PCMCIA_MEM_PHYS_ADDR + 0x004000000, 615 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
547 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 616 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
548 PCMCIA_IO_PHYS_ADDR + 0x004000000, 617 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
549 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 618 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
550 DB1200_PC1_INT, 619 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
551 DB1200_PC1_INSERT_INT,
552 /*DB1200_PC1_STSCHG_INT*/0,
553 DB1200_PC1_EJECT_INT,
554 1);
555 620
556 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 621 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
557 db1x_register_norflash(64 << 20, 2, swapped); 622 db1x_register_norflash(64 << 20, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 5c956fe8760f..7cd36e631f6c 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -40,24 +40,6 @@
40 40
41#include <prom.h> 41#include <prom.h>
42 42
43#ifdef CONFIG_MIPS_DB1500
44char irq_tab_alchemy[][5] __initdata = {
45 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
46 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
47};
48
49#endif
50
51
52#ifdef CONFIG_MIPS_DB1550
53char irq_tab_alchemy[][5] __initdata = {
54 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
55 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
56 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
57};
58#endif
59
60
61#ifdef CONFIG_MIPS_BOSPORUS 43#ifdef CONFIG_MIPS_BOSPORUS
62char irq_tab_alchemy[][5] __initdata = { 44char irq_tab_alchemy[][5] __initdata = {
63 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ 45 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
@@ -91,12 +73,6 @@ const char *get_system_type(void)
91 73
92 74
93#ifdef CONFIG_MIPS_MIRAGE 75#ifdef CONFIG_MIPS_MIRAGE
94char irq_tab_alchemy[][5] __initdata = {
95 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
96 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
97 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
98};
99
100static void mirage_power_off(void) 76static void mirage_power_off(void)
101{ 77{
102 alchemy_gpio_direction_output(210, 1); 78 alchemy_gpio_direction_output(210, 1);
@@ -158,9 +134,7 @@ void __init board_setup(void)
158 /* initialize board register space */ 134 /* initialize board register space */
159 bcsr_init(bcsr1, bcsr2); 135 bcsr_init(bcsr1, bcsr2);
160 136
161 /* Not valid for Au1550 */ 137#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
162#if defined(CONFIG_IRDA) && \
163 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
164 { 138 {
165 u32 pin_func; 139 u32 pin_func;
166 140
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index 7057d28f7301..9e6b3d442acd 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -20,14 +20,16 @@
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/dma-mapping.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24 25
25#include <asm/mach-au1x00/au1000.h> 26#include <asm/mach-au1x00/au1000.h>
26#include <asm/mach-au1x00/au1000_dma.h> 27#include <asm/mach-au1x00/au1000_dma.h>
27#include <asm/mach-au1x00/au1xxx.h>
28#include <asm/mach-db1x00/bcsr.h> 28#include <asm/mach-db1x00/bcsr.h>
29#include "../platform.h" 29#include "../platform.h"
30 30
31struct pci_dev;
32
31/* DB1xxx PCMCIA interrupt sources: 33/* DB1xxx PCMCIA interrupt sources:
32 * CD0/1 GPIO0/3 34 * CD0/1 GPIO0/3
33 * STSCHG0/1 GPIO1/4 35 * STSCHG0/1 GPIO1/4
@@ -88,6 +90,155 @@
88#endif 90#endif
89#endif 91#endif
90 92
93#ifdef CONFIG_PCI
94#ifdef CONFIG_MIPS_DB1500
95static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
96{
97 if ((slot < 12) || (slot > 13) || pin == 0)
98 return -1;
99 if (slot == 12)
100 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
101 if (slot == 13) {
102 switch (pin) {
103 case 1: return AU1500_PCI_INTA;
104 case 2: return AU1500_PCI_INTB;
105 case 3: return AU1500_PCI_INTC;
106 case 4: return AU1500_PCI_INTD;
107 }
108 }
109 return -1;
110}
111#endif
112
113#ifdef CONFIG_MIPS_DB1550
114static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
115{
116 if ((slot < 11) || (slot > 13) || pin == 0)
117 return -1;
118 if (slot == 11)
119 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
120 if (slot == 12) {
121 switch (pin) {
122 case 1: return AU1550_PCI_INTB;
123 case 2: return AU1550_PCI_INTC;
124 case 3: return AU1550_PCI_INTD;
125 case 4: return AU1550_PCI_INTA;
126 }
127 }
128 if (slot == 13) {
129 switch (pin) {
130 case 1: return AU1550_PCI_INTA;
131 case 2: return AU1550_PCI_INTB;
132 case 3: return AU1550_PCI_INTC;
133 case 4: return AU1550_PCI_INTD;
134 }
135 }
136 return -1;
137}
138#endif
139
140#ifdef CONFIG_MIPS_BOSPORUS
141static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
142{
143 if ((slot < 11) || (slot > 13) || pin == 0)
144 return -1;
145 if (slot == 12)
146 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
147 if (slot == 11) {
148 switch (pin) {
149 case 1: return AU1500_PCI_INTA;
150 case 2: return AU1500_PCI_INTB;
151 default: return 0xff;
152 }
153 }
154 if (slot == 13) {
155 switch (pin) {
156 case 1: return AU1500_PCI_INTA;
157 case 2: return AU1500_PCI_INTB;
158 case 3: return AU1500_PCI_INTC;
159 case 4: return AU1500_PCI_INTD;
160 }
161 }
162 return -1;
163}
164#endif
165
166#ifdef CONFIG_MIPS_MIRAGE
167static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
168{
169 if ((slot < 11) || (slot > 13) || pin == 0)
170 return -1;
171 if (slot == 11)
172 return (pin == 1) ? AU1500_PCI_INTD : 0xff;
173 if (slot == 12)
174 return (pin == 3) ? AU1500_PCI_INTC : 0xff;
175 if (slot == 13) {
176 switch (pin) {
177 case 1: return AU1500_PCI_INTA;
178 case 2: return AU1500_PCI_INTB;
179 default: return 0xff;
180 }
181 }
182 return -1;
183}
184#endif
185
186static struct resource alchemy_pci_host_res[] = {
187 [0] = {
188 .start = AU1500_PCI_PHYS_ADDR,
189 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
190 .flags = IORESOURCE_MEM,
191 },
192};
193
194static struct alchemy_pci_platdata db1xxx_pci_pd = {
195 .board_map_irq = db1xxx_map_pci_irq,
196};
197
198static struct platform_device db1xxx_pci_host_dev = {
199 .dev.platform_data = &db1xxx_pci_pd,
200 .name = "alchemy-pci",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
203 .resource = alchemy_pci_host_res,
204};
205
206static int __init db15x0_pci_init(void)
207{
208 return platform_device_register(&db1xxx_pci_host_dev);
209}
210/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
211arch_initcall(db15x0_pci_init);
212#endif
213
214#ifdef CONFIG_MIPS_DB1100
215static struct resource au1100_lcd_resources[] = {
216 [0] = {
217 .start = AU1100_LCD_PHYS_ADDR,
218 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 [1] = {
222 .start = AU1100_LCD_INT,
223 .end = AU1100_LCD_INT,
224 .flags = IORESOURCE_IRQ,
225 }
226};
227
228static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
229
230static struct platform_device au1100_lcd_device = {
231 .name = "au1100-lcd",
232 .id = 0,
233 .dev = {
234 .dma_mask = &au1100_lcd_dmamask,
235 .coherent_dma_mask = DMA_BIT_MASK(32),
236 },
237 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
238 .resource = au1100_lcd_resources,
239};
240#endif
241
91static struct resource alchemy_ac97c_res[] = { 242static struct resource alchemy_ac97c_res[] = {
92 [0] = { 243 [0] = {
93 .start = AU1000_AC97_PHYS_ADDR, 244 .start = AU1000_AC97_PHYS_ADDR,
@@ -130,29 +281,28 @@ static struct platform_device db1x00_audio_dev = {
130static int __init db1xxx_dev_init(void) 281static int __init db1xxx_dev_init(void)
131{ 282{
132#ifdef DB1XXX_HAS_PCMCIA 283#ifdef DB1XXX_HAS_PCMCIA
133 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 284 db1x_register_pcmcia_socket(
134 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 285 AU1000_PCMCIA_ATTR_PHYS_ADDR,
135 PCMCIA_MEM_PHYS_ADDR, 286 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
136 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 287 AU1000_PCMCIA_MEM_PHYS_ADDR,
137 PCMCIA_IO_PHYS_ADDR, 288 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
138 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 289 AU1000_PCMCIA_IO_PHYS_ADDR,
139 DB1XXX_PCMCIA_CARD0, 290 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
140 DB1XXX_PCMCIA_CD0, 291 DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
141 /*DB1XXX_PCMCIA_STSCHG0*/0, 292 /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
142 0, 293
143 0); 294 db1x_register_pcmcia_socket(
144 295 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
145 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 296 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
146 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 297 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
147 PCMCIA_MEM_PHYS_ADDR + 0x004000000, 298 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
148 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 299 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
149 PCMCIA_IO_PHYS_ADDR + 0x004000000, 300 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
150 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 301 DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
151 DB1XXX_PCMCIA_CARD1, 302 /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
152 DB1XXX_PCMCIA_CD1, 303#endif
153 /*DB1XXX_PCMCIA_STSCHG1*/0, 304#ifdef CONFIG_MIPS_DB1100
154 0, 305 platform_device_register(&au1100_lcd_device);
155 1);
156#endif 306#endif
157 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); 307 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
158 308
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
index 2c8dc29759fd..9c57c01a68c4 100644
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -19,31 +19,58 @@
19 */ 19 */
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/dma-mapping.h>
23#include <linux/platform_device.h>
22 24
23#include <asm/mach-au1x00/au1000.h> 25#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-db1x00/bcsr.h> 26#include <asm/mach-db1x00/bcsr.h>
25 27
26#include "../platform.h" 28#include "../platform.h"
27 29
30static struct resource au1100_lcd_resources[] = {
31 [0] = {
32 .start = AU1100_LCD_PHYS_ADDR,
33 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 [1] = {
37 .start = AU1100_LCD_INT,
38 .end = AU1100_LCD_INT,
39 .flags = IORESOURCE_IRQ,
40 }
41};
42
43static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
44
45static struct platform_device au1100_lcd_device = {
46 .name = "au1100-lcd",
47 .id = 0,
48 .dev = {
49 .dma_mask = &au1100_lcd_dmamask,
50 .coherent_dma_mask = DMA_BIT_MASK(32),
51 },
52 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
53 .resource = au1100_lcd_resources,
54};
55
28static int __init pb1100_dev_init(void) 56static int __init pb1100_dev_init(void)
29{ 57{
30 int swapped; 58 int swapped;
31 59
32 /* PCMCIA. single socket, identical to Pb1500 */ 60 /* PCMCIA. single socket, identical to Pb1500 */
33 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 61 db1x_register_pcmcia_socket(
34 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 62 AU1000_PCMCIA_ATTR_PHYS_ADDR,
35 PCMCIA_MEM_PHYS_ADDR, 63 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
36 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 64 AU1000_PCMCIA_MEM_PHYS_ADDR,
37 PCMCIA_IO_PHYS_ADDR, 65 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
38 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 66 AU1000_PCMCIA_IO_PHYS_ADDR,
39 AU1100_GPIO11_INT, /* card */ 67 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
40 AU1100_GPIO9_INT, /* insert */ 68 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
41 /*AU1100_GPIO10_INT*/0, /* stschg */ 69 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
42 0, /* eject */
43 0); /* id */
44 70
45 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 71 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
46 db1x_register_norflash(64 * 1024 * 1024, 4, swapped); 72 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
73 platform_device_register(&au1100_lcd_device);
47 74
48 return 0; 75 return 0;
49} 76}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 3ef2dceeb796..54f7f7b0676e 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -24,9 +24,11 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/smc91x.h> 25#include <linux/smc91x.h>
26 26
27#include <asm/mach-au1x00/au1xxx.h> 27#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1100_mmc.h> 28#include <asm/mach-au1x00/au1100_mmc.h>
29#include <asm/mach-au1x00/au1xxx_dbdma.h>
29#include <asm/mach-db1x00/bcsr.h> 30#include <asm/mach-db1x00/bcsr.h>
31#include <asm/mach-pb1x00/pb1200.h>
30 32
31#include "../platform.h" 33#include "../platform.h"
32 34
@@ -88,7 +90,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
88 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 90 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
89} 91}
90 92
91const struct au1xmmc_platform_data au1xmmc_platdata[2] = { 93static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
92 [0] = { 94 [0] = {
93 .set_power = pb1200mmc0_set_power, 95 .set_power = pb1200mmc0_set_power,
94 .card_inserted = pb1200mmc0_card_inserted, 96 .card_inserted = pb1200mmc0_card_inserted,
@@ -105,6 +107,79 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
105 }, 107 },
106}; 108};
107 109
110static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
111
112static struct resource au1200_mmc0_res[] = {
113 [0] = {
114 .start = AU1100_SD0_PHYS_ADDR,
115 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
116 .flags = IORESOURCE_MEM,
117 },
118 [1] = {
119 .start = AU1200_SD_INT,
120 .end = AU1200_SD_INT,
121 .flags = IORESOURCE_IRQ,
122 },
123 [2] = {
124 .start = AU1200_DSCR_CMD0_SDMS_TX0,
125 .end = AU1200_DSCR_CMD0_SDMS_TX0,
126 .flags = IORESOURCE_DMA,
127 },
128 [3] = {
129 .start = AU1200_DSCR_CMD0_SDMS_RX0,
130 .end = AU1200_DSCR_CMD0_SDMS_RX0,
131 .flags = IORESOURCE_DMA,
132 }
133};
134
135static struct platform_device pb1200_mmc0_dev = {
136 .name = "au1xxx-mmc",
137 .id = 0,
138 .dev = {
139 .dma_mask = &au1xxx_mmc_dmamask,
140 .coherent_dma_mask = DMA_BIT_MASK(32),
141 .platform_data = &pb1200mmc_platdata[0],
142 },
143 .num_resources = ARRAY_SIZE(au1200_mmc0_res),
144 .resource = au1200_mmc0_res,
145};
146
147static struct resource au1200_mmc1_res[] = {
148 [0] = {
149 .start = AU1100_SD1_PHYS_ADDR,
150 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = {
154 .start = AU1200_SD_INT,
155 .end = AU1200_SD_INT,
156 .flags = IORESOURCE_IRQ,
157 },
158 [2] = {
159 .start = AU1200_DSCR_CMD0_SDMS_TX1,
160 .end = AU1200_DSCR_CMD0_SDMS_TX1,
161 .flags = IORESOURCE_DMA,
162 },
163 [3] = {
164 .start = AU1200_DSCR_CMD0_SDMS_RX1,
165 .end = AU1200_DSCR_CMD0_SDMS_RX1,
166 .flags = IORESOURCE_DMA,
167 }
168};
169
170static struct platform_device pb1200_mmc1_dev = {
171 .name = "au1xxx-mmc",
172 .id = 1,
173 .dev = {
174 .dma_mask = &au1xxx_mmc_dmamask,
175 .coherent_dma_mask = DMA_BIT_MASK(32),
176 .platform_data = &pb1200mmc_platdata[1],
177 },
178 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
179 .resource = au1200_mmc1_res,
180};
181
182
108static struct resource ide_resources[] = { 183static struct resource ide_resources[] = {
109 [0] = { 184 [0] = {
110 .start = IDE_PHYS_ADDR, 185 .start = IDE_PHYS_ADDR,
@@ -115,7 +190,12 @@ static struct resource ide_resources[] = {
115 .start = IDE_INT, 190 .start = IDE_INT,
116 .end = IDE_INT, 191 .end = IDE_INT,
117 .flags = IORESOURCE_IRQ 192 .flags = IORESOURCE_IRQ
118 } 193 },
194 [2] = {
195 .start = AU1200_DSCR_CMD0_DMA_REQ1,
196 .end = AU1200_DSCR_CMD0_DMA_REQ1,
197 .flags = IORESOURCE_DMA,
198 },
119}; 199};
120 200
121static u64 ide_dmamask = DMA_BIT_MASK(32); 201static u64 ide_dmamask = DMA_BIT_MASK(32);
@@ -161,38 +241,94 @@ static struct platform_device smc91c111_device = {
161 .resource = smc91c111_resources 241 .resource = smc91c111_resources
162}; 242};
163 243
244static struct resource au1200_psc0_res[] = {
245 [0] = {
246 .start = AU1550_PSC0_PHYS_ADDR,
247 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
248 .flags = IORESOURCE_MEM,
249 },
250 [1] = {
251 .start = AU1200_PSC0_INT,
252 .end = AU1200_PSC0_INT,
253 .flags = IORESOURCE_IRQ,
254 },
255 [2] = {
256 .start = AU1200_DSCR_CMD0_PSC0_TX,
257 .end = AU1200_DSCR_CMD0_PSC0_TX,
258 .flags = IORESOURCE_DMA,
259 },
260 [3] = {
261 .start = AU1200_DSCR_CMD0_PSC0_RX,
262 .end = AU1200_DSCR_CMD0_PSC0_RX,
263 .flags = IORESOURCE_DMA,
264 },
265};
266
267static struct platform_device pb1200_i2c_dev = {
268 .name = "au1xpsc_smbus",
269 .id = 0, /* bus number */
270 .num_resources = ARRAY_SIZE(au1200_psc0_res),
271 .resource = au1200_psc0_res,
272};
273
274static struct resource au1200_lcd_res[] = {
275 [0] = {
276 .start = AU1200_LCD_PHYS_ADDR,
277 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = AU1200_LCD_INT,
282 .end = AU1200_LCD_INT,
283 .flags = IORESOURCE_IRQ,
284 }
285};
286
287static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
288
289static struct platform_device au1200_lcd_dev = {
290 .name = "au1200-lcd",
291 .id = 0,
292 .dev = {
293 .dma_mask = &au1200_lcd_dmamask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
295 },
296 .num_resources = ARRAY_SIZE(au1200_lcd_res),
297 .resource = au1200_lcd_res,
298};
299
164static struct platform_device *board_platform_devices[] __initdata = { 300static struct platform_device *board_platform_devices[] __initdata = {
165 &ide_device, 301 &ide_device,
166 &smc91c111_device 302 &smc91c111_device,
303 &pb1200_i2c_dev,
304 &pb1200_mmc0_dev,
305 &pb1200_mmc1_dev,
306 &au1200_lcd_dev,
167}; 307};
168 308
169static int __init board_register_devices(void) 309static int __init board_register_devices(void)
170{ 310{
171 int swapped; 311 int swapped;
172 312
173 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 313 db1x_register_pcmcia_socket(
174 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 314 AU1000_PCMCIA_ATTR_PHYS_ADDR,
175 PCMCIA_MEM_PHYS_ADDR, 315 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
176 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 316 AU1000_PCMCIA_MEM_PHYS_ADDR,
177 PCMCIA_IO_PHYS_ADDR, 317 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
178 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 318 AU1000_PCMCIA_IO_PHYS_ADDR,
179 PB1200_PC0_INT, 319 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
180 PB1200_PC0_INSERT_INT, 320 PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
181 /*PB1200_PC0_STSCHG_INT*/0, 321 /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
182 PB1200_PC0_EJECT_INT, 322
183 0); 323 db1x_register_pcmcia_socket(
184 324 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
185 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, 325 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
186 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, 326 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
187 PCMCIA_MEM_PHYS_ADDR + 0x008000000, 327 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
188 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, 328 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
189 PCMCIA_IO_PHYS_ADDR + 0x008000000, 329 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
190 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, 330 PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
191 PB1200_PC1_INT, 331 /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
192 PB1200_PC1_INSERT_INT,
193 /*PB1200_PC1_STSCHG_INT*/0,
194 PB1200_PC1_EJECT_INT,
195 1);
196 332
197 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 333 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
198 db1x_register_norflash(128 * 1024 * 1024, 2, swapped); 334 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 3b4fa3206969..37c1883b5ea9 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -33,13 +33,6 @@
33 33
34#include <prom.h> 34#include <prom.h>
35 35
36
37char irq_tab_alchemy[][5] __initdata = {
38 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
39 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
40};
41
42
43const char *get_system_type(void) 36const char *get_system_type(void)
44{ 37{
45 return "Alchemy Pb1500"; 38 return "Alchemy Pb1500";
@@ -101,20 +94,18 @@ void __init board_setup(void)
101#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 94#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
102 95
103#ifdef CONFIG_PCI 96#ifdef CONFIG_PCI
104 /* Setup PCI bus controller */ 97 {
105 au_writel(0, Au1500_PCI_CMEM); 98 void __iomem *base =
106 au_writel(0x00003fff, Au1500_CFG_BASE); 99 (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
107#if defined(__MIPSEB__) 100 /* Setup PCI bus controller */
108 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); 101 __raw_writel(0x00003fff, base + PCI_REG_CMEM);
109#else 102 __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
110 au_writel(0xf, Au1500_PCI_CFG); 103 __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
111#endif 104 __raw_writel(0x02a00356, base + PCI_REG_STATCMD);
112 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); 105 __raw_writel(0x00003c04, base + PCI_REG_PARAM);
113 au_writel(0, Au1500_PCI_MWBASE_REV_CCL); 106 __raw_writel(0x00000008, base + PCI_REG_MBAR);
114 au_writel(0x02a00356, Au1500_PCI_STATCMD); 107 wmb();
115 au_writel(0x00003c04, Au1500_PCI_HDRTYPE); 108 }
116 au_writel(0x00000008, Au1500_PCI_MBAR);
117 au_sync();
118#endif 109#endif
119 110
120 /* Enable sys bus clock divider when IDLE state or no bus activity. */ 111 /* Enable sys bus clock divider when IDLE state or no bus activity. */
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index d443bc7aa76e..1e52a01bac00 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -18,32 +18,77 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/dma-mapping.h>
21#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/platform_device.h>
22#include <asm/mach-au1x00/au1000.h> 24#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-db1x00/bcsr.h> 25#include <asm/mach-db1x00/bcsr.h>
24 26
25#include "../platform.h" 27#include "../platform.h"
26 28
29static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
30{
31 if ((slot < 12) || (slot > 13) || pin == 0)
32 return -1;
33 if (slot == 12)
34 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
35 if (slot == 13) {
36 switch (pin) {
37 case 1: return AU1500_PCI_INTA;
38 case 2: return AU1500_PCI_INTB;
39 case 3: return AU1500_PCI_INTC;
40 case 4: return AU1500_PCI_INTD;
41 }
42 }
43 return -1;
44}
45
46static struct resource alchemy_pci_host_res[] = {
47 [0] = {
48 .start = AU1500_PCI_PHYS_ADDR,
49 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
50 .flags = IORESOURCE_MEM,
51 },
52};
53
54static struct alchemy_pci_platdata pb1500_pci_pd = {
55 .board_map_irq = pb1500_map_pci_irq,
56 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
57 PCI_CONFIG_CH |
58#if defined(__MIPSEB__)
59 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
60#else
61 0,
62#endif
63};
64
65static struct platform_device pb1500_pci_host = {
66 .dev.platform_data = &pb1500_pci_pd,
67 .name = "alchemy-pci",
68 .id = 0,
69 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
70 .resource = alchemy_pci_host_res,
71};
72
27static int __init pb1500_dev_init(void) 73static int __init pb1500_dev_init(void)
28{ 74{
29 int swapped; 75 int swapped;
30 76
31 /* PCMCIA. single socket, identical to Pb1500 */ 77 /* PCMCIA. single socket, identical to Pb1100 */
32 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 78 db1x_register_pcmcia_socket(
33 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 79 AU1000_PCMCIA_ATTR_PHYS_ADDR,
34 PCMCIA_MEM_PHYS_ADDR, 80 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
35 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 81 AU1000_PCMCIA_MEM_PHYS_ADDR,
36 PCMCIA_IO_PHYS_ADDR, 82 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
37 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 83 AU1000_PCMCIA_IO_PHYS_ADDR,
38 AU1500_GPIO11_INT, /* card */ 84 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
39 AU1500_GPIO9_INT, /* insert */ 85 AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
40 /*AU1500_GPIO10_INT*/0, /* stschg */ 86 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
41 0, /* eject */
42 0); /* id */
43 87
44 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 88 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
45 db1x_register_norflash(64 * 1024 * 1024, 4, swapped); 89 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
90 platform_device_register(&pb1500_pci_host);
46 91
47 return 0; 92 return 0;
48} 93}
49device_initcall(pb1500_dev_init); 94arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index b790213848bd..0f62d1e3df24 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -37,12 +37,6 @@
37 37
38#include <prom.h> 38#include <prom.h>
39 39
40
41char irq_tab_alchemy[][5] __initdata = {
42 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
43 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
44};
45
46const char *get_system_type(void) 40const char *get_system_type(void)
47{ 41{
48 return "Alchemy Pb1550"; 42 return "Alchemy Pb1550";
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index d7150d0f49c0..a4604b8a349e 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -18,14 +18,89 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/dma-mapping.h>
21#include <linux/init.h> 22#include <linux/init.h>
22 23#include <linux/platform_device.h>
23#include <asm/mach-au1x00/au1000.h> 24#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-au1x00/au1xxx_dbdma.h>
24#include <asm/mach-pb1x00/pb1550.h> 26#include <asm/mach-pb1x00/pb1550.h>
25#include <asm/mach-db1x00/bcsr.h> 27#include <asm/mach-db1x00/bcsr.h>
26 28
27#include "../platform.h" 29#include "../platform.h"
28 30
31static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
32{
33 if ((slot < 12) || (slot > 13) || pin == 0)
34 return -1;
35 if (slot == 12) {
36 switch (pin) {
37 case 1: return AU1500_PCI_INTB;
38 case 2: return AU1500_PCI_INTC;
39 case 3: return AU1500_PCI_INTD;
40 case 4: return AU1500_PCI_INTA;
41 }
42 }
43 if (slot == 13) {
44 switch (pin) {
45 case 1: return AU1500_PCI_INTA;
46 case 2: return AU1500_PCI_INTB;
47 case 3: return AU1500_PCI_INTC;
48 case 4: return AU1500_PCI_INTD;
49 }
50 }
51 return -1;
52}
53
54static struct resource alchemy_pci_host_res[] = {
55 [0] = {
56 .start = AU1500_PCI_PHYS_ADDR,
57 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
58 .flags = IORESOURCE_MEM,
59 },
60};
61
62static struct alchemy_pci_platdata pb1550_pci_pd = {
63 .board_map_irq = pb1550_map_pci_irq,
64};
65
66static struct platform_device pb1550_pci_host = {
67 .dev.platform_data = &pb1550_pci_pd,
68 .name = "alchemy-pci",
69 .id = 0,
70 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
71 .resource = alchemy_pci_host_res,
72};
73
74static struct resource au1550_psc2_res[] = {
75 [0] = {
76 .start = AU1550_PSC2_PHYS_ADDR,
77 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
78 .flags = IORESOURCE_MEM,
79 },
80 [1] = {
81 .start = AU1550_PSC2_INT,
82 .end = AU1550_PSC2_INT,
83 .flags = IORESOURCE_IRQ,
84 },
85 [2] = {
86 .start = AU1550_DSCR_CMD0_PSC2_TX,
87 .end = AU1550_DSCR_CMD0_PSC2_TX,
88 .flags = IORESOURCE_DMA,
89 },
90 [3] = {
91 .start = AU1550_DSCR_CMD0_PSC2_RX,
92 .end = AU1550_DSCR_CMD0_PSC2_RX,
93 .flags = IORESOURCE_DMA,
94 },
95};
96
97static struct platform_device pb1550_i2c_dev = {
98 .name = "au1xpsc_smbus",
99 .id = 0, /* bus number */
100 .num_resources = ARRAY_SIZE(au1550_psc2_res),
101 .resource = au1550_psc2_res,
102};
103
29static int __init pb1550_dev_init(void) 104static int __init pb1550_dev_init(void)
30{ 105{
31 int swapped; 106 int swapped;
@@ -37,33 +112,29 @@ static int __init pb1550_dev_init(void)
37 * drivers are used to shared irqs and b) statuschange isn't really use- 112 * drivers are used to shared irqs and b) statuschange isn't really use-
38 * ful anyway. 113 * ful anyway.
39 */ 114 */
40 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 115 db1x_register_pcmcia_socket(
41 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 116 AU1000_PCMCIA_ATTR_PHYS_ADDR,
42 PCMCIA_MEM_PHYS_ADDR, 117 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
43 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 118 AU1000_PCMCIA_MEM_PHYS_ADDR,
44 PCMCIA_IO_PHYS_ADDR, 119 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
45 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 120 AU1000_PCMCIA_IO_PHYS_ADDR,
46 AU1550_GPIO201_205_INT, 121 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
47 AU1550_GPIO0_INT, 122 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
48 0,
49 0,
50 0);
51 123
52 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, 124 db1x_register_pcmcia_socket(
53 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, 125 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
54 PCMCIA_MEM_PHYS_ADDR + 0x008000000, 126 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
55 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, 127 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
56 PCMCIA_IO_PHYS_ADDR + 0x008000000, 128 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
57 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, 129 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
58 AU1550_GPIO201_205_INT, 130 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
59 AU1550_GPIO1_INT, 131 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
60 0,
61 0,
62 1);
63 132
64 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; 133 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
65 db1x_register_norflash(128 * 1024 * 1024, 4, swapped); 134 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
135 platform_device_register(&pb1550_pci_host);
136 platform_device_register(&pb1550_i2c_dev);
66 137
67 return 0; 138 return 0;
68} 139}
69device_initcall(pb1550_dev_init); 140arch_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
index 5f8f0691ed2d..dea45c78fdcd 100644
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -36,10 +36,6 @@
36 36
37#include <prom.h> 37#include <prom.h>
38 38
39char irq_tab_alchemy[][5] __initdata = {
40 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
41};
42
43static void gpr_reset(char *c) 39static void gpr_reset(char *c)
44{ 40{
45 /* switch System-LED to orange (red# and green# on) */ 41 /* switch System-LED to orange (red# and green# on) */
@@ -76,12 +72,4 @@ void __init board_setup(void)
76 72
77 /* Take away Reset of UMTS-card */ 73 /* Take away Reset of UMTS-card */
78 alchemy_gpio_direction_output(215, 1); 74 alchemy_gpio_direction_output(215, 1);
79
80#ifdef CONFIG_PCI
81#if defined(__MIPSEB__)
82 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
83#else
84 au_writel(0xf, Au1500_PCI_CFG);
85#endif
86#endif
87} 75}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
index 14b46629cfc8..982ce85db60d 100644
--- a/arch/mips/alchemy/gpr/platform.c
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = {
167 } 167 }
168}; 168};
169 169
170
171
172static struct resource alchemy_pci_host_res[] = {
173 [0] = {
174 .start = AU1500_PCI_PHYS_ADDR,
175 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
176 .flags = IORESOURCE_MEM,
177 },
178};
179
180static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
181{
182 if ((slot == 0) && (pin == 1))
183 return AU1550_PCI_INTA;
184 else if ((slot == 0) && (pin == 2))
185 return AU1550_PCI_INTB;
186
187 return -1;
188}
189
190static struct alchemy_pci_platdata gpr_pci_pd = {
191 .board_map_irq = gpr_map_pci_irq,
192 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
193 PCI_CONFIG_CH |
194#if defined(__MIPSEB__)
195 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
196#else
197 0,
198#endif
199};
200
201static struct platform_device gpr_pci_host_dev = {
202 .dev.platform_data = &gpr_pci_pd,
203 .name = "alchemy-pci",
204 .id = 0,
205 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
206 .resource = alchemy_pci_host_res,
207};
208
170static struct platform_device *gpr_devices[] __initdata = { 209static struct platform_device *gpr_devices[] __initdata = {
171 &gpr_wdt_device, 210 &gpr_wdt_device,
172 &gpr_mtd_device, 211 &gpr_mtd_device,
@@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = {
174 &gpr_led_devices, 213 &gpr_led_devices,
175}; 214};
176 215
216static int __init gpr_pci_init(void)
217{
218 return platform_device_register(&gpr_pci_host_dev);
219}
220/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
221arch_initcall(gpr_pci_init);
222
223
177static int __init gpr_dev_init(void) 224static int __init gpr_dev_init(void)
178{ 225{
179 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); 226 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3ae984cf98cf..851a5ab4c8f2 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -38,20 +38,6 @@
38 38
39#include <prom.h> 39#include <prom.h>
40 40
41char irq_tab_alchemy[][5] __initdata = {
42 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
43 [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
44 [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
45 [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
46 [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
47 [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
48 [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
49 [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
50};
51
52extern int (*board_pci_idsel)(unsigned int devsel, int assert);
53int mtx1_pci_idsel(unsigned int devsel, int assert);
54
55static void mtx1_reset(char *c) 41static void mtx1_reset(char *c)
56{ 42{
57 /* Jump to the reset vector */ 43 /* Jump to the reset vector */
@@ -74,15 +60,6 @@ void __init board_setup(void)
74 alchemy_gpio_direction_output(204, 0); 60 alchemy_gpio_direction_output(204, 0);
75#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 61#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
76 62
77#ifdef CONFIG_PCI
78#if defined(__MIPSEB__)
79 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
80#else
81 au_writel(0xf, Au1500_PCI_CFG);
82#endif
83 board_pci_idsel = mtx1_pci_idsel;
84#endif
85
86 /* Initialize sys_pinfunc */ 63 /* Initialize sys_pinfunc */
87 au_writel(SYS_PF_NI2, SYS_PINFUNC); 64 au_writel(SYS_PF_NI2, SYS_PINFUNC);
88 65
@@ -104,23 +81,6 @@ void __init board_setup(void)
104 printk(KERN_INFO "4G Systems MTX-1 Board\n"); 81 printk(KERN_INFO "4G Systems MTX-1 Board\n");
105} 82}
106 83
107int
108mtx1_pci_idsel(unsigned int devsel, int assert)
109{
110 /* This function is only necessary to support a proprietary Cardbus
111 * adapter on the mtx-1 "singleboard" variant. It triggers a custom
112 * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
113 */
114 if (assert && devsel != 0)
115 /* Suppress signal to Cardbus */
116 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
117 else
118 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
119
120 udelay(1);
121 return 1;
122}
123
124static int __init mtx1_init_irq(void) 84static int __init mtx1_init_irq(void)
125{ 85{
126 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 86 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
index 55628e390fd7..cc47b6868ca3 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/mtx-1/platform.c
@@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = {
135 .resource = &mtx1_mtd_resource, 135 .resource = &mtx1_mtd_resource,
136}; 136};
137 137
138static struct resource alchemy_pci_host_res[] = {
139 [0] = {
140 .start = AU1500_PCI_PHYS_ADDR,
141 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
142 .flags = IORESOURCE_MEM,
143 },
144};
145
146static int mtx1_pci_idsel(unsigned int devsel, int assert)
147{
148 /* This function is only necessary to support a proprietary Cardbus
149 * adapter on the mtx-1 "singleboard" variant. It triggers a custom
150 * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
151 */
152 if (assert && devsel != 0)
153 /* Suppress signal to Cardbus */
154 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
155 else
156 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
157
158 udelay(1);
159 return 1;
160}
161
162static const char mtx1_irqtab[][5] = {
163 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
164 [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
165 [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
166 [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
167 [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
168 [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
169 [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
170 [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
171};
172
173static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
174{
175 return mtx1_irqtab[slot][pin];
176}
177
178static struct alchemy_pci_platdata mtx1_pci_pd = {
179 .board_map_irq = mtx1_map_pci_irq,
180 .board_pci_idsel = mtx1_pci_idsel,
181 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
182 PCI_CONFIG_CH |
183#if defined(__MIPSEB__)
184 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
185#else
186 0,
187#endif
188};
189
190static struct platform_device mtx1_pci_host = {
191 .dev.platform_data = &mtx1_pci_pd,
192 .name = "alchemy-pci",
193 .id = 0,
194 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
195 .resource = alchemy_pci_host_res,
196};
197
198
138static struct __initdata platform_device * mtx1_devs[] = { 199static struct __initdata platform_device * mtx1_devs[] = {
200 &mtx1_pci_host,
139 &mtx1_gpio_leds, 201 &mtx1_gpio_leds,
140 &mtx1_wdt, 202 &mtx1_wdt,
141 &mtx1_button, 203 &mtx1_button,
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 81e57fad07ab..3fa83f72e014 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -70,14 +70,6 @@ void __init board_setup(void)
70 /* Enable DTR (MCR bit 0) = USB power up */ 70 /* Enable DTR (MCR bit 0) = USB power up */
71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); 71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
72 wmb(); 72 wmb();
73
74#ifdef CONFIG_PCI
75#if defined(__MIPSEB__)
76 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
77#else
78 au_writel(0xf, Au1500_PCI_CFG);
79#endif
80#endif
81} 73}
82 74
83static int __init xxs1500_init_irq(void) 75static int __init xxs1500_init_irq(void)
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
index e87c45cde61b..06a3a459b8aa 100644
--- a/arch/mips/alchemy/xxs1500/platform.c
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -27,20 +27,20 @@ static struct resource xxs1500_pcmcia_res[] = {
27 { 27 {
28 .name = "pcmcia-io", 28 .name = "pcmcia-io",
29 .flags = IORESOURCE_MEM, 29 .flags = IORESOURCE_MEM,
30 .start = PCMCIA_IO_PHYS_ADDR, 30 .start = AU1000_PCMCIA_IO_PHYS_ADDR,
31 .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, 31 .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
32 }, 32 },
33 { 33 {
34 .name = "pcmcia-attr", 34 .name = "pcmcia-attr",
35 .flags = IORESOURCE_MEM, 35 .flags = IORESOURCE_MEM,
36 .start = PCMCIA_ATTR_PHYS_ADDR, 36 .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
37 .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 37 .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
38 }, 38 },
39 { 39 {
40 .name = "pcmcia-mem", 40 .name = "pcmcia-mem",
41 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
42 .start = PCMCIA_MEM_PHYS_ADDR, 42 .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
43 .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 43 .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 }, 44 },
45}; 45};
46 46
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 21:44:54 -0500