MIPS: Alchemy: abstract USB block control register access

Alchemy chips have one or more registers which control access
to the usb blocks as well as PHY configuration.  I don't want
the OHCI/EHCI glues to know about the different registers and bits;
new code hides the gory details of USB configuration from them.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: linux-usb@vger.kernel.org
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Patchwork: https://patchwork.linux-mips.org/patch/2709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 create mode 100644 drivers/usb/host/alchemy-common.c

2 files changed, 6 insertions, 48 deletions

diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 347980e79a89..6652a237b920 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -88,12 +88,12 @@ static const struct dma_dev {
         { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR },    /* AC97 RX c */
         { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC },    /* UART3_TX */
         { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
-        { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
-        { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
-        { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
-        { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
-        { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
-        { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
+        { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
+        { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
+        { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
+        { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
+        { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
+        { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
         /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
         { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC},      /* I2S TX */
         { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 9ec85597bbf3..bdd6651e9a4f 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -47,7 +47,6 @@
  * We only have to save/restore registers that aren't otherwise
  * done as part of a driver pm_* function.
  */
-static unsigned int sleep_usb[2];
 static unsigned int sleep_sys_clocks[5];
 static unsigned int sleep_sys_pinfunc;
 static unsigned int sleep_static_memctlr[4][3];
@@ -55,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3];
 
 static void save_core_regs(void)
 {
-#ifndef CONFIG_SOC_AU1200
-        /* Shutdown USB host/device. */
-        sleep_usb[0] = au_readl(USB_HOST_CONFIG);
-
-        /* There appears to be some undocumented reset register.... */
-        au_writel(0, 0xb0100004);
-        au_sync();
-        au_writel(0, USB_HOST_CONFIG);
-        au_sync();
-
-        sleep_usb[1] = au_readl(USBD_ENABLE);
-        au_writel(0, USBD_ENABLE);
-        au_sync();
-
-#else   /* AU1200 */
-
-        /* enable access to OTG mmio so we can save OTG CAP/MUX.
-         * FIXME: write an OTG driver and move this stuff there!
-         */
-        au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
-        au_sync();
-        sleep_usb[0] = au_readl(0xb4020020);    /* OTG_CAP */
-        sleep_usb[1] = au_readl(0xb4020024);    /* OTG_MUX */
-#endif
-
         /* Clocks and PLLs. */
         sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
         sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
@@ -123,22 +97,6 @@ static void restore_core_regs(void)
         au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
         au_sync();
 
-#ifndef CONFIG_SOC_AU1200
-        au_writel(sleep_usb[0], USB_HOST_CONFIG);
-        au_writel(sleep_usb[1], USBD_ENABLE);
-        au_sync();
-#else
-        /* enable access to OTG memory */
-        au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
-        au_sync();
-
-        /* restore OTG caps and port mux. */
-        au_writel(sleep_usb[0], 0xb4020020 + 0);        /* OTG_CAP */
-        au_sync();
-        au_writel(sleep_usb[1], 0xb4020020 + 4);        /* OTG_MUX */
-        au_sync();
-#endif
-
         /* Restore the static memory controller configuration. */
         au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
         au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);