MIPS: Alchemy: Rewrite UART setup and constants.

Detect CPU type at runtime and setup uarts accordingly; also clean up the
uart base address mess in the process as far as possible.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Patchwork: https://patchwork.linux-mips.org/patch/2352/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org

2 files changed, 5 insertions, 8 deletions

diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index febfb0fb0896..81e57fad07ab 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -66,13 +66,10 @@ void __init board_setup(void)
         au_writel(pin_func, SYS_PINFUNC);
 
         /* Enable UART */
-        au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
-        mdelay(10);
-        au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
-        mdelay(10);
-
-        /* Enable DTR = USB power up */
-        au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
+        alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
+        /* Enable DTR (MCR bit 0) = USB power up */
+        __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
+        wmb();
 
 #ifdef CONFIG_PCI
 #if defined(__MIPSEB__)
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 34a90a4bb6f4..0ee02cfa989d 100644
--- a/arch/mips/alchemy/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -59,5 +59,5 @@ void __init prom_init(void)
 
 void prom_putchar(unsigned char c)
 {
-        alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
 }