aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/alchemy/common
diff options
context:
space:
mode:
authorManuel Lauss <manuel.lauss@googlemail.com>2009-10-07 14:15:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 06:52:53 -0500
commit788144656b8a862e724a1296e64ab6375eb541ed (patch)
tree96208eed56da25acdf9d923b9d9986e82dcd8944 /arch/mips/alchemy/common
parent93e9cd8485b31e5a33f1040bff4d15e65c0b2d19 (diff)
MIPS: Alchemy: Stop IRQ name sharing
Eliminate the sharing of IRQ names among the differenct Alchemy variants. IRQ numbers need no longer be hidden behind a CONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy code less reliant on a hardcoded subtype. This patch also renames the GPIO irq number constants. It's really an interrupt line, NOT a GPIO number! Code which relied on certain irq numbers to have the same name across all supported cpu subtypes is changed to determine current cpu subtype at runtime; in some places this isn't possible so a "compat" symbol is used. Run-tested on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/common')
-rw-r--r--arch/mips/alchemy/common/dbdma.c61
-rw-r--r--arch/mips/alchemy/common/dma.c36
-rw-r--r--arch/mips/alchemy/common/irq.c290
-rw-r--r--arch/mips/alchemy/common/platform.c8
-rw-r--r--arch/mips/alchemy/common/time.c35
5 files changed, 247 insertions, 183 deletions
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index f9201ca2295b..549b18f3c18b 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -30,6 +30,7 @@
30 * 30 *
31 */ 31 */
32 32
33#include <linux/init.h>
33#include <linux/kernel.h> 34#include <linux/kernel.h>
34#include <linux/slab.h> 35#include <linux/slab.h>
35#include <linux/spinlock.h> 36#include <linux/spinlock.h>
@@ -58,7 +59,6 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
58 59
59static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; 60static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
60static int dbdma_initialized; 61static int dbdma_initialized;
61static void au1xxx_dbdma_init(void);
62 62
63static dbdev_tab_t dbdev_tab[] = { 63static dbdev_tab_t dbdev_tab[] = {
64#ifdef CONFIG_SOC_AU1550 64#ifdef CONFIG_SOC_AU1550
@@ -250,8 +250,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
250 * which can't be done successfully during board set up. 250 * which can't be done successfully during board set up.
251 */ 251 */
252 if (!dbdma_initialized) 252 if (!dbdma_initialized)
253 au1xxx_dbdma_init(); 253 return 0;
254 dbdma_initialized = 1;
255 254
256 stp = find_dbdev_id(srcid); 255 stp = find_dbdev_id(srcid);
257 if (stp == NULL) 256 if (stp == NULL)
@@ -871,28 +870,6 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
871 return IRQ_RETVAL(1); 870 return IRQ_RETVAL(1);
872} 871}
873 872
874static void au1xxx_dbdma_init(void)
875{
876 int irq_nr;
877
878 dbdma_gptr->ddma_config = 0;
879 dbdma_gptr->ddma_throttle = 0;
880 dbdma_gptr->ddma_inten = 0xffff;
881 au_sync();
882
883#if defined(CONFIG_SOC_AU1550)
884 irq_nr = AU1550_DDMA_INT;
885#elif defined(CONFIG_SOC_AU1200)
886 irq_nr = AU1200_DDMA_INT;
887#else
888 #error Unknown Au1x00 SOC
889#endif
890
891 if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
892 "Au1xxx dbdma", (void *)dbdma_gptr))
893 printk(KERN_ERR "Can't get 1550 dbdma irq");
894}
895
896void au1xxx_dbdma_dump(u32 chanid) 873void au1xxx_dbdma_dump(u32 chanid)
897{ 874{
898 chan_tab_t *ctp; 875 chan_tab_t *ctp;
@@ -1041,4 +1018,38 @@ void au1xxx_dbdma_resume(void)
1041 } 1018 }
1042} 1019}
1043#endif /* CONFIG_PM */ 1020#endif /* CONFIG_PM */
1021
1022static int __init au1xxx_dbdma_init(void)
1023{
1024 int irq_nr, ret;
1025
1026 dbdma_gptr->ddma_config = 0;
1027 dbdma_gptr->ddma_throttle = 0;
1028 dbdma_gptr->ddma_inten = 0xffff;
1029 au_sync();
1030
1031 switch (alchemy_get_cputype()) {
1032 case ALCHEMY_CPU_AU1550:
1033 irq_nr = AU1550_DDMA_INT;
1034 break;
1035 case ALCHEMY_CPU_AU1200:
1036 irq_nr = AU1200_DDMA_INT;
1037 break;
1038 default:
1039 return -ENODEV;
1040 }
1041
1042 ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
1043 "Au1xxx dbdma", (void *)dbdma_gptr);
1044 if (ret)
1045 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1046 else {
1047 dbdma_initialized = 1;
1048 printk(KERN_INFO "Alchemy DBDMA initialized\n");
1049 }
1050
1051 return ret;
1052}
1053subsys_initcall(au1xxx_dbdma_init);
1054
1044#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 1055#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index d6fbda232e6a..d5278877891d 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -29,6 +29,8 @@
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 * 30 *
31 */ 31 */
32
33#include <linux/init.h>
32#include <linux/module.h> 34#include <linux/module.h>
33#include <linux/kernel.h> 35#include <linux/kernel.h>
34#include <linux/errno.h> 36#include <linux/errno.h>
@@ -188,17 +190,14 @@ int request_au1000_dma(int dev_id, const char *dev_str,
188 dev = &dma_dev_table[dev_id]; 190 dev = &dma_dev_table[dev_id];
189 191
190 if (irqhandler) { 192 if (irqhandler) {
191 chan->irq = AU1000_DMA_INT_BASE + i;
192 chan->irq_dev = irq_dev_id; 193 chan->irq_dev = irq_dev_id;
193 ret = request_irq(chan->irq, irqhandler, irqflags, dev_str, 194 ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
194 chan->irq_dev); 195 chan->irq_dev);
195 if (ret) { 196 if (ret) {
196 chan->irq = 0;
197 chan->irq_dev = NULL; 197 chan->irq_dev = NULL;
198 return ret; 198 return ret;
199 } 199 }
200 } else { 200 } else {
201 chan->irq = 0;
202 chan->irq_dev = NULL; 201 chan->irq_dev = NULL;
203 } 202 }
204 203
@@ -226,13 +225,40 @@ void free_au1000_dma(unsigned int dmanr)
226 } 225 }
227 226
228 disable_dma(dmanr); 227 disable_dma(dmanr);
229 if (chan->irq) 228 if (chan->irq_dev)
230 free_irq(chan->irq, chan->irq_dev); 229 free_irq(chan->irq, chan->irq_dev);
231 230
232 chan->irq = 0;
233 chan->irq_dev = NULL; 231 chan->irq_dev = NULL;
234 chan->dev_id = -1; 232 chan->dev_id = -1;
235} 233}
236EXPORT_SYMBOL(free_au1000_dma); 234EXPORT_SYMBOL(free_au1000_dma);
237 235
236static int __init au1000_dma_init(void)
237{
238 int base, i;
239
240 switch (alchemy_get_cputype()) {
241 case ALCHEMY_CPU_AU1000:
242 base = AU1000_DMA_INT_BASE;
243 break;
244 case ALCHEMY_CPU_AU1500:
245 base = AU1500_DMA_INT_BASE;
246 break;
247 case ALCHEMY_CPU_AU1100:
248 base = AU1100_DMA_INT_BASE;
249 break;
250 default:
251 goto out;
252 }
253
254 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
255 au1000_dma_table[i].irq = base + i;
256
257 printk(KERN_INFO "Alchemy DMA initialized\n");
258
259out:
260 return 0;
261}
262arch_initcall(au1000_dma_init);
263
238#endif /* AU1000 AU1500 AU1100 */ 264#endif /* AU1000 AU1500 AU1100 */
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b5f00b3ad4e..f5b148af8b8c 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -53,160 +53,160 @@ struct au1xxx_irqmap {
53 int im_request; /* set 1 to get higher priority */ 53 int im_request; /* set 1 to get higher priority */
54} au1xxx_ic0_map[] __initdata = { 54} au1xxx_ic0_map[] __initdata = {
55#if defined(CONFIG_SOC_AU1000) 55#if defined(CONFIG_SOC_AU1000)
56 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 56 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
57 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 57 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
58 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 58 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
59 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 59 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
60 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 60 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
61 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 61 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
62 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 62 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
63 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 63 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
64 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 64 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
65 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 65 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
66 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 66 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
67 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 67 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
68 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 68 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
69 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 69 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
70 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 70 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
71 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 71 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
72 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 72 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
73 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 73 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
74 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 74 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
75 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 75 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
76 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 76 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
77 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 77 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
78 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 78 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
79 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 79 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
80 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 80 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
81 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 81 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
82 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 82 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
83 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 83 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
84 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 84 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
85 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 85 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
86 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 86 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
87 87
88#elif defined(CONFIG_SOC_AU1500) 88#elif defined(CONFIG_SOC_AU1500)
89 89
90 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 90 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
91 { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 91 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
92 { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 92 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
93 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 93 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
94 { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 94 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
95 { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 95 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
96 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 96 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
97 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 97 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
98 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 98 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
99 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 99 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
100 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 100 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
101 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 101 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
102 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 102 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
103 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 103 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
104 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 104 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
105 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 105 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
106 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 106 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
107 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 107 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
108 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 108 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
109 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 109 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
110 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 110 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
111 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 111 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
112 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 112 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
113 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 113 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
114 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 114 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
115 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 115 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
116 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 116 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 117 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 118 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
119 119
120#elif defined(CONFIG_SOC_AU1100) 120#elif defined(CONFIG_SOC_AU1100)
121 121
122 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 122 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
123 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 123 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
124 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 124 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
125 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 125 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 126 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
127 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 127 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
128 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 128 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
129 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 129 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
130 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 130 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
131 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 131 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
132 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 132 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
133 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 133 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
134 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 134 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 135 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 136 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
137 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 137 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
138 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 138 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
139 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 139 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 140 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
141 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 141 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
142 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 142 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
143 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 143 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
144 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 144 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
145 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 145 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
146 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 146 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
147 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 147 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
148 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 148 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
149 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 149 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
150 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 150 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 151 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
152 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 152 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
153 153
154#elif defined(CONFIG_SOC_AU1550) 154#elif defined(CONFIG_SOC_AU1550)
155 155
156 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 156 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 157 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
158 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 158 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
159 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 159 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
160 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 160 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
161 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 161 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
162 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 162 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
163 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 163 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
164 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 164 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
165 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 165 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
166 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 166 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
167 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 167 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
168 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 168 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
169 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 169 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 170 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
171 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 171 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
172 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 172 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
173 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 173 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
174 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 174 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
175 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 175 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
176 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 176 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
177 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 177 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
178 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 178 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
179 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 179 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
180 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 180 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
181 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 181 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
182 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 182 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 183 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 184
185#elif defined(CONFIG_SOC_AU1200) 185#elif defined(CONFIG_SOC_AU1200)
186 186
187 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 187 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, 188 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
189 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 189 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
190 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 190 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
191 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 191 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
192 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 192 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
193 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 193 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
194 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 194 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
195 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 195 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
196 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 196 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
197 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 197 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
198 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 198 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
199 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 199 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
200 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 200 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
201 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 201 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
202 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 202 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
203 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 203 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
204 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 204 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
205 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 205 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
206 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 206 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
207 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 207 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
208 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 208 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
209 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 209 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
210 210
211#else 211#else
212#error "Error: Unknown Alchemy SOC" 212#error "Error: Unknown Alchemy SOC"
@@ -316,7 +316,7 @@ static void au1x_ic1_unmask(unsigned int irq_nr)
316 * nowhere in the current kernel sources is it disabled. --mlau 316 * nowhere in the current kernel sources is it disabled. --mlau
317 */ 317 */
318#if defined(CONFIG_MIPS_PB1000) 318#if defined(CONFIG_MIPS_PB1000)
319 if (irq_nr == AU1000_GPIO_15) 319 if (irq_nr == AU1000_GPIO15_INT)
320 au_writel(0x4000, PB1000_MDR); /* enable int */ 320 au_writel(0x4000, PB1000_MDR); /* enable int */
321#endif 321#endif
322 au_sync(); 322 au_sync();
@@ -388,11 +388,13 @@ static void au1x_ic1_maskack(unsigned int irq_nr)
388 388
389static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 389static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
390{ 390{
391 unsigned int bit = irq - AU1000_INTC1_INT_BASE; 391 int bit = irq - AU1000_INTC1_INT_BASE;
392 unsigned long wakemsk, flags; 392 unsigned long wakemsk, flags;
393 393
394 /* only GPIO 0-7 can act as wakeup source: */ 394 /* only GPIO 0-7 can act as wakeup source. Fortunately these
395 if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7)) 395 * are wired up identically on all supported variants.
396 */
397 if ((bit < 0) || (bit > 7))
396 return -EINVAL; 398 return -EINVAL;
397 399
398 local_irq_save(flags); 400 local_irq_save(flags);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 2b76a57c4947..5a9a4f9eba2e 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -73,8 +73,8 @@ static struct resource au1xxx_usb_ohci_resources[] = {
73 .flags = IORESOURCE_MEM, 73 .flags = IORESOURCE_MEM,
74 }, 74 },
75 [1] = { 75 [1] = {
76 .start = AU1000_USB_HOST_INT, 76 .start = FOR_PLATFORM_C_USB_HOST_INT,
77 .end = AU1000_USB_HOST_INT, 77 .end = FOR_PLATFORM_C_USB_HOST_INT,
78 .flags = IORESOURCE_IRQ, 78 .flags = IORESOURCE_IRQ,
79 }, 79 },
80}; 80};
@@ -132,8 +132,8 @@ static struct resource au1xxx_usb_ehci_resources[] = {
132 .flags = IORESOURCE_MEM, 132 .flags = IORESOURCE_MEM,
133 }, 133 },
134 [1] = { 134 [1] = {
135 .start = AU1000_USB_HOST_INT, 135 .start = AU1200_USB_INT,
136 .end = AU1000_USB_HOST_INT, 136 .end = AU1200_USB_INT,
137 .flags = IORESOURCE_IRQ, 137 .flags = IORESOURCE_IRQ,
138 }, 138 },
139}; 139};
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 379a664809b0..2aecb2fdf982 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net> 2 * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
3 * 3 *
4 * Previous incarnations were: 4 * Previous incarnations were:
5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> 5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
@@ -85,7 +85,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
85 .name = "rtcmatch2", 85 .name = "rtcmatch2",
86 .features = CLOCK_EVT_FEAT_ONESHOT, 86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 .rating = 100, 87 .rating = 100,
88 .irq = AU1000_RTC_MATCH2_INT,
89 .set_next_event = au1x_rtcmatch2_set_next_event, 88 .set_next_event = au1x_rtcmatch2_set_next_event,
90 .set_mode = au1x_rtcmatch2_set_mode, 89 .set_mode = au1x_rtcmatch2_set_mode,
91 .cpumask = cpu_all_mask, 90 .cpumask = cpu_all_mask,
@@ -98,11 +97,13 @@ static struct irqaction au1x_rtcmatch2_irqaction = {
98 .dev_id = &au1x_rtcmatch2_clockdev, 97 .dev_id = &au1x_rtcmatch2_clockdev,
99}; 98};
100 99
101void __init plat_time_init(void) 100static int __init alchemy_time_init(unsigned int m2int)
102{ 101{
103 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; 102 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
104 unsigned long t; 103 unsigned long t;
105 104
105 au1x_rtcmatch2_clockdev.irq = m2int;
106
106 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock 107 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
107 * has been detected. If so install the rtcmatch2 clocksource, 108 * has been detected. If so install the rtcmatch2 clocksource,
108 * otherwise don't bother. Note that both bits being set is by 109 * otherwise don't bother. Note that both bits being set is by
@@ -148,13 +149,18 @@ void __init plat_time_init(void)
148 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); 149 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
149 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ 150 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
150 clockevents_register_device(cd); 151 clockevents_register_device(cd);
151 setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); 152 setup_irq(m2int, &au1x_rtcmatch2_irqaction);
152 153
153 printk(KERN_INFO "Alchemy clocksource installed\n"); 154 printk(KERN_INFO "Alchemy clocksource installed\n");
154 155
155 return; 156 return 0;
156 157
157cntr_err: 158cntr_err:
159 return -1;
160}
161
162static void __init alchemy_setup_c0timer(void)
163{
158 /* 164 /*
159 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this 165 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
160 * function is called. Because the Alchemy counters are unusable 166 * function is called. Because the Alchemy counters are unusable
@@ -166,3 +172,22 @@ cntr_err:
166 r4k_clockevent_init(); 172 r4k_clockevent_init();
167 init_r4k_clocksource(); 173 init_r4k_clocksource();
168} 174}
175
176static int alchemy_m2inttab[] __initdata = {
177 AU1000_RTC_MATCH2_INT,
178 AU1500_RTC_MATCH2_INT,
179 AU1100_RTC_MATCH2_INT,
180 AU1550_RTC_MATCH2_INT,
181 AU1200_RTC_MATCH2_INT,
182};
183
184void __init plat_time_init(void)
185{
186 int t;
187
188 t = alchemy_get_cputype();
189 if (t == ALCHEMY_CPU_UNKNOWN)
190 alchemy_setup_c0timer();
191 else if (alchemy_time_init(alchemy_m2inttab[t]))
192 alchemy_setup_c0timer();
193}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 19:53:08 -0500