Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into mips-for-linux-next

1 files changed, 6 insertions, 5 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9806a5ae50be..b7dc39c6c849 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -106,6 +106,7 @@ config ATH79
 
 config BCM47XX
         bool "Broadcom BCM47XX based boards"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select CEVT_R4K
         select CSRC_R4K
         select DMA_NONCOHERENT
@@ -114,7 +115,6 @@ config BCM47XX
         select IRQ_CPU
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
-        select GENERIC_GPIO
         select SYS_HAS_EARLY_PRINTK
         help
          Support for BCM47XX based boards
@@ -798,7 +798,7 @@ config NLM_XLR_BOARD
         select CSRC_R4K
         select IRQ_CPU
         select ARCH_SUPPORTS_MSI
-        select ZONE_DMA if 64BIT
+        select ZONE_DMA32 if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
         select USB_ARCH_HAS_OHCI if USB_SUPPORT
@@ -826,7 +826,7 @@ config NLM_XLP_BOARD
         select CEVT_R4K
         select CSRC_R4K
         select IRQ_CPU
-        select ZONE_DMA if 64BIT
+        select ZONE_DMA32 if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
         select USE_OF
@@ -1507,6 +1507,7 @@ config CPU_XLP
         select WEAK_ORDERING
         select WEAK_REORDERING_BEYOND_LLSC
         select CPU_HAS_PREFETCH
+        select CPU_MIPSR2
         help
           Netlogic Microsystems XLP processors.
 endchoice
@@ -1718,7 +1719,7 @@ config CPU_SUPPORTS_UNCACHED_ACCELERATED
         bool
 config MIPS_PGD_C0_CONTEXT
         bool
-        default y if 64BIT && CPU_MIPSR2
+        default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
 
 #
 # Set to y for ptrace access to watch registers.
@@ -2149,7 +2150,7 @@ config NODES_SHIFT
 
 config HW_PERF_EVENTS
         bool "Enable hardware performance counter support for perf events"
-        depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON)
+        depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)
         default y
         help
           Enable hardware performance counter support for perf events. If