MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors.

Processors that support the mips64r2 ISA can in four instructions
convert a shifted PGD pointer stored in the upper bits of c0_context
into a usable pointer.  By doing this we save a memory load and
associated potential cache miss in the TLB exception handlers.

Since the upper bits of c0_context were holding the CPU number, we
move this to the upper bits of c0_xcontext which doesn't have enough
bits to hold the PGD pointer, but has plenty for the CPU number.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f6f3b990d837..20b223ba654d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1427,6 +1427,9 @@ config CPU_SUPPORTS_64BIT_KERNEL
         bool
 config CPU_SUPPORTS_HUGEPAGES
         bool
+config MIPS_PGD_C0_CONTEXT
+        bool
+        default y if 64BIT && CPU_MIPSR2
 
 #
 # Set to y for ptrace access to watch registers.