[MIPS] Dyntick support for SMTC:

The kernel currently only supports broadcasting of the timer interrupt
from a single timer, not multicasting into two multicast groups of
processors.  So the implemented mechanism for SMTC works by broadcasting
the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ecce3aab1981..d8c905840af5 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1368,6 +1368,7 @@ config MIPS_MT_SMTC
         depends on CPU_MIPS32_R2
         #depends on CPU_MIPS64_R2               # once there is hardware ...
         depends on SYS_SUPPORTS_MULTITHREADING
+        select GENERIC_CLOCKEVENTS_BROADCAST
         select CPU_MIPSR2_IRQ_VI
         select CPU_MIPSR2_IRQ_EI
         select CPU_MIPSR2_SRS
@@ -1537,6 +1538,9 @@ config CPU_HAS_SYNC
         depends on !CPU_R3000
         default y
 
+config GENERIC_CLOCKEVENTS_BROADCAST
+        bool
+
 #
 # Use the generic interrupt handling code in kernel/irq/:
 #