MIPS: Basic MSA context switching support

This patch adds support for context switching the MSA vector registers.
These 128 bit vector registers are aliased with the FP registers - an
FP register accesses the least significant bits of the vector register
with which it is aliased (ie. the register with the same index). Due to
both this & the requirement that the scalar FPU must be 64-bit (FR=1) if
enabled at the same time as MSA the kernel will enable MSA & scalar FP
at the same time for tasks which use MSA. If we restore the MSA vector
context then we might as well enable the scalar FPU since the reason it
was left disabled was to allow for lazy FP context restoring - but we
just restored the FP context as it's a subset of the vector context. If
we restore the FP context and have previously used MSA then we have to
restore the whole vector context anyway (see comment in
enable_restore_fp_context for details) so similarly we might as well
enable MSA.

Thus if a task does not use MSA then it will continue to behave as
without this patch - the scalar FP context will be saved & restored as
usual. But if a task executes an MSA instruction then it will save &
restore the vector context forever more.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6431/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 5 insertions, 4 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f627739eca49..50d854ce7f59 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2090,10 +2090,11 @@ config CPU_HAS_MSA
         help
           MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
           and a set of SIMD instructions to operate on them. When this option
-          is enabled the kernel will support detection of the MSA ASE. If you
-          know that your kernel will only be running on CPUs which do not
-          support MSA then you may wish to say N here to reduce the size of
-          your kernel.
+          is enabled the kernel will support allocating & switching MSA
+          vector register contexts. If you know that your kernel will only be
+          running on CPUs which do not support MSA or that your userland will
+          not be making use of it then you may wish to say N here to reduce
+          the size & complexity of your kernel.
 
           If unsure, say Y.