Merge branch 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr

Pull MIPS updates from Ralf Baechle:
 - Support for Imgtec's Aptiv family of MIPS cores.
 - Improved detection of BCM47xx configurations.
 - Fix hiberation for certain configurations.
 - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and
   systems.
 - Detection and support for the MIPS P5600 core.
 - A few more random fixes that didn't make 3.14.
 - Support for the EVA Extended Virtual Addressing
 - Switch Alchemy to the platform PATA driver
 - Complete unification of Alchemy support
 - Allow availability of I/O cache coherency to be runtime detected
 - Improvments to multiprocessing support for Imgtec platforms
 - A few microoptimizations
 - Cleanups of FPU support
 - Paul Gortmaker's fixes for the init stuff
 - Support for seccomp

* 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits)
  MIPS: CPC: Use __raw_ memory access functions
  MIPS: CM: use __raw_ memory access functions
  MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n
  MIPS: Malta: GIC IPIs may be used without MT
  MIPS: smp-mt: Use common GIC IPI implementation
  MIPS: smp-cmp: Remove incorrect core number probe
  MIPS: Fix gigaton of warning building with microMIPS.
  MIPS: Fix core number detection for MT cores
  MIPS: MT: core_nvpes function to retrieve VPE count
  MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n
  MIPS: Lasat: Replace del_timer by del_timer_sync
  MIPS: Malta: Setup PM I/O region on boot
  MIPS: Loongson: Add a Loongson-3 default config file
  MIPS: Loongson 3: Add CPU hotplug support
  MIPS: Loongson 3: Add Loongson-3 SMP support
  MIPS: Loongson: Add Loongson-3 Kconfig options
  MIPS: Loongson: Add swiotlb to support All-Memory DMA
  MIPS: Loongson 3: Add serial port support
  MIPS: Loongson 3: Add IRQ init and dispatch support
  MIPS: Loongson 3: Add HT-linked PCI support
  ...

1 files changed, 125 insertions, 10 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cb1da372346c..16d5ab1615b1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -10,6 +10,7 @@ config MIPS
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
         select HAVE_ARCH_KGDB
+        select HAVE_ARCH_SECCOMP_FILTER
         select HAVE_ARCH_TRACEHOOK
         select ARCH_HAVE_CUSTOM_GPIO_H
         select HAVE_FUNCTION_TRACER
@@ -62,6 +63,7 @@ config MIPS_ALCHEMY
         select CEVT_R4K
         select CSRC_R4K
         select IRQ_CPU
+        select DMA_MAYBE_COHERENT       # Au1000,1500,1100 aren't, rest is
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_APM_EMULATION
@@ -121,7 +123,7 @@ config BCM47XX
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
-        select EARLY_PRINTK_8250 if EARLY_PRINTK
+        select USE_GENERIC_EARLY_PRINTK_8250
         help
          Support for BCM47XX based boards
 
@@ -148,7 +150,6 @@ config MIPS_COBALT
         select CSRC_R4K
         select CEVT_GT641XX
         select DMA_NONCOHERENT
-        select EARLY_PRINTK_8250 if EARLY_PRINTK
         select HW_HAS_PCI
         select I8253
         select I8259
@@ -161,6 +162,7 @@ config MIPS_COBALT
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select USE_GENERIC_EARLY_PRINTK_8250
 
 config MACH_DECSTATION
         bool "DECstations"
@@ -233,7 +235,6 @@ config MACH_JZ4740
         select IRQ_CPU
         select ARCH_REQUIRE_GPIOLIB
         select SYS_HAS_EARLY_PRINTK
-        select HAVE_PWM
         select HAVE_CLK
         select GENERIC_IRQ_CHIP
 
@@ -318,6 +319,7 @@ config MIPS_MALTA
         select SWAP_IO_SPACE
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_HAS_CPU_MIPS32_R2
+        select SYS_HAS_CPU_MIPS32_R3_5
         select SYS_HAS_CPU_MIPS64_R1
         select SYS_HAS_CPU_MIPS64_R2
         select SYS_HAS_CPU_NEVADA
@@ -327,6 +329,7 @@ config MIPS_MALTA
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_SUPPORTS_MIPS_CMP
+        select SYS_SUPPORTS_MIPS_CPS
         select SYS_SUPPORTS_MULTITHREADING
         select SYS_SUPPORTS_SMARTMIPS
         select SYS_SUPPORTS_ZBOOT
@@ -671,6 +674,7 @@ config SNI_RM
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select USE_GENERIC_EARLY_PRINTK_8250
         help
           The SNI RM200/300/400 are MIPS-based machines manufactured by
           Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -775,7 +779,6 @@ config NLM_XLP_BOARD
         select CEVT_R4K
         select CSRC_R4K
         select IRQ_CPU
-        select ARCH_SUPPORTS_MSI
         select ZONE_DMA32 if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
@@ -861,6 +864,7 @@ config CEVT_R4K
         bool
 
 config CEVT_GIC
+        select MIPS_CM
         bool
 
 config CEVT_SB1250
@@ -879,6 +883,7 @@ config CSRC_R4K
         bool
 
 config CSRC_GIC
+        select MIPS_CM
         bool
 
 config CSRC_SB1250
@@ -1023,6 +1028,7 @@ config IRQ_GT641XX
         bool
 
 config IRQ_GIC
+        select MIPS_CM
         bool
 
 config PCI_GT64XXX_PCI0
@@ -1141,6 +1147,18 @@ choice
         prompt "CPU type"
         default CPU_R4X00
 
+config CPU_LOONGSON3
+        bool "Loongson 3 CPU"
+        depends on SYS_HAS_CPU_LOONGSON3
+        select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
+        select WEAK_ORDERING
+        select WEAK_REORDERING_BEYOND_LLSC
+        help
+                The Loongson 3 processor implements the MIPS64R2 instruction
+                set with many extensions.
+
 config CPU_LOONGSON2E
         bool "Loongson 2E"
         depends on SYS_HAS_CPU_LOONGSON2E
@@ -1196,6 +1214,7 @@ config CPU_MIPS32_R2
         select CPU_HAS_PREFETCH
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_MSA
         select HAVE_KVM
         help
           Choose this option to build a kernel for release 2 or later of the
@@ -1231,6 +1250,7 @@ config CPU_MIPS64_R2
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
         select CPU_SUPPORTS_HUGEPAGES
+        select CPU_SUPPORTS_MSA
         help
           Choose this option to build a kernel for release 2 or later of the
           MIPS64 architecture.  Many modern embedded systems with a 64-bit
@@ -1389,7 +1409,6 @@ config CPU_CAVIUM_OCTEON
         select LIBFDT
         select USE_OF
         select USB_EHCI_BIG_ENDIAN_MMIO
-        select SYS_HAS_DMA_OPS
         select MIPS_L1_CACHE_SHIFT_7
         help
           The Cavium Octeon processor is a highly integrated chip containing
@@ -1441,6 +1460,26 @@ config CPU_XLP
           Netlogic Microsystems XLP processors.
 endchoice
 
+config CPU_MIPS32_3_5_FEATURES
+        bool "MIPS32 Release 3.5 Features"
+        depends on SYS_HAS_CPU_MIPS32_R3_5
+        depends on CPU_MIPS32_R2
+        help
+          Choose this option to build a kernel for release 2 or later of the
+          MIPS32 architecture including features from the 3.5 release such as
+          support for Enhanced Virtual Addressing (EVA).
+
+config CPU_MIPS32_3_5_EVA
+        bool "Enhanced Virtual Addressing (EVA)"
+        depends on CPU_MIPS32_3_5_FEATURES
+        select EVA
+        default y
+        help
+          Choose this option if you want to enable the Enhanced Virtual
+          Addressing (EVA) on your MIPS32 core (such as proAptiv).
+          One of its primary benefits is an increase in the maximum size
+          of lowmem (up to 3GB). If unsure, say 'N' here.
+
 if CPU_LOONGSON2F
 config CPU_NOP_WORKAROUNDS
         bool
@@ -1516,6 +1555,10 @@ config CPU_BMIPS5000
         select SYS_SUPPORTS_SMP
         select SYS_SUPPORTS_HOTPLUG_CPU
 
+config SYS_HAS_CPU_LOONGSON3
+        bool
+        select CPU_SUPPORTS_CPUFREQ
+
 config SYS_HAS_CPU_LOONGSON2E
         bool
 
@@ -1534,6 +1577,9 @@ config SYS_HAS_CPU_MIPS32_R1
 config SYS_HAS_CPU_MIPS32_R2
         bool
 
+config SYS_HAS_CPU_MIPS32_R3_5
+        bool
+
 config SYS_HAS_CPU_MIPS64_R1
         bool
 
@@ -1650,6 +1696,9 @@ config CPU_MIPSR2
         bool
         default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
 
+config EVA
+        bool
+
 config SYS_SUPPORTS_32BIT_KERNEL
         bool
 config SYS_SUPPORTS_64BIT_KERNEL
@@ -1722,7 +1771,7 @@ choice
 
 config PAGE_SIZE_4KB
         bool "4kB"
-        depends on !CPU_LOONGSON2
+        depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
         help
          This option select the standard 4kB Linux page size.  On some
          R3000-family processors this is the only available page size.  Using
@@ -1863,6 +1912,7 @@ config MIPS_MT_SMP
         select CPU_MIPSR2_IRQ_VI
         select CPU_MIPSR2_IRQ_EI
         select SYNC_R4K
+        select MIPS_GIC_IPI
         select MIPS_MT
         select SMP
         select SMP_UP
@@ -1880,6 +1930,7 @@ config MIPS_MT_SMTC
         bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
         depends on CPU_MIPS32_R2
         depends on SYS_SUPPORTS_MULTITHREADING
+        depends on !MIPS_CPS
         select CPU_MIPSR2_IRQ_VI
         select CPU_MIPSR2_IRQ_EI
         select MIPS_MT
@@ -1987,13 +2038,45 @@ config MIPS_VPE_APSP_API_MT
         depends on MIPS_VPE_APSP_API && !MIPS_CMP
 
 config MIPS_CMP
-        bool "MIPS CMP support"
-        depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP
+        bool "MIPS CMP framework support (DEPRECATED)"
+        depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC
+        select MIPS_GIC_IPI
         select SYNC_R4K
         select WEAK_ORDERING
         default n
         help
-          Enable Coherency Manager processor (CMP) support.
+          Select this if you are using a bootloader which implements the "CMP
+          framework" protocol (ie. YAMON) and want your kernel to make use of
+          its ability to start secondary CPUs.
+
+          Unless you have a specific need, you should use CONFIG_MIPS_CPS
+          instead of this.
+
+config MIPS_CPS
+        bool "MIPS Coherent Processing System support"
+        depends on SYS_SUPPORTS_MIPS_CPS
+        select MIPS_CM
+        select MIPS_CPC
+        select MIPS_GIC_IPI
+        select SMP
+        select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
+        select SYS_SUPPORTS_SMP
+        select WEAK_ORDERING
+        help
+          Select this if you wish to run an SMP kernel across multiple cores
+          within a MIPS Coherent Processing System. When this option is
+          enabled the kernel will probe for other cores and boot them with
+          no external assistance. It is safe to enable this when hardware
+          support is unavailable.
+
+config MIPS_GIC_IPI
+        bool
+
+config MIPS_CM
+        bool
+
+config MIPS_CPC
+        bool
 
 config SB1_PASS_1_WORKAROUNDS
         bool
@@ -2036,6 +2119,21 @@ config CPU_MICROMIPS
           When this option is enabled the kernel will be built using the
           microMIPS ISA
 
+config CPU_HAS_MSA
+        bool "Support for the MIPS SIMD Architecture"
+        depends on CPU_SUPPORTS_MSA
+        default y
+        help
+          MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
+          and a set of SIMD instructions to operate on them. When this option
+          is enabled the kernel will support allocating & switching MSA
+          vector register contexts. If you know that your kernel will only be
+          running on CPUs which do not support MSA or that your userland will
+          not be making use of it then you may wish to say N here to reduce
+          the size & complexity of your kernel.
+
+          If unsure, say Y.
+
 config CPU_HAS_WB
         bool
 
@@ -2087,7 +2185,7 @@ config CPU_R4400_WORKAROUNDS
 #
 config HIGHMEM
         bool "High Memory Support"
-        depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
+        depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
 
 config CPU_SUPPORTS_HIGHMEM
         bool
@@ -2101,6 +2199,9 @@ config SYS_SUPPORTS_SMARTMIPS
 config SYS_SUPPORTS_MICROMIPS
         bool
 
+config CPU_SUPPORTS_MSA
+        bool
+
 config ARCH_FLATMEM_ENABLE
         def_bool y
         depends on !NUMA && !CPU_LOONGSON2
@@ -2174,6 +2275,9 @@ config SMP_UP
 config SYS_SUPPORTS_MIPS_CMP
         bool
 
+config SYS_SUPPORTS_MIPS_CPS
+        bool
+
 config SYS_SUPPORTS_SMP
         bool
 
@@ -2406,6 +2510,17 @@ config PCI
           your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
           say Y, otherwise N.
 
+config HT_PCI
+        bool "Support for HT-linked PCI"
+        default y
+        depends on CPU_LOONGSON3
+        select PCI
+        select PCI_DOMAINS
+        help
+          Loongson family machines use Hyper-Transport bus for inter-core
+          connection and device connection. The PCI bus is a subordinate
+          linked at HT. Choose Y for Loongson-3 based machines.
+
 config PCI_DOMAINS
         bool