MIPS: Add Cavium OCTEON to arch/mips/Kconfig

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 61 insertions, 2 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a5255e7c79e0..424ff744d07f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -595,6 +595,44 @@ config WR_PPMC
           This enables support for the Wind River MIPS32 4KC PPMC evaluation
           board, which is based on GT64120 bridge chip.
 
+config CAVIUM_OCTEON_SIMULATOR
+        bool "Support for the Cavium Networks Octeon Simulator"
+        select CEVT_R4K
+        select 64BIT_PHYS_ADDR
+        select DMA_COHERENT
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select CPU_CAVIUM_OCTEON
+        help
+          The Octeon simulator is software performance model of the Cavium
+          Octeon Processor. It supports simulating Octeon processors on x86
+          hardware.
+
+config CAVIUM_OCTEON_REFERENCE_BOARD
+        bool "Support for the Cavium Networks Octeon reference board"
+        select CEVT_R4K
+        select 64BIT_PHYS_ADDR
+        select DMA_COHERENT
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select SYS_HAS_EARLY_PRINTK
+        select CPU_CAVIUM_OCTEON
+        select SWAP_IO_SPACE
+        help
+          This option supports all of the Octeon reference boards from Cavium
+          Networks. It builds a kernel that dynamically determines the Octeon
+          CPU type and supports all known board reference implementations.
+          Some of the supported boards are:
+                EBT3000
+                EBH3000
+                EBH3100
+                Thunder
+                Kodama
+                Hikari
+          Say Y here for most Octeon reference boards.
+
 endchoice
 
 source "arch/mips/alchemy/Kconfig"
@@ -607,6 +645,7 @@ source "arch/mips/sgi-ip27/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
+source "arch/mips/cavium-octeon/Kconfig"
 
 endmenu
 
@@ -835,6 +874,9 @@ config IRQ_GT641XX
 config IRQ_GIC
         bool
 
+config IRQ_CPU_OCTEON
+        bool
+
 config MIPS_BOARDS_GEN
         bool
 
@@ -924,7 +966,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
         int
         default "4" if MACH_DECSTATION || MIKROTIK_RB532
-        default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
+        default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
         default "4" if PMC_MSP4200_EVAL
         default "5"
 
@@ -1185,6 +1227,23 @@ config CPU_SB1
         select CPU_SUPPORTS_HIGHMEM
         select WEAK_ORDERING
 
+config CPU_CAVIUM_OCTEON
+        bool "Cavium Octeon processor"
+        select IRQ_CPU
+        select IRQ_CPU_OCTEON
+        select CPU_HAS_PREFETCH
+        select CPU_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_SMP
+        select NR_CPUS_DEFAULT_16
+        select WEAK_ORDERING
+        select WEAK_REORDERING_BEYOND_LLSC
+        select CPU_SUPPORTS_HIGHMEM
+        help
+          The Cavium Octeon processor is a highly integrated chip containing
+          many ethernet hardware widgets for networking tasks. The processor
+          can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
+          Full details can be found at http://www.caviumnetworks.com.
+
 endchoice
 
 config SYS_HAS_CPU_LOONGSON2
@@ -1285,7 +1344,7 @@ config CPU_MIPSR1
 
 config CPU_MIPSR2
         bool
-        default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
+        default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
 
 config SYS_SUPPORTS_32BIT_KERNEL
         bool