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authorWu Zhangjin <wuzhangjin@gmail.com>2009-11-06 05:45:05 -0500
committerRalf Baechle <ralf@linux-mips.org>2009-12-16 20:57:10 -0500
commit6f7a251a259e5bf58a9ff334bdcfa3e42b6cb7a3 (patch)
treef5b65babda54c52073819629cc0f1047b5d1b413 /arch/mips/Kconfig
parent937893cf5be53203eabc6f4db29f86b1fdeea203 (diff)
MIPS: Loongson: Add basic Loongson 2F support
Loongson 2F has built-in DDR2 and PCI-X controller. The PCI-X controller has a programming interface similiar to the the FPGA northbridge used on Loongson 2E. The main differences between Loongson 2E and Loongson 2F include: 1. Loongson 2F has an extra address window configuration module, which is used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space. 2. Loongson 2F supports 8 levels of software configurable CPu frequency which can be configured in the LOONGSON_CHIPCFG0 register. The coming cpufreq and standby support are based on this feature. Loongson.h abstracts the modules and corresponding methods are abstracted. Add other Loongson-2F-specific source code including gcc 4.4 support, PCI memory space, PCI IO space, DMA address. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
-rw-r--r--arch/mips/Kconfig18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a16b6dfe3bc3..9618451011e1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1073,6 +1073,21 @@ config CPU_LOONGSON2E
1073 The Loongson 2E processor implements the MIPS III instruction set 1073 The Loongson 2E processor implements the MIPS III instruction set
1074 with many extensions. 1074 with many extensions.
1075 1075
1076 It has an internal FPGA northbridge, which is compatiable to
1077 bonito64.
1078
1079config CPU_LOONGSON2F
1080 bool "Loongson 2F"
1081 depends on SYS_HAS_CPU_LOONGSON2F
1082 select CPU_LOONGSON2
1083 help
1084 The Loongson 2F processor implements the MIPS III instruction set
1085 with many extensions.
1086
1087 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1088 have a similar programming interface with FPGA northbridge used in
1089 Loongson2E.
1090
1076config CPU_MIPS32_R1 1091config CPU_MIPS32_R1
1077 bool "MIPS32 Release 1" 1092 bool "MIPS32 Release 1"
1078 depends on SYS_HAS_CPU_MIPS32_R1 1093 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1317,6 +1332,9 @@ config CPU_LOONGSON2
1317config SYS_HAS_CPU_LOONGSON2E 1332config SYS_HAS_CPU_LOONGSON2E
1318 bool 1333 bool
1319 1334
1335config SYS_HAS_CPU_LOONGSON2F
1336 bool
1337
1320config SYS_HAS_CPU_MIPS32_R1 1338config SYS_HAS_CPU_MIPS32_R1
1321 bool 1339 bool
1322 1340