diff options
author | Michal Simek <monstr@monstr.eu> | 2009-03-27 09:25:49 -0400 |
---|---|---|
committer | Michal Simek <monstr@monstr.eu> | 2009-03-27 09:25:49 -0400 |
commit | eedbdab99fffb8ed71cac75a722088b8ace2583c (patch) | |
tree | 6f6b11f46a5d1b011a12dd61421cd1f2b10af237 /arch/microblaze | |
parent | 3be100114a352bb4b0eee5b6a847cf4f34ce28b1 (diff) |
microblaze_v8: Interrupt handling and timer support
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ingo Molnar <mingo@elte.hu>
Reviewed-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: John Linn <john.linn@xilinx.com>
Acked-by: John Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze')
-rw-r--r-- | arch/microblaze/include/asm/irq.h | 47 | ||||
-rw-r--r-- | arch/microblaze/kernel/intc.c | 172 | ||||
-rw-r--r-- | arch/microblaze/kernel/irq.c | 104 | ||||
-rw-r--r-- | arch/microblaze/kernel/timer.c | 262 |
4 files changed, 585 insertions, 0 deletions
diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h new file mode 100644 index 000000000000..db515deaa720 --- /dev/null +++ b/arch/microblaze/include/asm/irq.h | |||
@@ -0,0 +1,47 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2006 Atmark Techno, Inc. | ||
3 | * | ||
4 | * This file is subject to the terms and conditions of the GNU General Public | ||
5 | * License. See the file "COPYING" in the main directory of this archive | ||
6 | * for more details. | ||
7 | */ | ||
8 | |||
9 | #ifndef _ASM_MICROBLAZE_IRQ_H | ||
10 | #define _ASM_MICROBLAZE_IRQ_H | ||
11 | |||
12 | #define NR_IRQS 32 | ||
13 | |||
14 | #include <linux/interrupt.h> | ||
15 | |||
16 | extern unsigned int nr_irq; | ||
17 | |||
18 | #define NO_IRQ (-1) | ||
19 | |||
20 | static inline int irq_canonicalize(int irq) | ||
21 | { | ||
22 | return irq; | ||
23 | } | ||
24 | |||
25 | struct pt_regs; | ||
26 | extern void do_IRQ(struct pt_regs *regs); | ||
27 | |||
28 | /* irq_of_parse_and_map - Parse and Map an interrupt into linux virq space | ||
29 | * @device: Device node of the device whose interrupt is to be mapped | ||
30 | * @index: Index of the interrupt to map | ||
31 | * | ||
32 | * This function is a wrapper that chains of_irq_map_one() and | ||
33 | * irq_create_of_mapping() to make things easier to callers | ||
34 | */ | ||
35 | struct device_node; | ||
36 | extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index); | ||
37 | |||
38 | /** FIXME - not implement | ||
39 | * irq_dispose_mapping - Unmap an interrupt | ||
40 | * @virq: linux virq number of the interrupt to unmap | ||
41 | */ | ||
42 | static inline void irq_dispose_mapping(unsigned int virq) | ||
43 | { | ||
44 | return; | ||
45 | } | ||
46 | |||
47 | #endif /* _ASM_MICROBLAZE_IRQ_H */ | ||
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c new file mode 100644 index 000000000000..a69d3e3c2fd4 --- /dev/null +++ b/arch/microblaze/kernel/intc.c | |||
@@ -0,0 +1,172 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> | ||
3 | * Copyright (C) 2007-2009 PetaLogix | ||
4 | * Copyright (C) 2006 Atmark Techno, Inc. | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | |||
11 | #include <linux/init.h> | ||
12 | #include <linux/irq.h> | ||
13 | #include <asm/page.h> | ||
14 | #include <linux/io.h> | ||
15 | |||
16 | #include <asm/prom.h> | ||
17 | #include <asm/irq.h> | ||
18 | |||
19 | #ifdef CONFIG_SELFMOD_INTC | ||
20 | #include <asm/selfmod.h> | ||
21 | #define INTC_BASE BARRIER_BASE_ADDR | ||
22 | #else | ||
23 | static unsigned int intc_baseaddr; | ||
24 | #define INTC_BASE intc_baseaddr | ||
25 | #endif | ||
26 | |||
27 | unsigned int nr_irq; | ||
28 | |||
29 | /* No one else should require these constants, so define them locally here. */ | ||
30 | #define ISR 0x00 /* Interrupt Status Register */ | ||
31 | #define IPR 0x04 /* Interrupt Pending Register */ | ||
32 | #define IER 0x08 /* Interrupt Enable Register */ | ||
33 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | ||
34 | #define SIE 0x10 /* Set Interrupt Enable bits */ | ||
35 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | ||
36 | #define IVR 0x18 /* Interrupt Vector Register */ | ||
37 | #define MER 0x1c /* Master Enable Register */ | ||
38 | |||
39 | #define MER_ME (1<<0) | ||
40 | #define MER_HIE (1<<1) | ||
41 | |||
42 | static void intc_enable_or_unmask(unsigned int irq) | ||
43 | { | ||
44 | pr_debug("enable_or_unmask: %d\n", irq); | ||
45 | out_be32(INTC_BASE + SIE, 1 << irq); | ||
46 | } | ||
47 | |||
48 | static void intc_disable_or_mask(unsigned int irq) | ||
49 | { | ||
50 | pr_debug("disable: %d\n", irq); | ||
51 | out_be32(INTC_BASE + CIE, 1 << irq); | ||
52 | } | ||
53 | |||
54 | static void intc_ack(unsigned int irq) | ||
55 | { | ||
56 | pr_debug("ack: %d\n", irq); | ||
57 | out_be32(INTC_BASE + IAR, 1 << irq); | ||
58 | } | ||
59 | |||
60 | static void intc_mask_ack(unsigned int irq) | ||
61 | { | ||
62 | unsigned long mask = 1 << irq; | ||
63 | pr_debug("disable_and_ack: %d\n", irq); | ||
64 | out_be32(INTC_BASE + CIE, mask); | ||
65 | out_be32(INTC_BASE + IAR, mask); | ||
66 | } | ||
67 | |||
68 | static void intc_end(unsigned int irq) | ||
69 | { | ||
70 | unsigned long mask = 1 << irq; | ||
71 | pr_debug("end: %d\n", irq); | ||
72 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { | ||
73 | out_be32(INTC_BASE + SIE, mask); | ||
74 | /* ack level sensitive intr */ | ||
75 | if (irq_desc[irq].status & IRQ_LEVEL) | ||
76 | out_be32(INTC_BASE + IAR, mask); | ||
77 | } | ||
78 | } | ||
79 | |||
80 | static struct irq_chip intc_dev = { | ||
81 | .name = "Xilinx INTC", | ||
82 | .unmask = intc_enable_or_unmask, | ||
83 | .mask = intc_disable_or_mask, | ||
84 | .ack = intc_ack, | ||
85 | .mask_ack = intc_mask_ack, | ||
86 | .end = intc_end, | ||
87 | }; | ||
88 | |||
89 | unsigned int get_irq(struct pt_regs *regs) | ||
90 | { | ||
91 | int irq; | ||
92 | |||
93 | /* | ||
94 | * NOTE: This function is the one that needs to be improved in | ||
95 | * order to handle multiple interrupt controllers. It currently | ||
96 | * is hardcoded to check for interrupts only on the first INTC. | ||
97 | */ | ||
98 | irq = in_be32(INTC_BASE + IVR); | ||
99 | pr_debug("get_irq: %d\n", irq); | ||
100 | |||
101 | return irq; | ||
102 | } | ||
103 | |||
104 | void __init init_IRQ(void) | ||
105 | { | ||
106 | u32 i, j, intr_type; | ||
107 | struct device_node *intc = NULL; | ||
108 | #ifdef CONFIG_SELFMOD_INTC | ||
109 | unsigned int intc_baseaddr = 0; | ||
110 | static int arr_func[] = { | ||
111 | (int)&get_irq, | ||
112 | (int)&intc_enable_or_unmask, | ||
113 | (int)&intc_disable_or_mask, | ||
114 | (int)&intc_mask_ack, | ||
115 | (int)&intc_ack, | ||
116 | (int)&intc_end, | ||
117 | 0 | ||
118 | }; | ||
119 | #endif | ||
120 | static char *intc_list[] = { | ||
121 | "xlnx,xps-intc-1.00.a", | ||
122 | "xlnx,opb-intc-1.00.c", | ||
123 | "xlnx,opb-intc-1.00.b", | ||
124 | "xlnx,opb-intc-1.00.a", | ||
125 | NULL | ||
126 | }; | ||
127 | |||
128 | for (j = 0; intc_list[j] != NULL; j++) { | ||
129 | intc = of_find_compatible_node(NULL, NULL, intc_list[j]); | ||
130 | if (intc) | ||
131 | break; | ||
132 | } | ||
133 | |||
134 | intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL); | ||
135 | intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE); | ||
136 | nr_irq = *(int *) of_get_property(intc, "xlnx,num-intr-inputs", NULL); | ||
137 | |||
138 | intr_type = | ||
139 | *(int *) of_get_property(intc, "xlnx,kind-of-intr", NULL); | ||
140 | if (intr_type >= (1 << nr_irq)) | ||
141 | printk(KERN_INFO " ERROR: Mishmash in king-of-intr param\n"); | ||
142 | |||
143 | #ifdef CONFIG_SELFMOD_INTC | ||
144 | selfmod_function((int *) arr_func, intc_baseaddr); | ||
145 | #endif | ||
146 | printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n", | ||
147 | intc_list[j], intc_baseaddr, nr_irq, intr_type); | ||
148 | |||
149 | /* | ||
150 | * Disable all external interrupts until they are | ||
151 | * explicity requested. | ||
152 | */ | ||
153 | out_be32(intc_baseaddr + IER, 0); | ||
154 | |||
155 | /* Acknowledge any pending interrupts just in case. */ | ||
156 | out_be32(intc_baseaddr + IAR, 0xffffffff); | ||
157 | |||
158 | /* Turn on the Master Enable. */ | ||
159 | out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); | ||
160 | |||
161 | for (i = 0; i < nr_irq; ++i) { | ||
162 | if (intr_type & (0x00000001 << i)) { | ||
163 | set_irq_chip_and_handler_name(i, &intc_dev, | ||
164 | handle_edge_irq, intc_dev.name); | ||
165 | irq_desc[i].status &= ~IRQ_LEVEL; | ||
166 | } else { | ||
167 | set_irq_chip_and_handler_name(i, &intc_dev, | ||
168 | handle_level_irq, intc_dev.name); | ||
169 | irq_desc[i].status |= IRQ_LEVEL; | ||
170 | } | ||
171 | } | ||
172 | } | ||
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c new file mode 100644 index 000000000000..f688ee93e3b9 --- /dev/null +++ b/arch/microblaze/kernel/irq.c | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> | ||
3 | * Copyright (C) 2007-2009 PetaLogix | ||
4 | * Copyright (C) 2006 Atmark Techno, Inc. | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | |||
11 | #include <linux/init.h> | ||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/hardirq.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/irqflags.h> | ||
16 | #include <linux/seq_file.h> | ||
17 | #include <linux/kernel_stat.h> | ||
18 | #include <linux/irq.h> | ||
19 | |||
20 | #include <asm/prom.h> | ||
21 | |||
22 | unsigned int irq_of_parse_and_map(struct device_node *dev, int index) | ||
23 | { | ||
24 | struct of_irq oirq; | ||
25 | |||
26 | if (of_irq_map_one(dev, index, &oirq)) | ||
27 | return NO_IRQ; | ||
28 | |||
29 | return oirq.specifier[0]; | ||
30 | } | ||
31 | EXPORT_SYMBOL_GPL(irq_of_parse_and_map); | ||
32 | |||
33 | /* | ||
34 | * 'what should we do if we get a hw irq event on an illegal vector'. | ||
35 | * each architecture has to answer this themselves. | ||
36 | */ | ||
37 | void ack_bad_irq(unsigned int irq) | ||
38 | { | ||
39 | printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq); | ||
40 | } | ||
41 | |||
42 | static u32 concurrent_irq; | ||
43 | |||
44 | void do_IRQ(struct pt_regs *regs) | ||
45 | { | ||
46 | unsigned int irq; | ||
47 | struct pt_regs *old_regs = set_irq_regs(regs); | ||
48 | |||
49 | irq_enter(); | ||
50 | irq = get_irq(regs); | ||
51 | next_irq: | ||
52 | BUG_ON(irq == -1U); | ||
53 | generic_handle_irq(irq); | ||
54 | |||
55 | irq = get_irq(regs); | ||
56 | if (irq != -1U) { | ||
57 | pr_debug("next irq: %d\n", irq); | ||
58 | ++concurrent_irq; | ||
59 | goto next_irq; | ||
60 | } | ||
61 | |||
62 | irq_exit(); | ||
63 | set_irq_regs(old_regs); | ||
64 | } | ||
65 | |||
66 | int show_interrupts(struct seq_file *p, void *v) | ||
67 | { | ||
68 | int i = *(loff_t *) v, j; | ||
69 | struct irqaction *action; | ||
70 | unsigned long flags; | ||
71 | |||
72 | if (i == 0) { | ||
73 | seq_printf(p, " "); | ||
74 | for_each_online_cpu(j) | ||
75 | seq_printf(p, "CPU%-8d", j); | ||
76 | seq_putc(p, '\n'); | ||
77 | } | ||
78 | |||
79 | if (i < nr_irq) { | ||
80 | spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
81 | action = irq_desc[i].action; | ||
82 | if (!action) | ||
83 | goto skip; | ||
84 | seq_printf(p, "%3d: ", i); | ||
85 | #ifndef CONFIG_SMP | ||
86 | seq_printf(p, "%10u ", kstat_irqs(i)); | ||
87 | #else | ||
88 | for_each_online_cpu(j) | ||
89 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | ||
90 | #endif | ||
91 | seq_printf(p, " %8s", irq_desc[i].status & | ||
92 | IRQ_LEVEL ? "level" : "edge"); | ||
93 | seq_printf(p, " %8s", irq_desc[i].chip->name); | ||
94 | seq_printf(p, " %s", action->name); | ||
95 | |||
96 | for (action = action->next; action; action = action->next) | ||
97 | seq_printf(p, ", %s", action->name); | ||
98 | |||
99 | seq_putc(p, '\n'); | ||
100 | skip: | ||
101 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
102 | } | ||
103 | return 0; | ||
104 | } | ||
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c new file mode 100644 index 000000000000..05a497eefd78 --- /dev/null +++ b/arch/microblaze/kernel/timer.c | |||
@@ -0,0 +1,262 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> | ||
3 | * Copyright (C) 2007-2009 PetaLogix | ||
4 | * Copyright (C) 2006 Atmark Techno, Inc. | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | |||
11 | #include <linux/init.h> | ||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/param.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/profile.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/delay.h> | ||
18 | #include <linux/sched.h> | ||
19 | #include <linux/spinlock.h> | ||
20 | #include <linux/err.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/clocksource.h> | ||
23 | #include <linux/clockchips.h> | ||
24 | #include <linux/io.h> | ||
25 | #include <asm/cpuinfo.h> | ||
26 | #include <asm/setup.h> | ||
27 | #include <asm/prom.h> | ||
28 | #include <asm/irq.h> | ||
29 | #include <asm/system.h> | ||
30 | |||
31 | #ifdef CONFIG_SELFMOD_TIMER | ||
32 | #include <asm/selfmod.h> | ||
33 | #define TIMER_BASE BARRIER_BASE_ADDR | ||
34 | #else | ||
35 | static unsigned int timer_baseaddr; | ||
36 | #define TIMER_BASE timer_baseaddr | ||
37 | #endif | ||
38 | |||
39 | #define TCSR0 (0x00) | ||
40 | #define TLR0 (0x04) | ||
41 | #define TCR0 (0x08) | ||
42 | #define TCSR1 (0x10) | ||
43 | #define TLR1 (0x14) | ||
44 | #define TCR1 (0x18) | ||
45 | |||
46 | #define TCSR_MDT (1<<0) | ||
47 | #define TCSR_UDT (1<<1) | ||
48 | #define TCSR_GENT (1<<2) | ||
49 | #define TCSR_CAPT (1<<3) | ||
50 | #define TCSR_ARHT (1<<4) | ||
51 | #define TCSR_LOAD (1<<5) | ||
52 | #define TCSR_ENIT (1<<6) | ||
53 | #define TCSR_ENT (1<<7) | ||
54 | #define TCSR_TINT (1<<8) | ||
55 | #define TCSR_PWMA (1<<9) | ||
56 | #define TCSR_ENALL (1<<10) | ||
57 | |||
58 | static inline void microblaze_timer0_stop(void) | ||
59 | { | ||
60 | out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT); | ||
61 | } | ||
62 | |||
63 | static inline void microblaze_timer0_start_periodic(unsigned long load_val) | ||
64 | { | ||
65 | if (!load_val) | ||
66 | load_val = 1; | ||
67 | out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */ | ||
68 | |||
69 | /* load the initial value */ | ||
70 | out_be32(TIMER_BASE + TCSR0, TCSR_LOAD); | ||
71 | |||
72 | /* see timer data sheet for detail | ||
73 | * !ENALL - don't enable 'em all | ||
74 | * !PWMA - disable pwm | ||
75 | * TINT - clear interrupt status | ||
76 | * ENT- enable timer itself | ||
77 | * EINT - enable interrupt | ||
78 | * !LOAD - clear the bit to let go | ||
79 | * ARHT - auto reload | ||
80 | * !CAPT - no external trigger | ||
81 | * !GENT - no external signal | ||
82 | * UDT - set the timer as down counter | ||
83 | * !MDT0 - generate mode | ||
84 | */ | ||
85 | out_be32(TIMER_BASE + TCSR0, | ||
86 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); | ||
87 | } | ||
88 | |||
89 | static inline void microblaze_timer0_start_oneshot(unsigned long load_val) | ||
90 | { | ||
91 | if (!load_val) | ||
92 | load_val = 1; | ||
93 | out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */ | ||
94 | |||
95 | /* load the initial value */ | ||
96 | out_be32(TIMER_BASE + TCSR0, TCSR_LOAD); | ||
97 | |||
98 | out_be32(TIMER_BASE + TCSR0, | ||
99 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); | ||
100 | } | ||
101 | |||
102 | static int microblaze_timer_set_next_event(unsigned long delta, | ||
103 | struct clock_event_device *dev) | ||
104 | { | ||
105 | pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); | ||
106 | microblaze_timer0_start_oneshot(delta); | ||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | static void microblaze_timer_set_mode(enum clock_event_mode mode, | ||
111 | struct clock_event_device *evt) | ||
112 | { | ||
113 | switch (mode) { | ||
114 | case CLOCK_EVT_MODE_PERIODIC: | ||
115 | printk(KERN_INFO "%s: periodic\n", __func__); | ||
116 | microblaze_timer0_start_periodic(cpuinfo.freq_div_hz); | ||
117 | break; | ||
118 | case CLOCK_EVT_MODE_ONESHOT: | ||
119 | printk(KERN_INFO "%s: oneshot\n", __func__); | ||
120 | break; | ||
121 | case CLOCK_EVT_MODE_UNUSED: | ||
122 | printk(KERN_INFO "%s: unused\n", __func__); | ||
123 | break; | ||
124 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
125 | printk(KERN_INFO "%s: shutdown\n", __func__); | ||
126 | microblaze_timer0_stop(); | ||
127 | break; | ||
128 | case CLOCK_EVT_MODE_RESUME: | ||
129 | printk(KERN_INFO "%s: resume\n", __func__); | ||
130 | break; | ||
131 | } | ||
132 | } | ||
133 | |||
134 | static struct clock_event_device clockevent_microblaze_timer = { | ||
135 | .name = "microblaze_clockevent", | ||
136 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | ||
137 | .shift = 24, | ||
138 | .rating = 300, | ||
139 | .set_next_event = microblaze_timer_set_next_event, | ||
140 | .set_mode = microblaze_timer_set_mode, | ||
141 | }; | ||
142 | |||
143 | static inline void timer_ack(void) | ||
144 | { | ||
145 | out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0)); | ||
146 | } | ||
147 | |||
148 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | ||
149 | { | ||
150 | struct clock_event_device *evt = &clockevent_microblaze_timer; | ||
151 | #ifdef CONFIG_HEART_BEAT | ||
152 | heartbeat(); | ||
153 | #endif | ||
154 | timer_ack(); | ||
155 | evt->event_handler(evt); | ||
156 | return IRQ_HANDLED; | ||
157 | } | ||
158 | |||
159 | static struct irqaction timer_irqaction = { | ||
160 | .handler = timer_interrupt, | ||
161 | .flags = IRQF_DISABLED | IRQF_TIMER, | ||
162 | .name = "timer", | ||
163 | .dev_id = &clockevent_microblaze_timer, | ||
164 | }; | ||
165 | |||
166 | static __init void microblaze_clockevent_init(void) | ||
167 | { | ||
168 | clockevent_microblaze_timer.mult = | ||
169 | div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC, | ||
170 | clockevent_microblaze_timer.shift); | ||
171 | clockevent_microblaze_timer.max_delta_ns = | ||
172 | clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer); | ||
173 | clockevent_microblaze_timer.min_delta_ns = | ||
174 | clockevent_delta2ns(1, &clockevent_microblaze_timer); | ||
175 | clockevent_microblaze_timer.cpumask = cpumask_of(0); | ||
176 | clockevents_register_device(&clockevent_microblaze_timer); | ||
177 | } | ||
178 | |||
179 | static cycle_t microblaze_read(void) | ||
180 | { | ||
181 | /* reading actual value of timer 1 */ | ||
182 | return (cycle_t) (in_be32(TIMER_BASE + TCR1)); | ||
183 | } | ||
184 | |||
185 | static struct clocksource clocksource_microblaze = { | ||
186 | .name = "microblaze_clocksource", | ||
187 | .rating = 300, | ||
188 | .read = microblaze_read, | ||
189 | .mask = CLOCKSOURCE_MASK(32), | ||
190 | .shift = 24, /* I can shift it */ | ||
191 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
192 | }; | ||
193 | |||
194 | static int __init microblaze_clocksource_init(void) | ||
195 | { | ||
196 | clocksource_microblaze.mult = | ||
197 | clocksource_hz2mult(cpuinfo.cpu_clock_freq, | ||
198 | clocksource_microblaze.shift); | ||
199 | if (clocksource_register(&clocksource_microblaze)) | ||
200 | panic("failed to register clocksource"); | ||
201 | |||
202 | /* stop timer1 */ | ||
203 | out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT); | ||
204 | /* start timer1 - up counting without interrupt */ | ||
205 | out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); | ||
206 | return 0; | ||
207 | } | ||
208 | |||
209 | void __init time_init(void) | ||
210 | { | ||
211 | u32 irq, i = 0; | ||
212 | u32 timer_num = 1; | ||
213 | struct device_node *timer = NULL; | ||
214 | #ifdef CONFIG_SELFMOD_TIMER | ||
215 | unsigned int timer_baseaddr = 0; | ||
216 | int arr_func[] = { | ||
217 | (int)µblaze_read, | ||
218 | (int)&timer_interrupt, | ||
219 | (int)µblaze_clocksource_init, | ||
220 | (int)µblaze_timer_set_mode, | ||
221 | (int)µblaze_timer_set_next_event, | ||
222 | 0 | ||
223 | }; | ||
224 | #endif | ||
225 | char *timer_list[] = { | ||
226 | "xlnx,xps-timer-1.00.a", | ||
227 | "xlnx,opb-timer-1.00.b", | ||
228 | "xlnx,opb-timer-1.00.a", | ||
229 | NULL | ||
230 | }; | ||
231 | |||
232 | for (i = 0; timer_list[i] != NULL; i++) { | ||
233 | timer = of_find_compatible_node(NULL, NULL, timer_list[i]); | ||
234 | if (timer) | ||
235 | break; | ||
236 | } | ||
237 | |||
238 | timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL); | ||
239 | timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE); | ||
240 | irq = *(int *) of_get_property(timer, "interrupts", NULL); | ||
241 | timer_num = | ||
242 | *(int *) of_get_property(timer, "xlnx,one-timer-only", NULL); | ||
243 | if (timer_num) { | ||
244 | printk(KERN_EMERG "Please enable two timers in HW\n"); | ||
245 | BUG(); | ||
246 | } | ||
247 | |||
248 | #ifdef CONFIG_SELFMOD_TIMER | ||
249 | selfmod_function((int *) arr_func, timer_baseaddr); | ||
250 | #endif | ||
251 | printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n", | ||
252 | timer_list[i], timer_baseaddr, irq); | ||
253 | |||
254 | cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ; | ||
255 | |||
256 | setup_irq(irq, &timer_irqaction); | ||
257 | #ifdef CONFIG_HEART_BEAT | ||
258 | setup_heartbeat(); | ||
259 | #endif | ||
260 | microblaze_clocksource_init(); | ||
261 | microblaze_clockevent_init(); | ||
262 | } | ||