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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-10 21:17:26 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-06-07 19:08:38 -0400
commitbf13a6fa09b8db7f1fd59b5e2ed3674a89a6a25c (patch)
treeee99085ebf2843e613f7643aaeebecd7bf95215b /arch/microblaze
parent72bdee79f89ffc9ce425611cdaf88d28a96b8b66 (diff)
microblaze/pci: Move the remains of pci_32.c to pci-common.c
There's no point in keeping this separate. Even if microblaze grows a 64-bit variant, it will probably be able to re-use that code as-is Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/microblaze')
-rw-r--r--arch/microblaze/pci/Makefile2
-rw-r--r--arch/microblaze/pci/pci-common.c112
-rw-r--r--arch/microblaze/pci/pci_32.c138
3 files changed, 113 insertions, 139 deletions
diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile
index 9889cc2e1294..d1114fbd4780 100644
--- a/arch/microblaze/pci/Makefile
+++ b/arch/microblaze/pci/Makefile
@@ -2,5 +2,5 @@
2# Makefile 2# Makefile
3# 3#
4 4
5obj-$(CONFIG_PCI) += pci_32.o pci-common.o indirect_pci.o iomap.o 5obj-$(CONFIG_PCI) += pci-common.o indirect_pci.o iomap.o
6obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o 6obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 53599067d2f9..041b1d86d75b 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -50,6 +50,11 @@ unsigned int pci_flags;
50 50
51static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 51static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
52 52
53unsigned long isa_io_base;
54unsigned long pci_dram_offset;
55static int pci_bus_count;
56
57
53void set_pci_dma_ops(struct dma_map_ops *dma_ops) 58void set_pci_dma_ops(struct dma_map_ops *dma_ops)
54{ 59{
55 pci_dma_ops = dma_ops; 60 pci_dma_ops = dma_ops;
@@ -1558,6 +1563,112 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1558 (unsigned long)hose->io_base_virt - _IO_BASE); 1563 (unsigned long)hose->io_base_virt - _IO_BASE);
1559} 1564}
1560 1565
1566struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1567{
1568 struct pci_controller *hose = bus->sysdata;
1569
1570 return of_node_get(hose->dn);
1571}
1572
1573static void __devinit pcibios_scan_phb(struct pci_controller *hose)
1574{
1575 struct pci_bus *bus;
1576 struct device_node *node = hose->dn;
1577 unsigned long io_offset;
1578 struct resource *res = &hose->io_resource;
1579
1580 pr_debug("PCI: Scanning PHB %s\n",
1581 node ? node->full_name : "<NO NAME>");
1582
1583 /* Create an empty bus for the toplevel */
1584 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
1585 if (bus == NULL) {
1586 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
1587 hose->global_number);
1588 return;
1589 }
1590 bus->secondary = hose->first_busno;
1591 hose->bus = bus;
1592
1593 /* Fixup IO space offset */
1594 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1595 res->start = (res->start + io_offset) & 0xffffffffu;
1596 res->end = (res->end + io_offset) & 0xffffffffu;
1597
1598 /* Wire up PHB bus resources */
1599 pcibios_setup_phb_resources(hose);
1600
1601 /* Scan children */
1602 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1603}
1604
1605static int __init pcibios_init(void)
1606{
1607 struct pci_controller *hose, *tmp;
1608 int next_busno = 0;
1609
1610 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1611
1612 /* Scan all of the recorded PCI controllers. */
1613 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1614 hose->last_busno = 0xff;
1615 pcibios_scan_phb(hose);
1616 printk(KERN_INFO "calling pci_bus_add_devices()\n");
1617 pci_bus_add_devices(hose->bus);
1618 if (next_busno <= hose->last_busno)
1619 next_busno = hose->last_busno + 1;
1620 }
1621 pci_bus_count = next_busno;
1622
1623 /* Call common code to handle resource allocation */
1624 pcibios_resource_survey();
1625
1626 return 0;
1627}
1628
1629subsys_initcall(pcibios_init);
1630
1631static struct pci_controller *pci_bus_to_hose(int bus)
1632{
1633 struct pci_controller *hose, *tmp;
1634
1635 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1636 if (bus >= hose->first_busno && bus <= hose->last_busno)
1637 return hose;
1638 return NULL;
1639}
1640
1641/* Provide information on locations of various I/O regions in physical
1642 * memory. Do this on a per-card basis so that we choose the right
1643 * root bridge.
1644 * Note that the returned IO or memory base is a physical address
1645 */
1646
1647long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1648{
1649 struct pci_controller *hose;
1650 long result = -EOPNOTSUPP;
1651
1652 hose = pci_bus_to_hose(bus);
1653 if (!hose)
1654 return -ENODEV;
1655
1656 switch (which) {
1657 case IOBASE_BRIDGE_NUMBER:
1658 return (long)hose->first_busno;
1659 case IOBASE_MEMORY:
1660 return (long)hose->pci_mem_offset;
1661 case IOBASE_IO:
1662 return (long)hose->io_base_phys;
1663 case IOBASE_ISA_IO:
1664 return (long)isa_io_base;
1665 case IOBASE_ISA_MEM:
1666 return (long)isa_mem_base;
1667 }
1668
1669 return result;
1670}
1671
1561/* 1672/*
1562 * Null PCI config access functions, for the case when we can't 1673 * Null PCI config access functions, for the case when we can't
1563 * find a hose. 1674 * find a hose.
@@ -1626,3 +1737,4 @@ int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1626{ 1737{
1627 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1738 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1628} 1739}
1740
diff --git a/arch/microblaze/pci/pci_32.c b/arch/microblaze/pci/pci_32.c
deleted file mode 100644
index ab3c4d40a82c..000000000000
--- a/arch/microblaze/pci/pci_32.c
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * Common pmac/prep/chrp pci routines. -- Cort
3 */
4
5#include <linux/kernel.h>
6#include <linux/pci.h>
7#include <linux/delay.h>
8#include <linux/string.h>
9#include <linux/init.h>
10#include <linux/capability.h>
11#include <linux/sched.h>
12#include <linux/errno.h>
13#include <linux/bootmem.h>
14#include <linux/irq.h>
15#include <linux/list.h>
16#include <linux/of.h>
17#include <linux/slab.h>
18
19#include <asm/processor.h>
20#include <asm/io.h>
21#include <asm/prom.h>
22#include <asm/sections.h>
23#include <asm/pci-bridge.h>
24#include <asm/byteorder.h>
25#include <asm/uaccess.h>
26
27#undef DEBUG
28
29unsigned long isa_io_base;
30unsigned long pci_dram_offset;
31static int pci_bus_count;
32
33struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
34{
35 struct pci_controller *hose = bus->sysdata;
36
37 return of_node_get(hose->dn);
38}
39
40static void __devinit pcibios_scan_phb(struct pci_controller *hose)
41{
42 struct pci_bus *bus;
43 struct device_node *node = hose->dn;
44 unsigned long io_offset;
45 struct resource *res = &hose->io_resource;
46
47 pr_debug("PCI: Scanning PHB %s\n",
48 node ? node->full_name : "<NO NAME>");
49
50 /* Create an empty bus for the toplevel */
51 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
52 if (bus == NULL) {
53 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
54 hose->global_number);
55 return;
56 }
57 bus->secondary = hose->first_busno;
58 hose->bus = bus;
59
60 /* Fixup IO space offset */
61 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
62 res->start = (res->start + io_offset) & 0xffffffffu;
63 res->end = (res->end + io_offset) & 0xffffffffu;
64
65 /* Wire up PHB bus resources */
66 pcibios_setup_phb_resources(hose);
67
68 /* Scan children */
69 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
70}
71
72static int __init pcibios_init(void)
73{
74 struct pci_controller *hose, *tmp;
75 int next_busno = 0;
76
77 printk(KERN_INFO "PCI: Probing PCI hardware\n");
78
79 /* Scan all of the recorded PCI controllers. */
80 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
81 hose->last_busno = 0xff;
82 pcibios_scan_phb(hose);
83 printk(KERN_INFO "calling pci_bus_add_devices()\n");
84 pci_bus_add_devices(hose->bus);
85 if (next_busno <= hose->last_busno)
86 next_busno = hose->last_busno + 1;
87 }
88 pci_bus_count = next_busno;
89
90 /* Call common code to handle resource allocation */
91 pcibios_resource_survey();
92
93 return 0;
94}
95
96subsys_initcall(pcibios_init);
97
98static struct pci_controller*
99pci_bus_to_hose(int bus)
100{
101 struct pci_controller *hose, *tmp;
102
103 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
104 if (bus >= hose->first_busno && bus <= hose->last_busno)
105 return hose;
106 return NULL;
107}
108
109/* Provide information on locations of various I/O regions in physical
110 * memory. Do this on a per-card basis so that we choose the right
111 * root bridge.
112 * Note that the returned IO or memory base is a physical address
113 */
114
115long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
116{
117 struct pci_controller *hose;
118 long result = -EOPNOTSUPP;
119
120 hose = pci_bus_to_hose(bus);
121 if (!hose)
122 return -ENODEV;
123
124 switch (which) {
125 case IOBASE_BRIDGE_NUMBER:
126 return (long)hose->first_busno;
127 case IOBASE_MEMORY:
128 return (long)hose->pci_mem_offset;
129 case IOBASE_IO:
130 return (long)hose->io_base_phys;
131 case IOBASE_ISA_IO:
132 return (long)isa_io_base;
133 case IOBASE_ISA_MEM:
134 return (long)isa_mem_base;
135 }
136
137 return result;
138}