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authorMichal Simek <monstr@monstr.eu>2010-03-22 15:43:27 -0400
committerMichal Simek <monstr@monstr.eu>2010-04-01 02:38:23 -0400
commit3765d6958dfff34a15588e23c5d1274e1f6ba200 (patch)
tree32aeae698e777fa424749c84aef1571e8df4fbcb /arch/microblaze
parentbd1637d63e82aaf732ffbe907ba887fa12e82df4 (diff)
microblaze: Use instruction with delay slot
Sync labels. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze')
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S13
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 5d8c3de58b0c..995a2123635b 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -721,9 +721,8 @@ ex_handler_done:
721 * Many of these bits are software only. Bits we don't set 721 * Many of these bits are software only. Bits we don't set
722 * here we (properly should) assume have the appropriate value. 722 * here we (properly should) assume have the appropriate value.
723 */ 723 */
724 brid finish_tlb_load
724 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 725 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
725
726 bri finish_tlb_load
727 ex7: 726 ex7:
728 /* The bailout. Restore registers to pre-exception conditions 727 /* The bailout. Restore registers to pre-exception conditions
729 * and call the heavyweights to help us out. 728 * and call the heavyweights to help us out.
@@ -779,7 +778,7 @@ ex_handler_done:
779 lwi r4, r5, 0 /* Get Linux PTE */ 778 lwi r4, r5, 0 /* Get Linux PTE */
780 779
781 andi r6, r4, _PAGE_PRESENT 780 andi r6, r4, _PAGE_PRESENT
782 beqi r6, ex7 781 beqi r6, ex10
783 782
784 ori r4, r4, _PAGE_ACCESSED 783 ori r4, r4, _PAGE_ACCESSED
785 swi r4, r5, 0 784 swi r4, r5, 0
@@ -792,9 +791,8 @@ ex_handler_done:
792 * Many of these bits are software only. Bits we don't set 791 * Many of these bits are software only. Bits we don't set
793 * here we (properly should) assume have the appropriate value. 792 * here we (properly should) assume have the appropriate value.
794 */ 793 */
794 brid finish_tlb_load
795 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 795 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
796
797 bri finish_tlb_load
798 ex10: 796 ex10:
799 /* The bailout. Restore registers to pre-exception conditions 797 /* The bailout. Restore registers to pre-exception conditions
800 * and call the heavyweights to help us out. 798 * and call the heavyweights to help us out.
@@ -824,9 +822,9 @@ ex_handler_done:
824 andi r5, r5, (MICROBLAZE_TLB_SIZE-1) 822 andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
825 ori r6, r0, 1 823 ori r6, r0, 1
826 cmp r31, r5, r6 824 cmp r31, r5, r6
827 blti r31, sem 825 blti r31, ex12
828 addik r5, r6, 1 826 addik r5, r6, 1
829 sem: 827 ex12:
830 /* MS: save back current TLB index */ 828 /* MS: save back current TLB index */
831 swi r5, r0, TOPHYS(tlb_index) 829 swi r5, r0, TOPHYS(tlb_index)
832 830
@@ -846,7 +844,6 @@ ex_handler_done:
846 nop 844 nop
847 845
848 /* Done...restore registers and get out of here. */ 846 /* Done...restore registers and get out of here. */
849 ex12:
850 mts rpid, r11 847 mts rpid, r11
851 nop 848 nop
852 bri 4 849 bri 4