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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-22 13:23:46 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-22 13:23:46 -0400
commit74511020dde10252f8b8e648690d99dba721de14 (patch)
tree04fc22bc7dd5d5b8d9294b2e57985b093858bd84 /arch/microblaze/pci
parent69266866a5790080d7fe80094b28d670ff8aa765 (diff)
parent3cc4e53f86dab635166929bfa47cc68d59b28c26 (diff)
Merge branch 'for-2.6.34' into for-2.6.35
Diffstat (limited to 'arch/microblaze/pci')
-rw-r--r--arch/microblaze/pci/Makefile6
-rw-r--r--arch/microblaze/pci/indirect_pci.c163
-rw-r--r--arch/microblaze/pci/iomap.c39
-rw-r--r--arch/microblaze/pci/pci-common.c1642
-rw-r--r--arch/microblaze/pci/pci_32.c430
-rw-r--r--arch/microblaze/pci/xilinx_pci.c168
6 files changed, 2448 insertions, 0 deletions
diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile
new file mode 100644
index 000000000000..9889cc2e1294
--- /dev/null
+++ b/arch/microblaze/pci/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile
3#
4
5obj-$(CONFIG_PCI) += pci_32.o pci-common.o indirect_pci.o iomap.o
6obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o
diff --git a/arch/microblaze/pci/indirect_pci.c b/arch/microblaze/pci/indirect_pci.c
new file mode 100644
index 000000000000..25f18f017f21
--- /dev/null
+++ b/arch/microblaze/pci/indirect_pci.c
@@ -0,0 +1,163 @@
1/*
2 * Support for indirect PCI bridges.
3 *
4 * Copyright (C) 1998 Gabriel Paubert.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/delay.h>
15#include <linux/string.h>
16#include <linux/init.h>
17
18#include <asm/io.h>
19#include <asm/prom.h>
20#include <asm/pci-bridge.h>
21
22static int
23indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
24 int len, u32 *val)
25{
26 struct pci_controller *hose = pci_bus_to_host(bus);
27 volatile void __iomem *cfg_data;
28 u8 cfg_type = 0;
29 u32 bus_no, reg;
30
31 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
32 if (bus->number != hose->first_busno)
33 return PCIBIOS_DEVICE_NOT_FOUND;
34 if (devfn != 0)
35 return PCIBIOS_DEVICE_NOT_FOUND;
36 }
37
38 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
39 if (bus->number != hose->first_busno)
40 cfg_type = 1;
41
42 bus_no = (bus->number == hose->first_busno) ?
43 hose->self_busno : bus->number;
44
45 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
46 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
47 else
48 reg = offset & 0xfc; /* Only 3 bits for function */
49
50 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
51 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
52 (devfn << 8) | reg | cfg_type));
53 else
54 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
55 (devfn << 8) | reg | cfg_type));
56
57 /*
58 * Note: the caller has already checked that offset is
59 * suitably aligned and that len is 1, 2 or 4.
60 */
61 cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */
62 switch (len) {
63 case 1:
64 *val = in_8(cfg_data);
65 break;
66 case 2:
67 *val = in_le16(cfg_data);
68 break;
69 default:
70 *val = in_le32(cfg_data);
71 break;
72 }
73 return PCIBIOS_SUCCESSFUL;
74}
75
76static int
77indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
78 int len, u32 val)
79{
80 struct pci_controller *hose = pci_bus_to_host(bus);
81 volatile void __iomem *cfg_data;
82 u8 cfg_type = 0;
83 u32 bus_no, reg;
84
85 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
86 if (bus->number != hose->first_busno)
87 return PCIBIOS_DEVICE_NOT_FOUND;
88 if (devfn != 0)
89 return PCIBIOS_DEVICE_NOT_FOUND;
90 }
91
92 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
93 if (bus->number != hose->first_busno)
94 cfg_type = 1;
95
96 bus_no = (bus->number == hose->first_busno) ?
97 hose->self_busno : bus->number;
98
99 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
100 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
101 else
102 reg = offset & 0xfc;
103
104 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
105 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
106 (devfn << 8) | reg | cfg_type));
107 else
108 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
109 (devfn << 8) | reg | cfg_type));
110
111 /* surpress setting of PCI_PRIMARY_BUS */
112 if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
113 if ((offset == PCI_PRIMARY_BUS) &&
114 (bus->number == hose->first_busno))
115 val &= 0xffffff00;
116
117 /* Workaround for PCI_28 Errata in 440EPx/GRx */
118 if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&
119 offset == PCI_CACHE_LINE_SIZE) {
120 val = 0;
121 }
122
123 /*
124 * Note: the caller has already checked that offset is
125 * suitably aligned and that len is 1, 2 or 4.
126 */
127 cfg_data = hose->cfg_data + (offset & 3);
128 switch (len) {
129 case 1:
130 out_8(cfg_data, val);
131 break;
132 case 2:
133 out_le16(cfg_data, val);
134 break;
135 default:
136 out_le32(cfg_data, val);
137 break;
138 }
139
140 return PCIBIOS_SUCCESSFUL;
141}
142
143static struct pci_ops indirect_pci_ops = {
144 .read = indirect_read_config,
145 .write = indirect_write_config,
146};
147
148void __init
149setup_indirect_pci(struct pci_controller *hose,
150 resource_size_t cfg_addr,
151 resource_size_t cfg_data, u32 flags)
152{
153 resource_size_t base = cfg_addr & PAGE_MASK;
154 void __iomem *mbase;
155
156 mbase = ioremap(base, PAGE_SIZE);
157 hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
158 if ((cfg_data & PAGE_MASK) != base)
159 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
160 hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
161 hose->ops = &indirect_pci_ops;
162 hose->indirect_type = flags;
163}
diff --git a/arch/microblaze/pci/iomap.c b/arch/microblaze/pci/iomap.c
new file mode 100644
index 000000000000..3fbf16f4e16c
--- /dev/null
+++ b/arch/microblaze/pci/iomap.c
@@ -0,0 +1,39 @@
1/*
2 * ppc64 "iomap" interface implementation.
3 *
4 * (C) Copyright 2004 Linus Torvalds
5 */
6#include <linux/init.h>
7#include <linux/pci.h>
8#include <linux/mm.h>
9#include <asm/io.h>
10#include <asm/pci-bridge.h>
11
12void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
13{
14 resource_size_t start = pci_resource_start(dev, bar);
15 resource_size_t len = pci_resource_len(dev, bar);
16 unsigned long flags = pci_resource_flags(dev, bar);
17
18 if (!len)
19 return NULL;
20 if (max && len > max)
21 len = max;
22 if (flags & IORESOURCE_IO)
23 return ioport_map(start, len);
24 if (flags & IORESOURCE_MEM)
25 return ioremap(start, len);
26 /* What? */
27 return NULL;
28}
29EXPORT_SYMBOL(pci_iomap);
30
31void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
32{
33 if (isa_vaddr_is_ioport(addr))
34 return;
35 if (pcibios_vaddr_is_ioport(addr))
36 return;
37 iounmap(addr);
38}
39EXPORT_SYMBOL(pci_iounmap);
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
new file mode 100644
index 000000000000..0be34350d733
--- /dev/null
+++ b/arch/microblaze/pci/pci-common.c
@@ -0,0 +1,1642 @@
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29
30#include <asm/processor.h>
31#include <asm/io.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/byteorder.h>
35
36static DEFINE_SPINLOCK(hose_spinlock);
37LIST_HEAD(hose_list);
38
39/* XXX kill that some day ... */
40static int global_phb_number; /* Global phb counter */
41
42/* ISA Memory physical address */
43resource_size_t isa_mem_base;
44
45/* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
46unsigned int pci_flags;
47
48static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
49
50void set_pci_dma_ops(struct dma_map_ops *dma_ops)
51{
52 pci_dma_ops = dma_ops;
53}
54
55struct dma_map_ops *get_pci_dma_ops(void)
56{
57 return pci_dma_ops;
58}
59EXPORT_SYMBOL(get_pci_dma_ops);
60
61int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
62{
63 return dma_set_mask(&dev->dev, mask);
64}
65
66int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
67{
68 int rc;
69
70 rc = dma_set_mask(&dev->dev, mask);
71 dev->dev.coherent_dma_mask = dev->dma_mask;
72
73 return rc;
74}
75
76struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
77{
78 struct pci_controller *phb;
79
80 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
81 if (!phb)
82 return NULL;
83 spin_lock(&hose_spinlock);
84 phb->global_number = global_phb_number++;
85 list_add_tail(&phb->list_node, &hose_list);
86 spin_unlock(&hose_spinlock);
87 phb->dn = dev;
88 phb->is_dynamic = mem_init_done;
89 return phb;
90}
91
92void pcibios_free_controller(struct pci_controller *phb)
93{
94 spin_lock(&hose_spinlock);
95 list_del(&phb->list_node);
96 spin_unlock(&hose_spinlock);
97
98 if (phb->is_dynamic)
99 kfree(phb);
100}
101
102static resource_size_t pcibios_io_size(const struct pci_controller *hose)
103{
104 return hose->io_resource.end - hose->io_resource.start + 1;
105}
106
107int pcibios_vaddr_is_ioport(void __iomem *address)
108{
109 int ret = 0;
110 struct pci_controller *hose;
111 resource_size_t size;
112
113 spin_lock(&hose_spinlock);
114 list_for_each_entry(hose, &hose_list, list_node) {
115 size = pcibios_io_size(hose);
116 if (address >= hose->io_base_virt &&
117 address < (hose->io_base_virt + size)) {
118 ret = 1;
119 break;
120 }
121 }
122 spin_unlock(&hose_spinlock);
123 return ret;
124}
125
126unsigned long pci_address_to_pio(phys_addr_t address)
127{
128 struct pci_controller *hose;
129 resource_size_t size;
130 unsigned long ret = ~0;
131
132 spin_lock(&hose_spinlock);
133 list_for_each_entry(hose, &hose_list, list_node) {
134 size = pcibios_io_size(hose);
135 if (address >= hose->io_base_phys &&
136 address < (hose->io_base_phys + size)) {
137 unsigned long base =
138 (unsigned long)hose->io_base_virt - _IO_BASE;
139 ret = base + (address - hose->io_base_phys);
140 break;
141 }
142 }
143 spin_unlock(&hose_spinlock);
144
145 return ret;
146}
147EXPORT_SYMBOL_GPL(pci_address_to_pio);
148
149/*
150 * Return the domain number for this bus.
151 */
152int pci_domain_nr(struct pci_bus *bus)
153{
154 struct pci_controller *hose = pci_bus_to_host(bus);
155
156 return hose->global_number;
157}
158EXPORT_SYMBOL(pci_domain_nr);
159
160/* This routine is meant to be used early during boot, when the
161 * PCI bus numbers have not yet been assigned, and you need to
162 * issue PCI config cycles to an OF device.
163 * It could also be used to "fix" RTAS config cycles if you want
164 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
165 * config cycles.
166 */
167struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
168{
169 while (node) {
170 struct pci_controller *hose, *tmp;
171 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
172 if (hose->dn == node)
173 return hose;
174 node = node->parent;
175 }
176 return NULL;
177}
178
179static ssize_t pci_show_devspec(struct device *dev,
180 struct device_attribute *attr, char *buf)
181{
182 struct pci_dev *pdev;
183 struct device_node *np;
184
185 pdev = to_pci_dev(dev);
186 np = pci_device_to_OF_node(pdev);
187 if (np == NULL || np->full_name == NULL)
188 return 0;
189 return sprintf(buf, "%s", np->full_name);
190}
191static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
192
193/* Add sysfs properties */
194int pcibios_add_platform_entries(struct pci_dev *pdev)
195{
196 return device_create_file(&pdev->dev, &dev_attr_devspec);
197}
198
199char __devinit *pcibios_setup(char *str)
200{
201 return str;
202}
203
204/*
205 * Reads the interrupt pin to determine if interrupt is use by card.
206 * If the interrupt is used, then gets the interrupt line from the
207 * openfirmware and sets it in the pci_dev and pci_config line.
208 */
209int pci_read_irq_line(struct pci_dev *pci_dev)
210{
211 struct of_irq oirq;
212 unsigned int virq;
213
214 /* The current device-tree that iSeries generates from the HV
215 * PCI informations doesn't contain proper interrupt routing,
216 * and all the fallback would do is print out crap, so we
217 * don't attempt to resolve the interrupts here at all, some
218 * iSeries specific fixup does it.
219 *
220 * In the long run, we will hopefully fix the generated device-tree
221 * instead.
222 */
223 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
224
225#ifdef DEBUG
226 memset(&oirq, 0xff, sizeof(oirq));
227#endif
228 /* Try to get a mapping from the device-tree */
229 if (of_irq_map_pci(pci_dev, &oirq)) {
230 u8 line, pin;
231
232 /* If that fails, lets fallback to what is in the config
233 * space and map that through the default controller. We
234 * also set the type to level low since that's what PCI
235 * interrupts are. If your platform does differently, then
236 * either provide a proper interrupt tree or don't use this
237 * function.
238 */
239 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
240 return -1;
241 if (pin == 0)
242 return -1;
243 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
244 line == 0xff || line == 0) {
245 return -1;
246 }
247 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
248 line, pin);
249
250 virq = irq_create_mapping(NULL, line);
251 if (virq != NO_IRQ)
252 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
253 } else {
254 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
255 oirq.size, oirq.specifier[0], oirq.specifier[1],
256 oirq.controller ? oirq.controller->full_name :
257 "<default>");
258
259 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
260 oirq.size);
261 }
262 if (virq == NO_IRQ) {
263 pr_debug(" Failed to map !\n");
264 return -1;
265 }
266
267 pr_debug(" Mapped to linux irq %d\n", virq);
268
269 pci_dev->irq = virq;
270
271 return 0;
272}
273EXPORT_SYMBOL(pci_read_irq_line);
274
275/*
276 * Platform support for /proc/bus/pci/X/Y mmap()s,
277 * modelled on the sparc64 implementation by Dave Miller.
278 * -- paulus.
279 */
280
281/*
282 * Adjust vm_pgoff of VMA such that it is the physical page offset
283 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
284 *
285 * Basically, the user finds the base address for his device which he wishes
286 * to mmap. They read the 32-bit value from the config space base register,
287 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
288 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
289 *
290 * Returns negative error code on failure, zero on success.
291 */
292static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
293 resource_size_t *offset,
294 enum pci_mmap_state mmap_state)
295{
296 struct pci_controller *hose = pci_bus_to_host(dev->bus);
297 unsigned long io_offset = 0;
298 int i, res_bit;
299
300 if (hose == 0)
301 return NULL; /* should never happen */
302
303 /* If memory, add on the PCI bridge address offset */
304 if (mmap_state == pci_mmap_mem) {
305#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
306 *offset += hose->pci_mem_offset;
307#endif
308 res_bit = IORESOURCE_MEM;
309 } else {
310 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
311 *offset += io_offset;
312 res_bit = IORESOURCE_IO;
313 }
314
315 /*
316 * Check that the offset requested corresponds to one of the
317 * resources of the device.
318 */
319 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
320 struct resource *rp = &dev->resource[i];
321 int flags = rp->flags;
322
323 /* treat ROM as memory (should be already) */
324 if (i == PCI_ROM_RESOURCE)
325 flags |= IORESOURCE_MEM;
326
327 /* Active and same type? */
328 if ((flags & res_bit) == 0)
329 continue;
330
331 /* In the range of this resource? */
332 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
333 continue;
334
335 /* found it! construct the final physical address */
336 if (mmap_state == pci_mmap_io)
337 *offset += hose->io_base_phys - io_offset;
338 return rp;
339 }
340
341 return NULL;
342}
343
344/*
345 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
346 * device mapping.
347 */
348static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
349 pgprot_t protection,
350 enum pci_mmap_state mmap_state,
351 int write_combine)
352{
353 pgprot_t prot = protection;
354
355 /* Write combine is always 0 on non-memory space mappings. On
356 * memory space, if the user didn't pass 1, we check for a
357 * "prefetchable" resource. This is a bit hackish, but we use
358 * this to workaround the inability of /sysfs to provide a write
359 * combine bit
360 */
361 if (mmap_state != pci_mmap_mem)
362 write_combine = 0;
363 else if (write_combine == 0) {
364 if (rp->flags & IORESOURCE_PREFETCH)
365 write_combine = 1;
366 }
367
368 return pgprot_noncached(prot);
369}
370
371/*
372 * This one is used by /dev/mem and fbdev who have no clue about the
373 * PCI device, it tries to find the PCI device first and calls the
374 * above routine
375 */
376pgprot_t pci_phys_mem_access_prot(struct file *file,
377 unsigned long pfn,
378 unsigned long size,
379 pgprot_t prot)
380{
381 struct pci_dev *pdev = NULL;
382 struct resource *found = NULL;
383 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
384 int i;
385
386 if (page_is_ram(pfn))
387 return prot;
388
389 prot = pgprot_noncached(prot);
390 for_each_pci_dev(pdev) {
391 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
392 struct resource *rp = &pdev->resource[i];
393 int flags = rp->flags;
394
395 /* Active and same type? */
396 if ((flags & IORESOURCE_MEM) == 0)
397 continue;
398 /* In the range of this resource? */
399 if (offset < (rp->start & PAGE_MASK) ||
400 offset > rp->end)
401 continue;
402 found = rp;
403 break;
404 }
405 if (found)
406 break;
407 }
408 if (found) {
409 if (found->flags & IORESOURCE_PREFETCH)
410 prot = pgprot_noncached_wc(prot);
411 pci_dev_put(pdev);
412 }
413
414 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
415 (unsigned long long)offset, pgprot_val(prot));
416
417 return prot;
418}
419
420/*
421 * Perform the actual remap of the pages for a PCI device mapping, as
422 * appropriate for this architecture. The region in the process to map
423 * is described by vm_start and vm_end members of VMA, the base physical
424 * address is found in vm_pgoff.
425 * The pci device structure is provided so that architectures may make mapping
426 * decisions on a per-device or per-bus basis.
427 *
428 * Returns a negative error code on failure, zero on success.
429 */
430int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
431 enum pci_mmap_state mmap_state, int write_combine)
432{
433 resource_size_t offset =
434 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
435 struct resource *rp;
436 int ret;
437
438 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
439 if (rp == NULL)
440 return -EINVAL;
441
442 vma->vm_pgoff = offset >> PAGE_SHIFT;
443 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
444 vma->vm_page_prot,
445 mmap_state, write_combine);
446
447 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
448 vma->vm_end - vma->vm_start, vma->vm_page_prot);
449
450 return ret;
451}
452
453/* This provides legacy IO read access on a bus */
454int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
455{
456 unsigned long offset;
457 struct pci_controller *hose = pci_bus_to_host(bus);
458 struct resource *rp = &hose->io_resource;
459 void __iomem *addr;
460
461 /* Check if port can be supported by that bus. We only check
462 * the ranges of the PHB though, not the bus itself as the rules
463 * for forwarding legacy cycles down bridges are not our problem
464 * here. So if the host bridge supports it, we do it.
465 */
466 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
467 offset += port;
468
469 if (!(rp->flags & IORESOURCE_IO))
470 return -ENXIO;
471 if (offset < rp->start || (offset + size) > rp->end)
472 return -ENXIO;
473 addr = hose->io_base_virt + port;
474
475 switch (size) {
476 case 1:
477 *((u8 *)val) = in_8(addr);
478 return 1;
479 case 2:
480 if (port & 1)
481 return -EINVAL;
482 *((u16 *)val) = in_le16(addr);
483 return 2;
484 case 4:
485 if (port & 3)
486 return -EINVAL;
487 *((u32 *)val) = in_le32(addr);
488 return 4;
489 }
490 return -EINVAL;
491}
492
493/* This provides legacy IO write access on a bus */
494int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
495{
496 unsigned long offset;
497 struct pci_controller *hose = pci_bus_to_host(bus);
498 struct resource *rp = &hose->io_resource;
499 void __iomem *addr;
500
501 /* Check if port can be supported by that bus. We only check
502 * the ranges of the PHB though, not the bus itself as the rules
503 * for forwarding legacy cycles down bridges are not our problem
504 * here. So if the host bridge supports it, we do it.
505 */
506 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
507 offset += port;
508
509 if (!(rp->flags & IORESOURCE_IO))
510 return -ENXIO;
511 if (offset < rp->start || (offset + size) > rp->end)
512 return -ENXIO;
513 addr = hose->io_base_virt + port;
514
515 /* WARNING: The generic code is idiotic. It gets passed a pointer
516 * to what can be a 1, 2 or 4 byte quantity and always reads that
517 * as a u32, which means that we have to correct the location of
518 * the data read within those 32 bits for size 1 and 2
519 */
520 switch (size) {
521 case 1:
522 out_8(addr, val >> 24);
523 return 1;
524 case 2:
525 if (port & 1)
526 return -EINVAL;
527 out_le16(addr, val >> 16);
528 return 2;
529 case 4:
530 if (port & 3)
531 return -EINVAL;
532 out_le32(addr, val);
533 return 4;
534 }
535 return -EINVAL;
536}
537
538/* This provides legacy IO or memory mmap access on a bus */
539int pci_mmap_legacy_page_range(struct pci_bus *bus,
540 struct vm_area_struct *vma,
541 enum pci_mmap_state mmap_state)
542{
543 struct pci_controller *hose = pci_bus_to_host(bus);
544 resource_size_t offset =
545 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
546 resource_size_t size = vma->vm_end - vma->vm_start;
547 struct resource *rp;
548
549 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
550 pci_domain_nr(bus), bus->number,
551 mmap_state == pci_mmap_mem ? "MEM" : "IO",
552 (unsigned long long)offset,
553 (unsigned long long)(offset + size - 1));
554
555 if (mmap_state == pci_mmap_mem) {
556 /* Hack alert !
557 *
558 * Because X is lame and can fail starting if it gets an error
559 * trying to mmap legacy_mem (instead of just moving on without
560 * legacy memory access) we fake it here by giving it anonymous
561 * memory, effectively behaving just like /dev/zero
562 */
563 if ((offset + size) > hose->isa_mem_size) {
564#ifdef CONFIG_MMU
565 printk(KERN_DEBUG
566 "Process %s (pid:%d) mapped non-existing PCI"
567 "legacy memory for 0%04x:%02x\n",
568 current->comm, current->pid, pci_domain_nr(bus),
569 bus->number);
570#endif
571 if (vma->vm_flags & VM_SHARED)
572 return shmem_zero_setup(vma);
573 return 0;
574 }
575 offset += hose->isa_mem_phys;
576 } else {
577 unsigned long io_offset = (unsigned long)hose->io_base_virt - \
578 _IO_BASE;
579 unsigned long roffset = offset + io_offset;
580 rp = &hose->io_resource;
581 if (!(rp->flags & IORESOURCE_IO))
582 return -ENXIO;
583 if (roffset < rp->start || (roffset + size) > rp->end)
584 return -ENXIO;
585 offset += hose->io_base_phys;
586 }
587 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
588
589 vma->vm_pgoff = offset >> PAGE_SHIFT;
590 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
591 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
592 vma->vm_end - vma->vm_start,
593 vma->vm_page_prot);
594}
595
596void pci_resource_to_user(const struct pci_dev *dev, int bar,
597 const struct resource *rsrc,
598 resource_size_t *start, resource_size_t *end)
599{
600 struct pci_controller *hose = pci_bus_to_host(dev->bus);
601 resource_size_t offset = 0;
602
603 if (hose == NULL)
604 return;
605
606 if (rsrc->flags & IORESOURCE_IO)
607 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
608
609 /* We pass a fully fixed up address to userland for MMIO instead of
610 * a BAR value because X is lame and expects to be able to use that
611 * to pass to /dev/mem !
612 *
613 * That means that we'll have potentially 64 bits values where some
614 * userland apps only expect 32 (like X itself since it thinks only
615 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
616 * 32 bits CHRPs :-(
617 *
618 * Hopefully, the sysfs insterface is immune to that gunk. Once X
619 * has been fixed (and the fix spread enough), we can re-enable the
620 * 2 lines below and pass down a BAR value to userland. In that case
621 * we'll also have to re-enable the matching code in
622 * __pci_mmap_make_offset().
623 *
624 * BenH.
625 */
626#if 0
627 else if (rsrc->flags & IORESOURCE_MEM)
628 offset = hose->pci_mem_offset;
629#endif
630
631 *start = rsrc->start - offset;
632 *end = rsrc->end - offset;
633}
634
635/**
636 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
637 * @hose: newly allocated pci_controller to be setup
638 * @dev: device node of the host bridge
639 * @primary: set if primary bus (32 bits only, soon to be deprecated)
640 *
641 * This function will parse the "ranges" property of a PCI host bridge device
642 * node and setup the resource mapping of a pci controller based on its
643 * content.
644 *
645 * Life would be boring if it wasn't for a few issues that we have to deal
646 * with here:
647 *
648 * - We can only cope with one IO space range and up to 3 Memory space
649 * ranges. However, some machines (thanks Apple !) tend to split their
650 * space into lots of small contiguous ranges. So we have to coalesce.
651 *
652 * - We can only cope with all memory ranges having the same offset
653 * between CPU addresses and PCI addresses. Unfortunately, some bridges
654 * are setup for a large 1:1 mapping along with a small "window" which
655 * maps PCI address 0 to some arbitrary high address of the CPU space in
656 * order to give access to the ISA memory hole.
657 * The way out of here that I've chosen for now is to always set the
658 * offset based on the first resource found, then override it if we
659 * have a different offset and the previous was set by an ISA hole.
660 *
661 * - Some busses have IO space not starting at 0, which causes trouble with
662 * the way we do our IO resource renumbering. The code somewhat deals with
663 * it for 64 bits but I would expect problems on 32 bits.
664 *
665 * - Some 32 bits platforms such as 4xx can have physical space larger than
666 * 32 bits so we need to use 64 bits values for the parsing
667 */
668void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
669 struct device_node *dev,
670 int primary)
671{
672 const u32 *ranges;
673 int rlen;
674 int pna = of_n_addr_cells(dev);
675 int np = pna + 5;
676 int memno = 0, isa_hole = -1;
677 u32 pci_space;
678 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
679 unsigned long long isa_mb = 0;
680 struct resource *res;
681
682 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
683 dev->full_name, primary ? "(primary)" : "");
684
685 /* Get ranges property */
686 ranges = of_get_property(dev, "ranges", &rlen);
687 if (ranges == NULL)
688 return;
689
690 /* Parse it */
691 pr_debug("Parsing ranges property...\n");
692 while ((rlen -= np * 4) >= 0) {
693 /* Read next ranges element */
694 pci_space = ranges[0];
695 pci_addr = of_read_number(ranges + 1, 2);
696 cpu_addr = of_translate_address(dev, ranges + 3);
697 size = of_read_number(ranges + pna + 3, 2);
698
699 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
700 "cpu_addr:0x%016llx size:0x%016llx\n",
701 pci_space, pci_addr, cpu_addr, size);
702
703 ranges += np;
704
705 /* If we failed translation or got a zero-sized region
706 * (some FW try to feed us with non sensical zero sized regions
707 * such as power3 which look like some kind of attempt
708 * at exposing the VGA memory hole)
709 */
710 if (cpu_addr == OF_BAD_ADDR || size == 0)
711 continue;
712
713 /* Now consume following elements while they are contiguous */
714 for (; rlen >= np * sizeof(u32);
715 ranges += np, rlen -= np * 4) {
716 if (ranges[0] != pci_space)
717 break;
718 pci_next = of_read_number(ranges + 1, 2);
719 cpu_next = of_translate_address(dev, ranges + 3);
720 if (pci_next != pci_addr + size ||
721 cpu_next != cpu_addr + size)
722 break;
723 size += of_read_number(ranges + pna + 3, 2);
724 }
725
726 /* Act based on address space type */
727 res = NULL;
728 switch ((pci_space >> 24) & 0x3) {
729 case 1: /* PCI IO space */
730 printk(KERN_INFO
731 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
732 cpu_addr, cpu_addr + size - 1, pci_addr);
733
734 /* We support only one IO range */
735 if (hose->pci_io_size) {
736 printk(KERN_INFO
737 " \\--> Skipped (too many) !\n");
738 continue;
739 }
740 /* On 32 bits, limit I/O space to 16MB */
741 if (size > 0x01000000)
742 size = 0x01000000;
743
744 /* 32 bits needs to map IOs here */
745 hose->io_base_virt = ioremap(cpu_addr, size);
746
747 /* Expect trouble if pci_addr is not 0 */
748 if (primary)
749 isa_io_base =
750 (unsigned long)hose->io_base_virt;
751 /* pci_io_size and io_base_phys always represent IO
752 * space starting at 0 so we factor in pci_addr
753 */
754 hose->pci_io_size = pci_addr + size;
755 hose->io_base_phys = cpu_addr - pci_addr;
756
757 /* Build resource */
758 res = &hose->io_resource;
759 res->flags = IORESOURCE_IO;
760 res->start = pci_addr;
761 break;
762 case 2: /* PCI Memory space */
763 case 3: /* PCI 64 bits Memory space */
764 printk(KERN_INFO
765 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
766 cpu_addr, cpu_addr + size - 1, pci_addr,
767 (pci_space & 0x40000000) ? "Prefetch" : "");
768
769 /* We support only 3 memory ranges */
770 if (memno >= 3) {
771 printk(KERN_INFO
772 " \\--> Skipped (too many) !\n");
773 continue;
774 }
775 /* Handles ISA memory hole space here */
776 if (pci_addr == 0) {
777 isa_mb = cpu_addr;
778 isa_hole = memno;
779 if (primary || isa_mem_base == 0)
780 isa_mem_base = cpu_addr;
781 hose->isa_mem_phys = cpu_addr;
782 hose->isa_mem_size = size;
783 }
784
785 /* We get the PCI/Mem offset from the first range or
786 * the, current one if the offset came from an ISA
787 * hole. If they don't match, bugger.
788 */
789 if (memno == 0 ||
790 (isa_hole >= 0 && pci_addr != 0 &&
791 hose->pci_mem_offset == isa_mb))
792 hose->pci_mem_offset = cpu_addr - pci_addr;
793 else if (pci_addr != 0 &&
794 hose->pci_mem_offset != cpu_addr - pci_addr) {
795 printk(KERN_INFO
796 " \\--> Skipped (offset mismatch) !\n");
797 continue;
798 }
799
800 /* Build resource */
801 res = &hose->mem_resources[memno++];
802 res->flags = IORESOURCE_MEM;
803 if (pci_space & 0x40000000)
804 res->flags |= IORESOURCE_PREFETCH;
805 res->start = cpu_addr;
806 break;
807 }
808 if (res != NULL) {
809 res->name = dev->full_name;
810 res->end = res->start + size - 1;
811 res->parent = NULL;
812 res->sibling = NULL;
813 res->child = NULL;
814 }
815 }
816
817 /* If there's an ISA hole and the pci_mem_offset is -not- matching
818 * the ISA hole offset, then we need to remove the ISA hole from
819 * the resource list for that brige
820 */
821 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
822 unsigned int next = isa_hole + 1;
823 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
824 if (next < memno)
825 memmove(&hose->mem_resources[isa_hole],
826 &hose->mem_resources[next],
827 sizeof(struct resource) * (memno - next));
828 hose->mem_resources[--memno].flags = 0;
829 }
830}
831
832/* Decide whether to display the domain number in /proc */
833int pci_proc_domain(struct pci_bus *bus)
834{
835 struct pci_controller *hose = pci_bus_to_host(bus);
836
837 if (!(pci_flags & PCI_ENABLE_PROC_DOMAINS))
838 return 0;
839 if (pci_flags & PCI_COMPAT_DOMAIN_0)
840 return hose->global_number != 0;
841 return 1;
842}
843
844void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
845 struct resource *res)
846{
847 resource_size_t offset = 0, mask = (resource_size_t)-1;
848 struct pci_controller *hose = pci_bus_to_host(dev->bus);
849
850 if (!hose)
851 return;
852 if (res->flags & IORESOURCE_IO) {
853 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
854 mask = 0xffffffffu;
855 } else if (res->flags & IORESOURCE_MEM)
856 offset = hose->pci_mem_offset;
857
858 region->start = (res->start - offset) & mask;
859 region->end = (res->end - offset) & mask;
860}
861EXPORT_SYMBOL(pcibios_resource_to_bus);
862
863void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
864 struct pci_bus_region *region)
865{
866 resource_size_t offset = 0, mask = (resource_size_t)-1;
867 struct pci_controller *hose = pci_bus_to_host(dev->bus);
868
869 if (!hose)
870 return;
871 if (res->flags & IORESOURCE_IO) {
872 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
873 mask = 0xffffffffu;
874 } else if (res->flags & IORESOURCE_MEM)
875 offset = hose->pci_mem_offset;
876 res->start = (region->start + offset) & mask;
877 res->end = (region->end + offset) & mask;
878}
879EXPORT_SYMBOL(pcibios_bus_to_resource);
880
881/* Fixup a bus resource into a linux resource */
882static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
883{
884 struct pci_controller *hose = pci_bus_to_host(dev->bus);
885 resource_size_t offset = 0, mask = (resource_size_t)-1;
886
887 if (res->flags & IORESOURCE_IO) {
888 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
889 mask = 0xffffffffu;
890 } else if (res->flags & IORESOURCE_MEM)
891 offset = hose->pci_mem_offset;
892
893 res->start = (res->start + offset) & mask;
894 res->end = (res->end + offset) & mask;
895}
896
897/* This header fixup will do the resource fixup for all devices as they are
898 * probed, but not for bridge ranges
899 */
900static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
901{
902 struct pci_controller *hose = pci_bus_to_host(dev->bus);
903 int i;
904
905 if (!hose) {
906 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
907 pci_name(dev));
908 return;
909 }
910 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
911 struct resource *res = dev->resource + i;
912 if (!res->flags)
913 continue;
914 /* On platforms that have PCI_PROBE_ONLY set, we don't
915 * consider 0 as an unassigned BAR value. It's technically
916 * a valid value, but linux doesn't like it... so when we can
917 * re-assign things, we do so, but if we can't, we keep it
918 * around and hope for the best...
919 */
920 if (res->start == 0 && !(pci_flags & PCI_PROBE_ONLY)) {
921 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
922 "is unassigned\n",
923 pci_name(dev), i,
924 (unsigned long long)res->start,
925 (unsigned long long)res->end,
926 (unsigned int)res->flags);
927 res->end -= res->start;
928 res->start = 0;
929 res->flags |= IORESOURCE_UNSET;
930 continue;
931 }
932
933 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
934 pci_name(dev), i,
935 (unsigned long long)res->start,\
936 (unsigned long long)res->end,
937 (unsigned int)res->flags);
938
939 fixup_resource(res, dev);
940
941 pr_debug("PCI:%s %016llx-%016llx\n",
942 pci_name(dev),
943 (unsigned long long)res->start,
944 (unsigned long long)res->end);
945 }
946}
947DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
948
949/* This function tries to figure out if a bridge resource has been initialized
950 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
951 * things go more smoothly when it gets it right. It should covers cases such
952 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
953 */
954static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
955 struct resource *res)
956{
957 struct pci_controller *hose = pci_bus_to_host(bus);
958 struct pci_dev *dev = bus->self;
959 resource_size_t offset;
960 u16 command;
961 int i;
962
963 /* We don't do anything if PCI_PROBE_ONLY is set */
964 if (pci_flags & PCI_PROBE_ONLY)
965 return 0;
966
967 /* Job is a bit different between memory and IO */
968 if (res->flags & IORESOURCE_MEM) {
969 /* If the BAR is non-0 (res != pci_mem_offset) then it's
970 * probably been initialized by somebody
971 */
972 if (res->start != hose->pci_mem_offset)
973 return 0;
974
975 /* The BAR is 0, let's check if memory decoding is enabled on
976 * the bridge. If not, we consider it unassigned
977 */
978 pci_read_config_word(dev, PCI_COMMAND, &command);
979 if ((command & PCI_COMMAND_MEMORY) == 0)
980 return 1;
981
982 /* Memory decoding is enabled and the BAR is 0. If any of
983 * the bridge resources covers that starting address (0 then
984 * it's good enough for us for memory
985 */
986 for (i = 0; i < 3; i++) {
987 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
988 hose->mem_resources[i].start == hose->pci_mem_offset)
989 return 0;
990 }
991
992 /* Well, it starts at 0 and we know it will collide so we may as
993 * well consider it as unassigned. That covers the Apple case.
994 */
995 return 1;
996 } else {
997 /* If the BAR is non-0, then we consider it assigned */
998 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
999 if (((res->start - offset) & 0xfffffffful) != 0)
1000 return 0;
1001
1002 /* Here, we are a bit different than memory as typically IO
1003 * space starting at low addresses -is- valid. What we do
1004 * instead if that we consider as unassigned anything that
1005 * doesn't have IO enabled in the PCI command register,
1006 * and that's it.
1007 */
1008 pci_read_config_word(dev, PCI_COMMAND, &command);
1009 if (command & PCI_COMMAND_IO)
1010 return 0;
1011
1012 /* It's starting at 0 and IO is disabled in the bridge, consider
1013 * it unassigned
1014 */
1015 return 1;
1016 }
1017}
1018
1019/* Fixup resources of a PCI<->PCI bridge */
1020static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1021{
1022 struct resource *res;
1023 int i;
1024
1025 struct pci_dev *dev = bus->self;
1026
1027 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1028 res = bus->resource[i];
1029 if (!res)
1030 continue;
1031 if (!res->flags)
1032 continue;
1033 if (i >= 3 && bus->self->transparent)
1034 continue;
1035
1036 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1037 pci_name(dev), i,
1038 (unsigned long long)res->start,\
1039 (unsigned long long)res->end,
1040 (unsigned int)res->flags);
1041
1042 /* Perform fixup */
1043 fixup_resource(res, dev);
1044
1045 /* Try to detect uninitialized P2P bridge resources,
1046 * and clear them out so they get re-assigned later
1047 */
1048 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1049 res->flags = 0;
1050 pr_debug("PCI:%s (unassigned)\n",
1051 pci_name(dev));
1052 } else {
1053 pr_debug("PCI:%s %016llx-%016llx\n",
1054 pci_name(dev),
1055 (unsigned long long)res->start,
1056 (unsigned long long)res->end);
1057 }
1058 }
1059}
1060
1061void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1062{
1063 /* Fix up the bus resources for P2P bridges */
1064 if (bus->self != NULL)
1065 pcibios_fixup_bridge(bus);
1066}
1067
1068void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1069{
1070 struct pci_dev *dev;
1071
1072 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1073 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1074
1075 list_for_each_entry(dev, &bus->devices, bus_list) {
1076 struct dev_archdata *sd = &dev->dev.archdata;
1077
1078 /* Setup OF node pointer in archdata */
1079 sd->of_node = pci_device_to_OF_node(dev);
1080
1081 /* Fixup NUMA node as it may not be setup yet by the generic
1082 * code and is needed by the DMA init
1083 */
1084 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1085
1086 /* Hook up default DMA ops */
1087 sd->dma_ops = pci_dma_ops;
1088 sd->dma_data = (void *)PCI_DRAM_OFFSET;
1089
1090 /* Read default IRQs and fixup if necessary */
1091 pci_read_irq_line(dev);
1092 }
1093}
1094
1095void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1096{
1097 /* When called from the generic PCI probe, read PCI<->PCI bridge
1098 * bases. This is -not- called when generating the PCI tree from
1099 * the OF device-tree.
1100 */
1101 if (bus->self != NULL)
1102 pci_read_bridge_bases(bus);
1103
1104 /* Now fixup the bus bus */
1105 pcibios_setup_bus_self(bus);
1106
1107 /* Now fixup devices on that bus */
1108 pcibios_setup_bus_devices(bus);
1109}
1110EXPORT_SYMBOL(pcibios_fixup_bus);
1111
1112static int skip_isa_ioresource_align(struct pci_dev *dev)
1113{
1114 if ((pci_flags & PCI_CAN_SKIP_ISA_ALIGN) &&
1115 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1116 return 1;
1117 return 0;
1118}
1119
1120/*
1121 * We need to avoid collisions with `mirrored' VGA ports
1122 * and other strange ISA hardware, so we always want the
1123 * addresses to be allocated in the 0x000-0x0ff region
1124 * modulo 0x400.
1125 *
1126 * Why? Because some silly external IO cards only decode
1127 * the low 10 bits of the IO address. The 0x00-0xff region
1128 * is reserved for motherboard devices that decode all 16
1129 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1130 * but we want to try to avoid allocating at 0x2900-0x2bff
1131 * which might have be mirrored at 0x0100-0x03ff..
1132 */
1133void pcibios_align_resource(void *data, struct resource *res,
1134 resource_size_t size, resource_size_t align)
1135{
1136 struct pci_dev *dev = data;
1137
1138 if (res->flags & IORESOURCE_IO) {
1139 resource_size_t start = res->start;
1140
1141 if (skip_isa_ioresource_align(dev))
1142 return;
1143 if (start & 0x300) {
1144 start = (start + 0x3ff) & ~0x3ff;
1145 res->start = start;
1146 }
1147 }
1148}
1149EXPORT_SYMBOL(pcibios_align_resource);
1150
1151/*
1152 * Reparent resource children of pr that conflict with res
1153 * under res, and make res replace those children.
1154 */
1155static int __init reparent_resources(struct resource *parent,
1156 struct resource *res)
1157{
1158 struct resource *p, **pp;
1159 struct resource **firstpp = NULL;
1160
1161 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1162 if (p->end < res->start)
1163 continue;
1164 if (res->end < p->start)
1165 break;
1166 if (p->start < res->start || p->end > res->end)
1167 return -1; /* not completely contained */
1168 if (firstpp == NULL)
1169 firstpp = pp;
1170 }
1171 if (firstpp == NULL)
1172 return -1; /* didn't find any conflicting entries? */
1173 res->parent = parent;
1174 res->child = *firstpp;
1175 res->sibling = *pp;
1176 *firstpp = res;
1177 *pp = NULL;
1178 for (p = res->child; p != NULL; p = p->sibling) {
1179 p->parent = res;
1180 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1181 p->name,
1182 (unsigned long long)p->start,
1183 (unsigned long long)p->end, res->name);
1184 }
1185 return 0;
1186}
1187
1188/*
1189 * Handle resources of PCI devices. If the world were perfect, we could
1190 * just allocate all the resource regions and do nothing more. It isn't.
1191 * On the other hand, we cannot just re-allocate all devices, as it would
1192 * require us to know lots of host bridge internals. So we attempt to
1193 * keep as much of the original configuration as possible, but tweak it
1194 * when it's found to be wrong.
1195 *
1196 * Known BIOS problems we have to work around:
1197 * - I/O or memory regions not configured
1198 * - regions configured, but not enabled in the command register
1199 * - bogus I/O addresses above 64K used
1200 * - expansion ROMs left enabled (this may sound harmless, but given
1201 * the fact the PCI specs explicitly allow address decoders to be
1202 * shared between expansion ROMs and other resource regions, it's
1203 * at least dangerous)
1204 *
1205 * Our solution:
1206 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1207 * This gives us fixed barriers on where we can allocate.
1208 * (2) Allocate resources for all enabled devices. If there is
1209 * a collision, just mark the resource as unallocated. Also
1210 * disable expansion ROMs during this step.
1211 * (3) Try to allocate resources for disabled devices. If the
1212 * resources were assigned correctly, everything goes well,
1213 * if they weren't, they won't disturb allocation of other
1214 * resources.
1215 * (4) Assign new addresses to resources which were either
1216 * not configured at all or misconfigured. If explicitly
1217 * requested by the user, configure expansion ROM address
1218 * as well.
1219 */
1220
1221void pcibios_allocate_bus_resources(struct pci_bus *bus)
1222{
1223 struct pci_bus *b;
1224 int i;
1225 struct resource *res, *pr;
1226
1227 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1228 pci_domain_nr(bus), bus->number);
1229
1230 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1231 res = bus->resource[i];
1232 if (!res || !res->flags
1233 || res->start > res->end || res->parent)
1234 continue;
1235 if (bus->parent == NULL)
1236 pr = (res->flags & IORESOURCE_IO) ?
1237 &ioport_resource : &iomem_resource;
1238 else {
1239 /* Don't bother with non-root busses when
1240 * re-assigning all resources. We clear the
1241 * resource flags as if they were colliding
1242 * and as such ensure proper re-allocation
1243 * later.
1244 */
1245 if (pci_flags & PCI_REASSIGN_ALL_RSRC)
1246 goto clear_resource;
1247 pr = pci_find_parent_resource(bus->self, res);
1248 if (pr == res) {
1249 /* this happens when the generic PCI
1250 * code (wrongly) decides that this
1251 * bridge is transparent -- paulus
1252 */
1253 continue;
1254 }
1255 }
1256
1257 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1258 "[0x%x], parent %p (%s)\n",
1259 bus->self ? pci_name(bus->self) : "PHB",
1260 bus->number, i,
1261 (unsigned long long)res->start,
1262 (unsigned long long)res->end,
1263 (unsigned int)res->flags,
1264 pr, (pr && pr->name) ? pr->name : "nil");
1265
1266 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1267 if (request_resource(pr, res) == 0)
1268 continue;
1269 /*
1270 * Must be a conflict with an existing entry.
1271 * Move that entry (or entries) under the
1272 * bridge resource and try again.
1273 */
1274 if (reparent_resources(pr, res) == 0)
1275 continue;
1276 }
1277 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1278 "%d of PCI bridge %d, will remap\n", i, bus->number);
1279clear_resource:
1280 res->flags = 0;
1281 }
1282
1283 list_for_each_entry(b, &bus->children, node)
1284 pcibios_allocate_bus_resources(b);
1285}
1286
1287static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1288{
1289 struct resource *pr, *r = &dev->resource[idx];
1290
1291 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1292 pci_name(dev), idx,
1293 (unsigned long long)r->start,
1294 (unsigned long long)r->end,
1295 (unsigned int)r->flags);
1296
1297 pr = pci_find_parent_resource(dev, r);
1298 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1299 request_resource(pr, r) < 0) {
1300 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1301 " of device %s, will remap\n", idx, pci_name(dev));
1302 if (pr)
1303 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1304 pr,
1305 (unsigned long long)pr->start,
1306 (unsigned long long)pr->end,
1307 (unsigned int)pr->flags);
1308 /* We'll assign a new address later */
1309 r->flags |= IORESOURCE_UNSET;
1310 r->end -= r->start;
1311 r->start = 0;
1312 }
1313}
1314
1315static void __init pcibios_allocate_resources(int pass)
1316{
1317 struct pci_dev *dev = NULL;
1318 int idx, disabled;
1319 u16 command;
1320 struct resource *r;
1321
1322 for_each_pci_dev(dev) {
1323 pci_read_config_word(dev, PCI_COMMAND, &command);
1324 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1325 r = &dev->resource[idx];
1326 if (r->parent) /* Already allocated */
1327 continue;
1328 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1329 continue; /* Not assigned at all */
1330 /* We only allocate ROMs on pass 1 just in case they
1331 * have been screwed up by firmware
1332 */
1333 if (idx == PCI_ROM_RESOURCE)
1334 disabled = 1;
1335 if (r->flags & IORESOURCE_IO)
1336 disabled = !(command & PCI_COMMAND_IO);
1337 else
1338 disabled = !(command & PCI_COMMAND_MEMORY);
1339 if (pass == disabled)
1340 alloc_resource(dev, idx);
1341 }
1342 if (pass)
1343 continue;
1344 r = &dev->resource[PCI_ROM_RESOURCE];
1345 if (r->flags) {
1346 /* Turn the ROM off, leave the resource region,
1347 * but keep it unregistered.
1348 */
1349 u32 reg;
1350 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1351 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1352 pr_debug("PCI: Switching off ROM of %s\n",
1353 pci_name(dev));
1354 r->flags &= ~IORESOURCE_ROM_ENABLE;
1355 pci_write_config_dword(dev, dev->rom_base_reg,
1356 reg & ~PCI_ROM_ADDRESS_ENABLE);
1357 }
1358 }
1359 }
1360}
1361
1362static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1363{
1364 struct pci_controller *hose = pci_bus_to_host(bus);
1365 resource_size_t offset;
1366 struct resource *res, *pres;
1367 int i;
1368
1369 pr_debug("Reserving legacy ranges for domain %04x\n",
1370 pci_domain_nr(bus));
1371
1372 /* Check for IO */
1373 if (!(hose->io_resource.flags & IORESOURCE_IO))
1374 goto no_io;
1375 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1376 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1377 BUG_ON(res == NULL);
1378 res->name = "Legacy IO";
1379 res->flags = IORESOURCE_IO;
1380 res->start = offset;
1381 res->end = (offset + 0xfff) & 0xfffffffful;
1382 pr_debug("Candidate legacy IO: %pR\n", res);
1383 if (request_resource(&hose->io_resource, res)) {
1384 printk(KERN_DEBUG
1385 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1386 pci_domain_nr(bus), bus->number, res);
1387 kfree(res);
1388 }
1389
1390 no_io:
1391 /* Check for memory */
1392 offset = hose->pci_mem_offset;
1393 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1394 for (i = 0; i < 3; i++) {
1395 pres = &hose->mem_resources[i];
1396 if (!(pres->flags & IORESOURCE_MEM))
1397 continue;
1398 pr_debug("hose mem res: %pR\n", pres);
1399 if ((pres->start - offset) <= 0xa0000 &&
1400 (pres->end - offset) >= 0xbffff)
1401 break;
1402 }
1403 if (i >= 3)
1404 return;
1405 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1406 BUG_ON(res == NULL);
1407 res->name = "Legacy VGA memory";
1408 res->flags = IORESOURCE_MEM;
1409 res->start = 0xa0000 + offset;
1410 res->end = 0xbffff + offset;
1411 pr_debug("Candidate VGA memory: %pR\n", res);
1412 if (request_resource(pres, res)) {
1413 printk(KERN_DEBUG
1414 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1415 pci_domain_nr(bus), bus->number, res);
1416 kfree(res);
1417 }
1418}
1419
1420void __init pcibios_resource_survey(void)
1421{
1422 struct pci_bus *b;
1423
1424 /* Allocate and assign resources. If we re-assign everything, then
1425 * we skip the allocate phase
1426 */
1427 list_for_each_entry(b, &pci_root_buses, node)
1428 pcibios_allocate_bus_resources(b);
1429
1430 if (!(pci_flags & PCI_REASSIGN_ALL_RSRC)) {
1431 pcibios_allocate_resources(0);
1432 pcibios_allocate_resources(1);
1433 }
1434
1435 /* Before we start assigning unassigned resource, we try to reserve
1436 * the low IO area and the VGA memory area if they intersect the
1437 * bus available resources to avoid allocating things on top of them
1438 */
1439 if (!(pci_flags & PCI_PROBE_ONLY)) {
1440 list_for_each_entry(b, &pci_root_buses, node)
1441 pcibios_reserve_legacy_regions(b);
1442 }
1443
1444 /* Now, if the platform didn't decide to blindly trust the firmware,
1445 * we proceed to assigning things that were left unassigned
1446 */
1447 if (!(pci_flags & PCI_PROBE_ONLY)) {
1448 pr_debug("PCI: Assigning unassigned resources...\n");
1449 pci_assign_unassigned_resources();
1450 }
1451}
1452
1453#ifdef CONFIG_HOTPLUG
1454
1455/* This is used by the PCI hotplug driver to allocate resource
1456 * of newly plugged busses. We can try to consolidate with the
1457 * rest of the code later, for now, keep it as-is as our main
1458 * resource allocation function doesn't deal with sub-trees yet.
1459 */
1460void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1461{
1462 struct pci_dev *dev;
1463 struct pci_bus *child_bus;
1464
1465 list_for_each_entry(dev, &bus->devices, bus_list) {
1466 int i;
1467
1468 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1469 struct resource *r = &dev->resource[i];
1470
1471 if (r->parent || !r->start || !r->flags)
1472 continue;
1473
1474 pr_debug("PCI: Claiming %s: "
1475 "Resource %d: %016llx..%016llx [%x]\n",
1476 pci_name(dev), i,
1477 (unsigned long long)r->start,
1478 (unsigned long long)r->end,
1479 (unsigned int)r->flags);
1480
1481 pci_claim_resource(dev, i);
1482 }
1483 }
1484
1485 list_for_each_entry(child_bus, &bus->children, node)
1486 pcibios_claim_one_bus(child_bus);
1487}
1488EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1489
1490
1491/* pcibios_finish_adding_to_bus
1492 *
1493 * This is to be called by the hotplug code after devices have been
1494 * added to a bus, this include calling it for a PHB that is just
1495 * being added
1496 */
1497void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1498{
1499 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1500 pci_domain_nr(bus), bus->number);
1501
1502 /* Allocate bus and devices resources */
1503 pcibios_allocate_bus_resources(bus);
1504 pcibios_claim_one_bus(bus);
1505
1506 /* Add new devices to global lists. Register in proc, sysfs. */
1507 pci_bus_add_devices(bus);
1508
1509 /* Fixup EEH */
1510 eeh_add_device_tree_late(bus);
1511}
1512EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1513
1514#endif /* CONFIG_HOTPLUG */
1515
1516int pcibios_enable_device(struct pci_dev *dev, int mask)
1517{
1518 return pci_enable_resources(dev, mask);
1519}
1520
1521void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1522{
1523 struct pci_bus *bus = hose->bus;
1524 struct resource *res;
1525 int i;
1526
1527 /* Hookup PHB IO resource */
1528 bus->resource[0] = res = &hose->io_resource;
1529
1530 if (!res->flags) {
1531 printk(KERN_WARNING "PCI: I/O resource not set for host"
1532 " bridge %s (domain %d)\n",
1533 hose->dn->full_name, hose->global_number);
1534 /* Workaround for lack of IO resource only on 32-bit */
1535 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1536 res->end = res->start + IO_SPACE_LIMIT;
1537 res->flags = IORESOURCE_IO;
1538 }
1539
1540 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1541 (unsigned long long)res->start,
1542 (unsigned long long)res->end,
1543 (unsigned long)res->flags);
1544
1545 /* Hookup PHB Memory resources */
1546 for (i = 0; i < 3; ++i) {
1547 res = &hose->mem_resources[i];
1548 if (!res->flags) {
1549 if (i > 0)
1550 continue;
1551 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1552 "host bridge %s (domain %d)\n",
1553 hose->dn->full_name, hose->global_number);
1554
1555 /* Workaround for lack of MEM resource only on 32-bit */
1556 res->start = hose->pci_mem_offset;
1557 res->end = (resource_size_t)-1LL;
1558 res->flags = IORESOURCE_MEM;
1559
1560 }
1561 bus->resource[i+1] = res;
1562
1563 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1564 i, (unsigned long long)res->start,
1565 (unsigned long long)res->end,
1566 (unsigned long)res->flags);
1567 }
1568
1569 pr_debug("PCI: PHB MEM offset = %016llx\n",
1570 (unsigned long long)hose->pci_mem_offset);
1571 pr_debug("PCI: PHB IO offset = %08lx\n",
1572 (unsigned long)hose->io_base_virt - _IO_BASE);
1573}
1574
1575/*
1576 * Null PCI config access functions, for the case when we can't
1577 * find a hose.
1578 */
1579#define NULL_PCI_OP(rw, size, type) \
1580static int \
1581null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1582{ \
1583 return PCIBIOS_DEVICE_NOT_FOUND; \
1584}
1585
1586static int
1587null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1588 int len, u32 *val)
1589{
1590 return PCIBIOS_DEVICE_NOT_FOUND;
1591}
1592
1593static int
1594null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1595 int len, u32 val)
1596{
1597 return PCIBIOS_DEVICE_NOT_FOUND;
1598}
1599
1600static struct pci_ops null_pci_ops = {
1601 .read = null_read_config,
1602 .write = null_write_config,
1603};
1604
1605/*
1606 * These functions are used early on before PCI scanning is done
1607 * and all of the pci_dev and pci_bus structures have been created.
1608 */
1609static struct pci_bus *
1610fake_pci_bus(struct pci_controller *hose, int busnr)
1611{
1612 static struct pci_bus bus;
1613
1614 if (!hose)
1615 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1616
1617 bus.number = busnr;
1618 bus.sysdata = hose;
1619 bus.ops = hose ? hose->ops : &null_pci_ops;
1620 return &bus;
1621}
1622
1623#define EARLY_PCI_OP(rw, size, type) \
1624int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1625 int devfn, int offset, type value) \
1626{ \
1627 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1628 devfn, offset, value); \
1629}
1630
1631EARLY_PCI_OP(read, byte, u8 *)
1632EARLY_PCI_OP(read, word, u16 *)
1633EARLY_PCI_OP(read, dword, u32 *)
1634EARLY_PCI_OP(write, byte, u8)
1635EARLY_PCI_OP(write, word, u16)
1636EARLY_PCI_OP(write, dword, u32)
1637
1638int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1639 int cap)
1640{
1641 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1642}
diff --git a/arch/microblaze/pci/pci_32.c b/arch/microblaze/pci/pci_32.c
new file mode 100644
index 000000000000..7e0c94f501cc
--- /dev/null
+++ b/arch/microblaze/pci/pci_32.c
@@ -0,0 +1,430 @@
1/*
2 * Common pmac/prep/chrp pci routines. -- Cort
3 */
4
5#include <linux/kernel.h>
6#include <linux/pci.h>
7#include <linux/delay.h>
8#include <linux/string.h>
9#include <linux/init.h>
10#include <linux/capability.h>
11#include <linux/sched.h>
12#include <linux/errno.h>
13#include <linux/bootmem.h>
14#include <linux/irq.h>
15#include <linux/list.h>
16#include <linux/of.h>
17
18#include <asm/processor.h>
19#include <asm/io.h>
20#include <asm/prom.h>
21#include <asm/sections.h>
22#include <asm/pci-bridge.h>
23#include <asm/byteorder.h>
24#include <asm/uaccess.h>
25
26#undef DEBUG
27
28unsigned long isa_io_base;
29unsigned long pci_dram_offset;
30int pcibios_assign_bus_offset = 1;
31
32static u8 *pci_to_OF_bus_map;
33
34/* By default, we don't re-assign bus numbers. We do this only on
35 * some pmacs
36 */
37static int pci_assign_all_buses;
38
39static int pci_bus_count;
40
41/*
42 * Functions below are used on OpenFirmware machines.
43 */
44static void
45make_one_node_map(struct device_node *node, u8 pci_bus)
46{
47 const int *bus_range;
48 int len;
49
50 if (pci_bus >= pci_bus_count)
51 return;
52 bus_range = of_get_property(node, "bus-range", &len);
53 if (bus_range == NULL || len < 2 * sizeof(int)) {
54 printk(KERN_WARNING "Can't get bus-range for %s, "
55 "assuming it starts at 0\n", node->full_name);
56 pci_to_OF_bus_map[pci_bus] = 0;
57 } else
58 pci_to_OF_bus_map[pci_bus] = bus_range[0];
59
60 for_each_child_of_node(node, node) {
61 struct pci_dev *dev;
62 const unsigned int *class_code, *reg;
63
64 class_code = of_get_property(node, "class-code", NULL);
65 if (!class_code ||
66 ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
67 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
68 continue;
69 reg = of_get_property(node, "reg", NULL);
70 if (!reg)
71 continue;
72 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
73 if (!dev || !dev->subordinate) {
74 pci_dev_put(dev);
75 continue;
76 }
77 make_one_node_map(node, dev->subordinate->number);
78 pci_dev_put(dev);
79 }
80}
81
82void
83pcibios_make_OF_bus_map(void)
84{
85 int i;
86 struct pci_controller *hose, *tmp;
87 struct property *map_prop;
88 struct device_node *dn;
89
90 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
91 if (!pci_to_OF_bus_map) {
92 printk(KERN_ERR "Can't allocate OF bus map !\n");
93 return;
94 }
95
96 /* We fill the bus map with invalid values, that helps
97 * debugging.
98 */
99 for (i = 0; i < pci_bus_count; i++)
100 pci_to_OF_bus_map[i] = 0xff;
101
102 /* For each hose, we begin searching bridges */
103 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
104 struct device_node *node = hose->dn;
105
106 if (!node)
107 continue;
108 make_one_node_map(node, hose->first_busno);
109 }
110 dn = of_find_node_by_path("/");
111 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
112 if (map_prop) {
113 BUG_ON(pci_bus_count > map_prop->length);
114 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
115 }
116 of_node_put(dn);
117#ifdef DEBUG
118 printk(KERN_INFO "PCI->OF bus map:\n");
119 for (i = 0; i < pci_bus_count; i++) {
120 if (pci_to_OF_bus_map[i] == 0xff)
121 continue;
122 printk(KERN_INFO "%d -> %d\n", i, pci_to_OF_bus_map[i]);
123 }
124#endif
125}
126
127typedef int (*pci_OF_scan_iterator)(struct device_node *node, void *data);
128
129static struct device_node *scan_OF_pci_childs(struct device_node *parent,
130 pci_OF_scan_iterator filter, void *data)
131{
132 struct device_node *node;
133 struct device_node *sub_node;
134
135 for_each_child_of_node(parent, node) {
136 const unsigned int *class_code;
137
138 if (filter(node, data)) {
139 of_node_put(node);
140 return node;
141 }
142
143 /* For PCI<->PCI bridges or CardBus bridges, we go down
144 * Note: some OFs create a parent node "multifunc-device" as
145 * a fake root for all functions of a multi-function device,
146 * we go down them as well.
147 */
148 class_code = of_get_property(node, "class-code", NULL);
149 if ((!class_code ||
150 ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
151 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
152 strcmp(node->name, "multifunc-device"))
153 continue;
154 sub_node = scan_OF_pci_childs(node, filter, data);
155 if (sub_node) {
156 of_node_put(node);
157 return sub_node;
158 }
159 }
160 return NULL;
161}
162
163static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
164 unsigned int devfn)
165{
166 struct device_node *np, *cnp;
167 const u32 *reg;
168 unsigned int psize;
169
170 for_each_child_of_node(parent, np) {
171 reg = of_get_property(np, "reg", &psize);
172 if (reg && psize >= 4 && ((reg[0] >> 8) & 0xff) == devfn)
173 return np;
174
175 /* Note: some OFs create a parent node "multifunc-device" as
176 * a fake root for all functions of a multi-function device,
177 * we go down them as well. */
178 if (!strcmp(np->name, "multifunc-device")) {
179 cnp = scan_OF_for_pci_dev(np, devfn);
180 if (cnp)
181 return cnp;
182 }
183 }
184 return NULL;
185}
186
187
188static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
189{
190 struct device_node *parent, *np;
191
192 /* Are we a root bus ? */
193 if (bus->self == NULL || bus->parent == NULL) {
194 struct pci_controller *hose = pci_bus_to_host(bus);
195 if (hose == NULL)
196 return NULL;
197 return of_node_get(hose->dn);
198 }
199
200 /* not a root bus, we need to get our parent */
201 parent = scan_OF_for_pci_bus(bus->parent);
202 if (parent == NULL)
203 return NULL;
204
205 /* now iterate for children for a match */
206 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
207 of_node_put(parent);
208
209 return np;
210}
211
212/*
213 * Scans the OF tree for a device node matching a PCI device
214 */
215struct device_node *
216pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
217{
218 struct device_node *parent, *np;
219
220 pr_debug("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
221 parent = scan_OF_for_pci_bus(bus);
222 if (parent == NULL)
223 return NULL;
224 pr_debug(" parent is %s\n", parent ? parent->full_name : "<NULL>");
225 np = scan_OF_for_pci_dev(parent, devfn);
226 of_node_put(parent);
227 pr_debug(" result is %s\n", np ? np->full_name : "<NULL>");
228
229 /* XXX most callers don't release the returned node
230 * mostly because ppc64 doesn't increase the refcount,
231 * we need to fix that.
232 */
233 return np;
234}
235EXPORT_SYMBOL(pci_busdev_to_OF_node);
236
237struct device_node*
238pci_device_to_OF_node(struct pci_dev *dev)
239{
240 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
241}
242EXPORT_SYMBOL(pci_device_to_OF_node);
243
244static int
245find_OF_pci_device_filter(struct device_node *node, void *data)
246{
247 return ((void *)node == data);
248}
249
250/*
251 * Returns the PCI device matching a given OF node
252 */
253int
254pci_device_from_OF_node(struct device_node *node, u8 *bus, u8 *devfn)
255{
256 const unsigned int *reg;
257 struct pci_controller *hose;
258 struct pci_dev *dev = NULL;
259
260 /* Make sure it's really a PCI device */
261 hose = pci_find_hose_for_OF_device(node);
262 if (!hose || !hose->dn)
263 return -ENODEV;
264 if (!scan_OF_pci_childs(hose->dn,
265 find_OF_pci_device_filter, (void *)node))
266 return -ENODEV;
267 reg = of_get_property(node, "reg", NULL);
268 if (!reg)
269 return -ENODEV;
270 *bus = (reg[0] >> 16) & 0xff;
271 *devfn = ((reg[0] >> 8) & 0xff);
272
273 /* Ok, here we need some tweak. If we have already renumbered
274 * all busses, we can't rely on the OF bus number any more.
275 * the pci_to_OF_bus_map is not enough as several PCI busses
276 * may match the same OF bus number.
277 */
278 if (!pci_to_OF_bus_map)
279 return 0;
280
281 for_each_pci_dev(dev)
282 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
283 dev->devfn == *devfn) {
284 *bus = dev->bus->number;
285 pci_dev_put(dev);
286 return 0;
287 }
288
289 return -ENODEV;
290}
291EXPORT_SYMBOL(pci_device_from_OF_node);
292
293/* We create the "pci-OF-bus-map" property now so it appears in the
294 * /proc device tree
295 */
296void __init
297pci_create_OF_bus_map(void)
298{
299 struct property *of_prop;
300 struct device_node *dn;
301
302 of_prop = (struct property *) alloc_bootmem(sizeof(struct property) + \
303 256);
304 if (!of_prop)
305 return;
306 dn = of_find_node_by_path("/");
307 if (dn) {
308 memset(of_prop, -1, sizeof(struct property) + 256);
309 of_prop->name = "pci-OF-bus-map";
310 of_prop->length = 256;
311 of_prop->value = &of_prop[1];
312 prom_add_property(dn, of_prop);
313 of_node_put(dn);
314 }
315}
316
317static void __devinit pcibios_scan_phb(struct pci_controller *hose)
318{
319 struct pci_bus *bus;
320 struct device_node *node = hose->dn;
321 unsigned long io_offset;
322 struct resource *res = &hose->io_resource;
323
324 pr_debug("PCI: Scanning PHB %s\n",
325 node ? node->full_name : "<NO NAME>");
326
327 /* Create an empty bus for the toplevel */
328 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
329 if (bus == NULL) {
330 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
331 hose->global_number);
332 return;
333 }
334 bus->secondary = hose->first_busno;
335 hose->bus = bus;
336
337 /* Fixup IO space offset */
338 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
339 res->start = (res->start + io_offset) & 0xffffffffu;
340 res->end = (res->end + io_offset) & 0xffffffffu;
341
342 /* Wire up PHB bus resources */
343 pcibios_setup_phb_resources(hose);
344
345 /* Scan children */
346 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
347}
348
349static int __init pcibios_init(void)
350{
351 struct pci_controller *hose, *tmp;
352 int next_busno = 0;
353
354 printk(KERN_INFO "PCI: Probing PCI hardware\n");
355
356 if (pci_flags & PCI_REASSIGN_ALL_BUS) {
357 printk(KERN_INFO "setting pci_asign_all_busses\n");
358 pci_assign_all_buses = 1;
359 }
360
361 /* Scan all of the recorded PCI controllers. */
362 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
363 if (pci_assign_all_buses)
364 hose->first_busno = next_busno;
365 hose->last_busno = 0xff;
366 pcibios_scan_phb(hose);
367 printk(KERN_INFO "calling pci_bus_add_devices()\n");
368 pci_bus_add_devices(hose->bus);
369 if (pci_assign_all_buses || next_busno <= hose->last_busno)
370 next_busno = hose->last_busno + \
371 pcibios_assign_bus_offset;
372 }
373 pci_bus_count = next_busno;
374
375 /* OpenFirmware based machines need a map of OF bus
376 * numbers vs. kernel bus numbers since we may have to
377 * remap them.
378 */
379 if (pci_assign_all_buses)
380 pcibios_make_OF_bus_map();
381
382 /* Call common code to handle resource allocation */
383 pcibios_resource_survey();
384
385 return 0;
386}
387
388subsys_initcall(pcibios_init);
389
390static struct pci_controller*
391pci_bus_to_hose(int bus)
392{
393 struct pci_controller *hose, *tmp;
394
395 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
396 if (bus >= hose->first_busno && bus <= hose->last_busno)
397 return hose;
398 return NULL;
399}
400
401/* Provide information on locations of various I/O regions in physical
402 * memory. Do this on a per-card basis so that we choose the right
403 * root bridge.
404 * Note that the returned IO or memory base is a physical address
405 */
406
407long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
408{
409 struct pci_controller *hose;
410 long result = -EOPNOTSUPP;
411
412 hose = pci_bus_to_hose(bus);
413 if (!hose)
414 return -ENODEV;
415
416 switch (which) {
417 case IOBASE_BRIDGE_NUMBER:
418 return (long)hose->first_busno;
419 case IOBASE_MEMORY:
420 return (long)hose->pci_mem_offset;
421 case IOBASE_IO:
422 return (long)hose->io_base_phys;
423 case IOBASE_ISA_IO:
424 return (long)isa_io_base;
425 case IOBASE_ISA_MEM:
426 return (long)isa_mem_base;
427 }
428
429 return result;
430}
diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c
new file mode 100644
index 000000000000..7869a41b0f94
--- /dev/null
+++ b/arch/microblaze/pci/xilinx_pci.c
@@ -0,0 +1,168 @@
1/*
2 * PCI support for Xilinx plbv46_pci soft-core which can be used on
3 * Xilinx Virtex ML410 / ML510 boards.
4 *
5 * Copyright 2009 Roderick Colenbrander
6 * Copyright 2009 Secret Lab Technologies Ltd.
7 *
8 * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
9 * by Benjamin Herrenschmidt.
10 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17#include <linux/ioport.h>
18#include <linux/of.h>
19#include <linux/pci.h>
20#include <asm/io.h>
21
22#define XPLB_PCI_ADDR 0x10c
23#define XPLB_PCI_DATA 0x110
24#define XPLB_PCI_BUS 0x114
25
26#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
27 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
28
29static struct of_device_id xilinx_pci_match[] = {
30 { .compatible = "xlnx,plbv46-pci-1.03.a", },
31 {}
32};
33
34/**
35 * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
36 */
37static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
38{
39 struct pci_controller *hose;
40 int i;
41
42 if (dev->devfn || dev->bus->self)
43 return;
44
45 hose = pci_bus_to_host(dev->bus);
46 if (!hose)
47 return;
48
49 if (!of_match_node(xilinx_pci_match, hose->dn))
50 return;
51
52 /* Hide the PCI host BARs from the kernel as their content doesn't
53 * fit well in the resource management
54 */
55 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
56 dev->resource[i].start = 0;
57 dev->resource[i].end = 0;
58 dev->resource[i].flags = 0;
59 }
60
61 dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
62 pci_name(dev));
63}
64DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
65
66#ifdef DEBUG
67/**
68 * xilinx_pci_exclude_device - Don't do config access for non-root bus
69 *
70 * This is a hack. Config access to any bus other than bus 0 does not
71 * currently work on the ML510 so we prevent it here.
72 */
73static int
74xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
75{
76 return (bus != 0);
77}
78
79/**
80 * xilinx_early_pci_scan - List pci config space for available devices
81 *
82 * List pci devices in very early phase.
83 */
84void __init xilinx_early_pci_scan(struct pci_controller *hose)
85{
86 u32 bus = 0;
87 u32 val, dev, func, offset;
88
89 /* Currently we have only 2 device connected - up-to 32 devices */
90 for (dev = 0; dev < 2; dev++) {
91 /* List only first function number - up-to 8 functions */
92 for (func = 0; func < 1; func++) {
93 printk(KERN_INFO "%02x:%02x:%02x", bus, dev, func);
94 /* read the first 64 standardized bytes */
95 /* Up-to 192 bytes can be list of capabilities */
96 for (offset = 0; offset < 64; offset += 4) {
97 early_read_config_dword(hose, bus,
98 PCI_DEVFN(dev, func), offset, &val);
99 if (offset == 0 && val == 0xFFFFFFFF) {
100 printk(KERN_CONT "\nABSENT");
101 break;
102 }
103 if (!(offset % 0x10))
104 printk(KERN_CONT "\n%04x: ", offset);
105
106 printk(KERN_CONT "%08x ", val);
107 }
108 printk(KERN_INFO "\n");
109 }
110 }
111}
112#else
113void __init xilinx_early_pci_scan(struct pci_controller *hose)
114{
115}
116#endif
117
118/**
119 * xilinx_pci_init - Find and register a Xilinx PCI host bridge
120 */
121void __init xilinx_pci_init(void)
122{
123 struct pci_controller *hose;
124 struct resource r;
125 void __iomem *pci_reg;
126 struct device_node *pci_node;
127
128 pci_node = of_find_matching_node(NULL, xilinx_pci_match);
129 if (!pci_node)
130 return;
131
132 if (of_address_to_resource(pci_node, 0, &r)) {
133 pr_err("xilinx-pci: cannot resolve base address\n");
134 return;
135 }
136
137 hose = pcibios_alloc_controller(pci_node);
138 if (!hose) {
139 pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
140 return;
141 }
142
143 /* Setup config space */
144 setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
145 r.start + XPLB_PCI_DATA,
146 INDIRECT_TYPE_SET_CFG_TYPE);
147
148 /* According to the xilinx plbv46_pci documentation the soft-core starts
149 * a self-init when the bus master enable bit is set. Without this bit
150 * set the pci bus can't be scanned.
151 */
152 early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
153
154 /* Set the max latency timer to 255 */
155 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
156
157 /* Set the max bus number to 255, and bus/subbus no's to 0 */
158 pci_reg = of_iomap(pci_node, 0);
159 out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
160 iounmap(pci_reg);
161
162 /* Register the host bridge with the linux kernel! */
163 pci_process_bridge_OF_ranges(hose, pci_node,
164 INDIRECT_TYPE_SET_CFG_TYPE);
165
166 pr_info("xilinx-pci: Registered PCI host bridge\n");
167 xilinx_early_pci_scan(hose);
168}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 04:46:57 -0500