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authorMichal Simek <monstr@monstr.eu>2009-03-27 09:25:11 -0400
committerMichal Simek <monstr@monstr.eu>2009-03-27 09:25:11 -0400
commit406107dacde125346c313d34534eed937eb25444 (patch)
tree18f9d4a73eabfd13810ca027fdf76d11f061607d /arch/microblaze/kernel
parent8e0ee43bc2c3e19db56a4adaa9a9b04ce885cd84 (diff)
microblaze_v8: Cpuinfo handling
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/kernel')
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c101
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo-static.c144
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo.c86
3 files changed, 331 insertions, 0 deletions
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
new file mode 100644
index 000000000000..cf7424a6bb87
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
@@ -0,0 +1,101 @@
1/*
2 * Support for MicroBlaze PVR (processor version register)
3 *
4 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2007-2009 PetaLogix
6 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/string.h>
15#include <asm/pvr.h>
16#include <asm/cpuinfo.h>
17
18/*
19 * Helper macro to map between fields in our struct cpuinfo, and
20 * the PVR macros in pvr.h.
21 */
22
23#define CI(c, p) { ci->c = PVR_##p(pvr); }
24#define err_printk(x) \
25 early_printk("ERROR: Microblaze " x " - different for PVR and DTS\n");
26
27void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
28{
29 struct pvr_s pvr;
30 int temp; /* for saving temp value */
31 get_pvr(&pvr);
32
33 temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |\
34 PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr);
35 if (ci->use_instr != temp)
36 err_printk("BARREL, MSR, PCMP or DIV");
37 ci->use_instr = temp;
38
39 temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr);
40 if (ci->use_mult != temp)
41 err_printk("HW_MUL");
42 ci->use_mult = temp;
43
44 temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr);
45 if (ci->use_fpu != temp)
46 err_printk("HW_FPU");
47 ci->use_fpu = temp;
48
49 ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |\
50 PVR_UNALIGNED_EXCEPTION(pvr) |\
51 PVR_ILL_OPCODE_EXCEPTION(pvr) |\
52 PVR_IOPB_BUS_EXCEPTION(pvr) |\
53 PVR_DOPB_BUS_EXCEPTION(pvr) |\
54 PVR_DIV_ZERO_EXCEPTION(pvr) |\
55 PVR_FPU_EXCEPTION(pvr) |\
56 PVR_FSL_EXCEPTION(pvr);
57
58 CI(pvr_user1, USER1);
59 CI(pvr_user2, USER2);
60
61 CI(mmu, USE_MMU);
62
63 CI(ver_code, VERSION);
64
65 CI(use_icache, USE_ICACHE);
66 CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
67 CI(icache_write, ICACHE_ALLOW_WR);
68 CI(icache_line, ICACHE_LINE_LEN);
69 CI(icache_size, ICACHE_BYTE_SIZE);
70 CI(icache_base, ICACHE_BASEADDR);
71 CI(icache_high, ICACHE_HIGHADDR);
72
73 CI(use_dcache, USE_DCACHE);
74 CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
75 CI(dcache_write, DCACHE_ALLOW_WR);
76 CI(dcache_line, DCACHE_LINE_LEN);
77 CI(dcache_size, DCACHE_BYTE_SIZE);
78 CI(dcache_base, DCACHE_BASEADDR);
79 CI(dcache_high, DCACHE_HIGHADDR);
80
81 CI(use_dopb, D_OPB);
82 CI(use_iopb, I_OPB);
83 CI(use_dlmb, D_LMB);
84 CI(use_ilmb, I_LMB);
85 CI(num_fsl, FSL_LINKS);
86
87 CI(irq_edge, INTERRUPT_IS_EDGE);
88 CI(irq_positive, EDGE_IS_POSITIVE);
89
90 CI(area_optimised, AREA_OPTIMISED);
91
92 CI(hw_debug, DEBUG_ENABLED);
93 CI(num_pc_brk, NUMBER_OF_PC_BRK);
94 CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);
95 CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);
96
97 CI(fpga_family_code, TARGET_FAMILY);
98
99 /* take timebase-frequency from DTS */
100 ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
101}
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
new file mode 100644
index 000000000000..cfe44effdb77
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -0,0 +1,144 @@
1/*
2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/string.h>
14#include <asm/cpuinfo.h>
15#include <asm/pvr.h>
16
17const static char family_string[] = CONFIG_XILINX_MICROBLAZE0_FAMILY;
18const static char cpu_ver_string[] = CONFIG_XILINX_MICROBLAZE0_HW_VER;
19
20#define err_printk(x) \
21 early_printk("ERROR: Microblaze " x "- different for kernel and DTS\n");
22
23void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
24{
25 int i = 0;
26
27 ci->use_instr =
28 (fcpu(cpu, "xlnx,use-barrel") ? PVR0_USE_BARREL_MASK : 0) |
29 (fcpu(cpu, "xlnx,use-msr-instr") ? PVR2_USE_MSR_INSTR : 0) |
30 (fcpu(cpu, "xlnx,use-pcmp-instr") ? PVR2_USE_PCMP_INSTR : 0) |
31 (fcpu(cpu, "xlnx,use-div") ? PVR0_USE_DIV_MASK : 0);
32 if (CONFIG_XILINX_MICROBLAZE0_USE_BARREL)
33 i |= PVR0_USE_BARREL_MASK;
34 if (CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR)
35 i |= PVR2_USE_MSR_INSTR;
36 if (CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR)
37 i |= PVR2_USE_PCMP_INSTR;
38 if (CONFIG_XILINX_MICROBLAZE0_USE_DIV)
39 i |= PVR0_USE_DIV_MASK;
40 if (ci->use_instr != i)
41 err_printk("BARREL, MSR, PCMP or DIV");
42
43 ci->use_mult = fcpu(cpu, "xlnx,use-hw-mul");
44 if (ci->use_mult != CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)
45 err_printk("HW_MUL");
46 ci->use_mult =
47 (ci->use_mult > 1 ?
48 (PVR2_USE_MUL64_MASK | PVR0_USE_HW_MUL_MASK) :
49 (ci->use_mult == 1 ? PVR0_USE_HW_MUL_MASK : 0));
50
51 ci->use_fpu = fcpu(cpu, "xlnx,use-fpu");
52 if (ci->use_fpu != CONFIG_XILINX_MICROBLAZE0_USE_FPU)
53 err_printk("HW_FPU");
54 ci->use_fpu = (ci->use_fpu > 1 ?
55 (PVR2_USE_FPU2_MASK | PVR0_USE_FPU_MASK) :
56 (ci->use_fpu == 1 ? PVR0_USE_FPU_MASK : 0));
57
58 ci->use_exc =
59 (fcpu(cpu, "xlnx,unaligned-exceptions") ?
60 PVR2_UNALIGNED_EXC_MASK : 0) |
61 (fcpu(cpu, "xlnx,ill-opcode-exception") ?
62 PVR2_ILL_OPCODE_EXC_MASK : 0) |
63 (fcpu(cpu, "xlnx,iopb-bus-exception") ?
64 PVR2_IOPB_BUS_EXC_MASK : 0) |
65 (fcpu(cpu, "xlnx,dopb-bus-exception") ?
66 PVR2_DOPB_BUS_EXC_MASK : 0) |
67 (fcpu(cpu, "xlnx,div-zero-exception") ?
68 PVR2_DIV_ZERO_EXC_MASK : 0) |
69 (fcpu(cpu, "xlnx,fpu-exception") ? PVR2_FPU_EXC_MASK : 0) |
70 (fcpu(cpu, "xlnx,fsl-exception") ? PVR2_USE_EXTEND_FSL : 0);
71
72 ci->use_icache = fcpu(cpu, "xlnx,use-icache");
73 ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
74 ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
75 ci->icache_line = fcpu(cpu, "xlnx,icache-line-len") << 2;
76 if (!ci->icache_line) {
77 if (fcpu(cpu, "xlnx,icache-use-fsl"))
78 ci->icache_line = 4 << 2;
79 else
80 ci->icache_line = 1 << 2;
81 }
82 ci->icache_size = fcpu(cpu, "i-cache-size");
83 ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
84 ci->icache_high = fcpu(cpu, "i-cache-highaddr");
85
86 ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
87 ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
88 ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
89 ci->dcache_line = fcpu(cpu, "xlnx,dcache-line-len") << 2;
90 if (!ci->dcache_line) {
91 if (fcpu(cpu, "xlnx,dcache-use-fsl"))
92 ci->dcache_line = 4 << 2;
93 else
94 ci->dcache_line = 1 << 2;
95 }
96 ci->dcache_size = fcpu(cpu, "d-cache-size");
97 ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");
98 ci->dcache_high = fcpu(cpu, "d-cache-highaddr");
99
100 ci->use_dopb = fcpu(cpu, "xlnx,d-opb");
101 ci->use_iopb = fcpu(cpu, "xlnx,i-opb");
102 ci->use_dlmb = fcpu(cpu, "xlnx,d-lmb");
103 ci->use_ilmb = fcpu(cpu, "xlnx,i-lmb");
104
105 ci->num_fsl = fcpu(cpu, "xlnx,fsl-links");
106 ci->irq_edge = fcpu(cpu, "xlnx,interrupt-is-edge");
107 ci->irq_positive = fcpu(cpu, "xlnx,edge-is-positive");
108 ci->area_optimised = 0;
109
110 ci->hw_debug = fcpu(cpu, "xlnx,debug-enabled");
111 ci->num_pc_brk = fcpu(cpu, "xlnx,number-of-pc-brk");
112 ci->num_rd_brk = fcpu(cpu, "xlnx,number-of-rd-addr-brk");
113 ci->num_wr_brk = fcpu(cpu, "xlnx,number-of-wr-addr-brk");
114
115 ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
116
117 ci->pvr_user1 = fcpu(cpu, "xlnx,pvr-user1");
118 ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");
119
120 ci->mmu = fcpu(cpu, "xlnx,use-mmu");
121
122 ci->ver_code = 0;
123 ci->fpga_family_code = 0;
124
125 /* Do various fixups based on CPU version and FPGA family strings */
126
127 /* Resolved the CPU version code */
128 for (i = 0; cpu_ver_lookup[i].s != NULL; i++) {
129 if (strcmp(cpu_ver_lookup[i].s, cpu_ver_string) == 0)
130 ci->ver_code = cpu_ver_lookup[i].k;
131 }
132
133 /* Resolved the fpga family code */
134 for (i = 0; family_string_lookup[i].s != NULL; i++) {
135 if (strcmp(family_string_lookup[i].s, family_string) == 0)
136 ci->fpga_family_code = family_string_lookup[i].k;
137 }
138
139 /* FIXME - mb3 and spartan2 do not exist in PVR */
140 /* This is mb3 and on a non Spartan2 */
141 if (ci->ver_code == 0x20 && ci->fpga_family_code != 0xf0)
142 /* Hardware Multiplier in use */
143 ci->use_mult = 1;
144}
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
new file mode 100644
index 000000000000..4a740dfcf6da
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -0,0 +1,86 @@
1/*
2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <asm/cpuinfo.h>
14#include <asm/pvr.h>
15
16const struct cpu_ver_key cpu_ver_lookup[] = {
17 /* These key value are as per MBV field in PVR0 */
18 {"5.00.a", 0x01},
19 {"5.00.b", 0x02},
20 {"5.00.c", 0x03},
21 {"6.00.a", 0x04},
22 {"6.00.b", 0x06},
23 {"7.00.a", 0x05},
24 {"7.00.b", 0x07},
25 {"7.10.a", 0x08},
26 {"7.10.b", 0x09},
27 {"7.10.c", 0x0a},
28 {"7.10.d", 0x0b},
29 /* FIXME There is no keycode defined in MBV for these versions */
30 {"2.10.a", 0x10},
31 {"3.00.a", 0x20},
32 {"4.00.a", 0x30},
33 {"4.00.b", 0x40},
34 {NULL, 0},
35};
36
37/*
38 * FIXME Not sure if the actual key is defined by Xilinx in the PVR
39 */
40const struct family_string_key family_string_lookup[] = {
41 {"virtex2", 0x4},
42 {"virtex2pro", 0x5},
43 {"spartan3", 0x6},
44 {"virtex4", 0x7},
45 {"virtex5", 0x8},
46 {"spartan3e", 0x9},
47 {"spartan3a", 0xa},
48 {"spartan3an", 0xb},
49 {"spartan3adsp", 0xc},
50 /* FIXME There is no key code defined for spartan2 */
51 {"spartan2", 0xf0},
52 {NULL, 0},
53};
54
55struct cpuinfo cpuinfo;
56
57void __init setup_cpuinfo(void)
58{
59 struct device_node *cpu = NULL;
60
61 cpu = (struct device_node *) of_find_node_by_type(NULL, "cpu");
62 if (!cpu)
63 printk(KERN_ERR "You don't have cpu!!!\n");
64
65 printk(KERN_INFO "%s: initialising\n", __func__);
66
67 switch (cpu_has_pvr()) {
68 case 0:
69 printk(KERN_WARNING
70 "%s: No PVR support. Using static CPU info from FDT\n",
71 __func__);
72 set_cpuinfo_static(&cpuinfo, cpu);
73 break;
74/* FIXME I found weird behavior with MB 7.00.a/b
75 * please do not use FULL PVR with MMU */
76 case 1:
77 printk(KERN_INFO "%s: Using full CPU PVR support\n",
78 __func__);
79 set_cpuinfo_static(&cpuinfo, cpu);
80 set_cpuinfo_pvr_full(&cpuinfo, cpu);
81 break;
82 default:
83 printk(KERN_WARNING "%s: Unsupported PVR setting\n", __func__);
84 set_cpuinfo_static(&cpuinfo, cpu);
85 }
86}
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