diff options
author | Michal Simek <michal.simek@xilinx.com> | 2013-08-27 03:57:52 -0400 |
---|---|---|
committer | Michal Simek <michal.simek@xilinx.com> | 2013-09-03 05:13:46 -0400 |
commit | 9e77dab68496f68ccc50f47638c79f24106f0546 (patch) | |
tree | 04efa3995b0d4d47da403983dd9d5a8c218844e3 /arch/microblaze/kernel/timer.c | |
parent | 4f7b6de437544cd1e2e210919cb58cbe5cc3c393 (diff) |
microblaze: Remove selfmodified feature
This was experimental feature which has never been
widely used because it expects GCC behaviour.
Also remove INTC_BASE and TIMER_BASE macros.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/microblaze/kernel/timer.c')
-rw-r--r-- | arch/microblaze/kernel/timer.c | 47 |
1 files changed, 16 insertions, 31 deletions
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c index aec5020a6e31..d00a60e62e05 100644 --- a/arch/microblaze/kernel/timer.c +++ b/arch/microblaze/kernel/timer.c | |||
@@ -29,13 +29,7 @@ | |||
29 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
30 | #include <linux/cnt32_to_63.h> | 30 | #include <linux/cnt32_to_63.h> |
31 | 31 | ||
32 | #ifdef CONFIG_SELFMOD_TIMER | ||
33 | #include <asm/selfmod.h> | ||
34 | #define TIMER_BASE BARRIER_BASE_ADDR | ||
35 | #else | ||
36 | static unsigned int timer_baseaddr; | 32 | static unsigned int timer_baseaddr; |
37 | #define TIMER_BASE timer_baseaddr | ||
38 | #endif | ||
39 | 33 | ||
40 | static unsigned int freq_div_hz; | 34 | static unsigned int freq_div_hz; |
41 | static unsigned int timer_clock_freq; | 35 | static unsigned int timer_clock_freq; |
@@ -61,17 +55,19 @@ static unsigned int timer_clock_freq; | |||
61 | 55 | ||
62 | static inline void microblaze_timer0_stop(void) | 56 | static inline void microblaze_timer0_stop(void) |
63 | { | 57 | { |
64 | out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT); | 58 | out_be32(timer_baseaddr + TCSR0, |
59 | in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); | ||
65 | } | 60 | } |
66 | 61 | ||
67 | static inline void microblaze_timer0_start_periodic(unsigned long load_val) | 62 | static inline void microblaze_timer0_start_periodic(unsigned long load_val) |
68 | { | 63 | { |
69 | if (!load_val) | 64 | if (!load_val) |
70 | load_val = 1; | 65 | load_val = 1; |
71 | out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */ | 66 | /* loading value to timer reg */ |
67 | out_be32(timer_baseaddr + TLR0, load_val); | ||
72 | 68 | ||
73 | /* load the initial value */ | 69 | /* load the initial value */ |
74 | out_be32(TIMER_BASE + TCSR0, TCSR_LOAD); | 70 | out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); |
75 | 71 | ||
76 | /* see timer data sheet for detail | 72 | /* see timer data sheet for detail |
77 | * !ENALL - don't enable 'em all | 73 | * !ENALL - don't enable 'em all |
@@ -86,7 +82,7 @@ static inline void microblaze_timer0_start_periodic(unsigned long load_val) | |||
86 | * UDT - set the timer as down counter | 82 | * UDT - set the timer as down counter |
87 | * !MDT0 - generate mode | 83 | * !MDT0 - generate mode |
88 | */ | 84 | */ |
89 | out_be32(TIMER_BASE + TCSR0, | 85 | out_be32(timer_baseaddr + TCSR0, |
90 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); | 86 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); |
91 | } | 87 | } |
92 | 88 | ||
@@ -94,12 +90,13 @@ static inline void microblaze_timer0_start_oneshot(unsigned long load_val) | |||
94 | { | 90 | { |
95 | if (!load_val) | 91 | if (!load_val) |
96 | load_val = 1; | 92 | load_val = 1; |
97 | out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */ | 93 | /* loading value to timer reg */ |
94 | out_be32(timer_baseaddr + TLR0, load_val); | ||
98 | 95 | ||
99 | /* load the initial value */ | 96 | /* load the initial value */ |
100 | out_be32(TIMER_BASE + TCSR0, TCSR_LOAD); | 97 | out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); |
101 | 98 | ||
102 | out_be32(TIMER_BASE + TCSR0, | 99 | out_be32(timer_baseaddr + TCSR0, |
103 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); | 100 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); |
104 | } | 101 | } |
105 | 102 | ||
@@ -146,7 +143,7 @@ static struct clock_event_device clockevent_microblaze_timer = { | |||
146 | 143 | ||
147 | static inline void timer_ack(void) | 144 | static inline void timer_ack(void) |
148 | { | 145 | { |
149 | out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0)); | 146 | out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0)); |
150 | } | 147 | } |
151 | 148 | ||
152 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | 149 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
@@ -183,7 +180,7 @@ static __init void microblaze_clockevent_init(void) | |||
183 | static cycle_t microblaze_read(struct clocksource *cs) | 180 | static cycle_t microblaze_read(struct clocksource *cs) |
184 | { | 181 | { |
185 | /* reading actual value of timer 1 */ | 182 | /* reading actual value of timer 1 */ |
186 | return (cycle_t) (in_be32(TIMER_BASE + TCR1)); | 183 | return (cycle_t) (in_be32(timer_baseaddr + TCR1)); |
187 | } | 184 | } |
188 | 185 | ||
189 | static struct timecounter microblaze_tc = { | 186 | static struct timecounter microblaze_tc = { |
@@ -225,9 +222,10 @@ static int __init microblaze_clocksource_init(void) | |||
225 | panic("failed to register clocksource"); | 222 | panic("failed to register clocksource"); |
226 | 223 | ||
227 | /* stop timer1 */ | 224 | /* stop timer1 */ |
228 | out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT); | 225 | out_be32(timer_baseaddr + TCSR1, |
226 | in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT); | ||
229 | /* start timer1 - up counting without interrupt */ | 227 | /* start timer1 - up counting without interrupt */ |
230 | out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); | 228 | out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); |
231 | 229 | ||
232 | /* register timecounter - for ftrace support */ | 230 | /* register timecounter - for ftrace support */ |
233 | init_microblaze_timecounter(); | 231 | init_microblaze_timecounter(); |
@@ -246,17 +244,7 @@ void __init time_init(void) | |||
246 | u32 timer_num = 1; | 244 | u32 timer_num = 1; |
247 | struct device_node *timer = NULL; | 245 | struct device_node *timer = NULL; |
248 | const void *prop; | 246 | const void *prop; |
249 | #ifdef CONFIG_SELFMOD_TIMER | 247 | |
250 | unsigned int timer_baseaddr = 0; | ||
251 | int arr_func[] = { | ||
252 | (int)µblaze_read, | ||
253 | (int)&timer_interrupt, | ||
254 | (int)µblaze_clocksource_init, | ||
255 | (int)µblaze_timer_set_mode, | ||
256 | (int)µblaze_timer_set_next_event, | ||
257 | 0 | ||
258 | }; | ||
259 | #endif | ||
260 | prop = of_get_property(of_chosen, "system-timer", NULL); | 248 | prop = of_get_property(of_chosen, "system-timer", NULL); |
261 | if (prop) | 249 | if (prop) |
262 | timer = of_find_node_by_phandle(be32_to_cpup(prop)); | 250 | timer = of_find_node_by_phandle(be32_to_cpup(prop)); |
@@ -278,9 +266,6 @@ void __init time_init(void) | |||
278 | BUG(); | 266 | BUG(); |
279 | } | 267 | } |
280 | 268 | ||
281 | #ifdef CONFIG_SELFMOD_TIMER | ||
282 | selfmod_function((int *) arr_func, timer_baseaddr); | ||
283 | #endif | ||
284 | pr_info("%s #0 at 0x%08x, irq=%d\n", | 269 | pr_info("%s #0 at 0x%08x, irq=%d\n", |
285 | timer->name, timer_baseaddr, irq); | 270 | timer->name, timer_baseaddr, irq); |
286 | 271 | ||