microblaze: Fix copy_to_user_page macro

copy_to_user_page macro is used in mm/memory.c:access_process_vm
function. This function is called from ptrace code (POKETEXT, POKEDATA)
which write data to memory. Microblaze handle physical address for
caches that's why there is virt_to_phys conversion.

There is potential one location which can caused the problem on WB system.

The important is take a look at write PTRACEs requests
(POKE/TEXT, DATA, USR).

Note:
Majority of Microblaze PTRACE code is moved to generic location
in newer kernel version that's why this solution should work on
the newest kernel version too.

linux/io.h is in cacheflush because of mm/nommu.c

Tested on a WB system - hello world debugging.

Signed-off-by: Michal Simek <monstr@monstr.eu>

1 files changed, 16 insertions, 1 deletions

diff --git a/arch/microblaze/kernel/ptrace.c b/arch/microblaze/kernel/ptrace.c
index a4a7770c6140..dc03ffc8174a 100644
--- a/arch/microblaze/kernel/ptrace.c
+++ b/arch/microblaze/kernel/ptrace.c
@@ -38,6 +38,8 @@
 #include <asm/processor.h>
 #include <linux/uaccess.h>
 #include <asm/asm-offsets.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
 
 /* Returns the address where the register at REG_OFFS in P is stashed away. */
 static microblaze_reg_t *reg_save_addr(unsigned reg_offs,
@@ -101,8 +103,21 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         microblaze_reg_t *reg_addr = reg_save_addr(addr, child);
                         if (request == PTRACE_PEEKUSR)
                                 val = *reg_addr;
-                        else
+                        else {
+#if 1
                                 *reg_addr = data;
+#else
+                                /* MS potential problem on WB system
+                                 * Be aware that reg_addr is virtual address
+                                 * virt_to_phys conversion is necessary.
+                                 * This could be sensible solution.
+                                 */
+                                u32 paddr = virt_to_phys((u32)reg_addr);
+                                invalidate_icache_range(paddr, paddr + 4);
+                                *reg_addr = data;
+                                flush_dcache_range(paddr, paddr + 4);
+#endif
+                        }
                 } else
                         rval = -EIO;