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authorFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>2010-08-10 21:03:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-11 11:59:21 -0400
commita6eb9fe105d5de0053b261148cee56c94b4720ca (patch)
tree36e3f324a6a768397ef398674176c0f5f5365bff /arch/microblaze/include
parentcd1542c8197fc3c2eb3a8301505d5d9738fab1e4 (diff)
dma-mapping: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN
Now each architecture has the own dma_get_cache_alignment implementation. dma_get_cache_alignment returns the minimum DMA alignment. Architectures define it as ARCH_KMALLOC_MINALIGN (it's used to make sure that malloc'ed buffer is DMA-safe; the buffer doesn't share a cache with the others). So we can unify dma_get_cache_alignment implementations. This patch: dma_get_cache_alignment() needs to know if an architecture defines ARCH_KMALLOC_MINALIGN or not (needs to know if architecture has DMA alignment restriction). However, slab.h define ARCH_KMALLOC_MINALIGN if architectures doesn't define it. Let's rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN. ARCH_KMALLOC_MINALIGN is used only in the internals of slab/slob/slub (except for crypto). Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/microblaze/include')
-rw-r--r--arch/microblaze/include/asm/page.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 4f268faa0126..cf377d91da71 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -40,7 +40,7 @@
40#ifndef __ASSEMBLY__ 40#ifndef __ASSEMBLY__
41 41
42/* MS be sure that SLAB allocates aligned objects */ 42/* MS be sure that SLAB allocates aligned objects */
43#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES 43#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
44 44
45#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES 45#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
46 46