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authorMichal Simek <monstr@monstr.eu>2010-09-10 06:58:37 -0400
committerMichal Simek <monstr@monstr.eu>2010-10-21 01:51:55 -0400
commitb4dcaee50a3859bc3c7e6bace5daeec1d903e239 (patch)
treeed8fe545854940ce165ebf0c376f5742748c6043 /arch/microblaze/include/asm/pvr.h
parent6c3bbdd6609aefa6494ee3020f80108dbdccf755 (diff)
microblaze: trivial: Add comment for AXI pvr
AXI and OPB share some PVR macros. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/include/asm/pvr.h')
-rw-r--r--arch/microblaze/include/asm/pvr.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index cf59ef55c3b6..316105531d55 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -39,9 +39,9 @@ struct pvr_s {
39#define PVR1_USER2_MASK 0xFFFFFFFF 39#define PVR1_USER2_MASK 0xFFFFFFFF
40 40
41/* Configuration PVR masks */ 41/* Configuration PVR masks */
42#define PVR2_D_OPB_MASK 0x80000000 42#define PVR2_D_OPB_MASK 0x80000000 /* or AXI */
43#define PVR2_D_LMB_MASK 0x40000000 43#define PVR2_D_LMB_MASK 0x40000000
44#define PVR2_I_OPB_MASK 0x20000000 44#define PVR2_I_OPB_MASK 0x20000000 /* or AXI */
45#define PVR2_I_LMB_MASK 0x10000000 45#define PVR2_I_LMB_MASK 0x10000000
46#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 46#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
47#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 47#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
@@ -64,8 +64,8 @@ struct pvr_s {
64#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 64#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
65#define PVR2_UNALIGNED_EXC_MASK 0x00000020 65#define PVR2_UNALIGNED_EXC_MASK 0x00000020
66#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 66#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
67#define PVR2_IOPB_BUS_EXC_MASK 0x00000008 67#define PVR2_IOPB_BUS_EXC_MASK 0x00000008 /* or AXI */
68#define PVR2_DOPB_BUS_EXC_MASK 0x00000004 68#define PVR2_DOPB_BUS_EXC_MASK 0x00000004 /* or AXI */
69#define PVR2_DIV_ZERO_EXC_MASK 0x00000002 69#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
70#define PVR2_FPU_EXC_MASK 0x00000001 70#define PVR2_FPU_EXC_MASK 0x00000001
71 71