m68k,m68knommu: merge header files

Merge header files for m68k and m68knommu to the single location:

    arch/m68k/include/asm

The majority of this patch was the result of the
script that is included in the changelog below.

The script was originally written by Arnd Bergman and
exten by me to cover a few more files.

When the header files differed the script uses the following:

The original m68k file is named <file>_mm.h  [mm for memory manager]
The m68knommu file is named <file>_no.h [no for no memory manager]

The files uses the following include guard:

This include gaurd works as the m68knommu toolchain set
the __uClinux__ symbol - so this should work in userspace too.

Merging the header files for m68k and m68knommu exposes the
(unexpected?) ABI differences thus it is easier to actually
identify these and thus to fix them.

The commit has been build tested with both a m68k and
a m68knommu toolchain - with success.

The commit has also been tested with "make headers_check"
and this patch fixes make headers_check for m68knommu.

The script used:
TARGET=arch/m68k/include/asm
SOURCE=arch/m68knommu/include/asm

INCLUDE="cachectl.h errno.h fcntl.h hwtest.h ioctls.h ipcbuf.h \
linkage.h math-emu.h md.h mman.h movs.h msgbuf.h openprom.h \
oplib.h poll.h posix_types.h resource.h rtc.h sembuf.h shmbuf.h \
shm.h shmparam.h socket.h sockios.h spinlock.h statfs.h stat.h \
termbits.h termios.h tlb.h types.h user.h"

EQUAL="auxvec.h cputime.h device.h emergency-restart.h futex.h \
ioctl.h irq_regs.h kdebug.h local.h mutex.h percpu.h \
sections.h topology.h"

NOMUUFILES="anchor.h bootstd.h coldfire.h commproc.h dbg.h \
elia.h flat.h m5206sim.h m520xsim.h m523xsim.h m5249sim.h \
m5272sim.h m527xsim.h m528xsim.h m5307sim.h m532xsim.h \
m5407sim.h m68360_enet.h m68360.h m68360_pram.h m68360_quicc.h \
m68360_regs.h MC68328.h MC68332.h MC68EZ328.h MC68VZ328.h \
mcfcache.h mcfdma.h mcfmbus.h mcfne.h mcfpci.h mcfpit.h \
mcfsim.h mcfsmc.h mcftimer.h mcfuart.h mcfwdebug.h \
nettel.h quicc_simple.h smp.h"

FILES="atomic.h bitops.h bootinfo.h bug.h bugs.h byteorder.h cache.h \
cacheflush.h checksum.h current.h delay.h div64.h \
dma-mapping.h dma.h elf.h entry.h fb.h fpu.h hardirq.h hw_irq.h io.h \
irq.h kmap_types.h machdep.h mc146818rtc.h mmu.h mmu_context.h \
module.h page.h page_offset.h param.h pci.h pgalloc.h \
pgtable.h processor.h ptrace.h scatterlist.h segment.h \
setup.h sigcontext.h siginfo.h signal.h string.h system.h swab.h \
thread_info.h timex.h tlbflush.h traps.h uaccess.h ucontext.h \
unaligned.h unistd.h"

mergefile() {
	BASE=${1%.h}
	git mv ${SOURCE}/$1 ${TARGET}/${BASE}_no.h
	git mv ${TARGET}/$1 ${TARGET}/${BASE}_mm.h

cat << EOF > ${TARGET}/$1
EOF

	git add ${TARGET}/$1
}

set -e

mkdir -p ${TARGET}

git mv include/asm-m68k/* ${TARGET}
rmdir include/asm-m68k

git rm ${SOURCE}/Kbuild
for F in $INCLUDE $EQUAL; do
	git rm ${SOURCE}/$F
done

for F in $NOMUUFILES; do
	git mv ${SOURCE}/$F ${TARGET}/$F
done

for F in $FILES ; do
	mergefile $F
done

rmdir arch/m68knommu/include/asm
rmdir arch/m68knommu/include

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

139 files changed, 0 insertions, 15838 deletions

diff --git a/arch/m68knommu/include/asm/Kbuild b/arch/m68knommu/include/asm/Kbuild
deleted file mode 100644
index 58c02a454130..000000000000
--- a/arch/m68knommu/include/asm/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-unifdef-y += swab.h
diff --git a/arch/m68knommu/include/asm/MC68328.h b/arch/m68knommu/include/asm/MC68328.h
deleted file mode 100644
index a337e56d09bf..000000000000
--- a/arch/m68knommu/include/asm/MC68328.h
+++ /dev/null
@@ -1,1266 +0,0 @@
-
-/* include/asm-m68knommu/MC68328.h: '328 control registers
- *
- * Copyright (C) 1999  Vladimir Gurevich <vgurevic@cisco.com>
- *                     Bear & Hare Software, Inc.
- *
- * Based on include/asm-m68knommu/MC68332.h
- * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
- *
- */
-
-#ifndef _MC68328_H_
-#define _MC68328_H_
-
-#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
-#define WORD_REF(addr) (*((volatile unsigned short*)addr))
-#define LONG_REF(addr) (*((volatile unsigned long*)addr))
-
-#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
-#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
-
-/********** 
- *
- * 0xFFFFF0xx -- System Control
- *
- **********/
- 
-/*
- * System Control Register (SCR)
- */
-#define SCR_ADDR        0xfffff000
-#define SCR             BYTE_REF(SCR_ADDR)
-
-#define SCR_WDTH8       0x01    /* 8-Bit Width Select */
-#define SCR_DMAP        0x04    /* Double Map */
-#define SCR_SO          0x08    /* Supervisor Only */
-#define SCR_BETEN       0x10    /* Bus-Error Time-Out Enable */
-#define SCR_PRV         0x20    /* Privilege Violation */
-#define SCR_WPV         0x40    /* Write Protect Violation */
-#define SCR_BETO        0x80    /* Bus-Error TimeOut */
-
-/*
- * Mask Revision Register
- */
-#define MRR_ADDR 0xfffff004
-#define MRR      LONG_REF(MRR_ADDR)
- 
-/********** 
- *
- * 0xFFFFF1xx -- Chip-Select logic
- *
- **********/
-
-/********** 
- *
- * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
- *
- **********/
-
-/*
- * Group Base Address Registers
- */
-#define GRPBASEA_ADDR   0xfffff100
-#define GRPBASEB_ADDR   0xfffff102
-#define GRPBASEC_ADDR   0xfffff104
-#define GRPBASED_ADDR   0xfffff106
-
-#define GRPBASEA        WORD_REF(GRPBASEA_ADDR)
-#define GRPBASEB        WORD_REF(GRPBASEB_ADDR)
-#define GRPBASEC        WORD_REF(GRPBASEC_ADDR)
-#define GRPBASED        WORD_REF(GRPBASED_ADDR)
-
-#define GRPBASE_V         0x0001        /* Valid */
-#define GRPBASE_GBA_MASK  0xfff0        /* Group Base Address (bits 31-20) */
-
-/*
- * Group Base Address Mask Registers 
- */
-#define GRPMASKA_ADDR   0xfffff108
-#define GRPMASKB_ADDR   0xfffff10a
-#define GRPMASKC_ADDR   0xfffff10c
-#define GRPMASKD_ADDR   0xfffff10e
-
-#define GRPMASKA        WORD_REF(GRPMASKA_ADDR)
-#define GRPMASKB        WORD_REF(GRPMASKB_ADDR)
-#define GRPMASKC        WORD_REF(GRPMASKC_ADDR)
-#define GRPMASKD        WORD_REF(GRPMASKD_ADDR)
-
-#define GRMMASK_GMA_MASK 0xfffff0       /* Group Base Mask (bits 31-20) */
-
-/*
- * Chip-Select Option Registers (group A)
- */
-#define CSA0_ADDR       0xfffff110
-#define CSA1_ADDR       0xfffff114
-#define CSA2_ADDR       0xfffff118
-#define CSA3_ADDR       0xfffff11c
-
-#define CSA0            LONG_REF(CSA0_ADDR)
-#define CSA1            LONG_REF(CSA1_ADDR)
-#define CSA2            LONG_REF(CSA2_ADDR)
-#define CSA3            LONG_REF(CSA3_ADDR)
-
-#define CSA_WAIT_MASK   0x00000007      /* Wait State Selection */
-#define CSA_WAIT_SHIFT  0
-#define CSA_RO          0x00000008      /* Read-Only */
-#define CSA_AM_MASK     0x0000ff00      /* Address Mask (bits 23-16) */
-#define CSA_AM_SHIFT    8
-#define CSA_BUSW        0x00010000      /* Bus Width Select */
-#define CSA_AC_MASK     0xff000000      /* Address Compare (bits 23-16) */
-#define CSA_AC_SHIFT    24
-
-/*
- * Chip-Select Option Registers (group B)
- */
-#define CSB0_ADDR       0xfffff120
-#define CSB1_ADDR       0xfffff124
-#define CSB2_ADDR       0xfffff128
-#define CSB3_ADDR       0xfffff12c
-
-#define CSB0            LONG_REF(CSB0_ADDR)
-#define CSB1            LONG_REF(CSB1_ADDR)
-#define CSB2            LONG_REF(CSB2_ADDR)
-#define CSB3            LONG_REF(CSB3_ADDR)
-
-#define CSB_WAIT_MASK   0x00000007      /* Wait State Selection */
-#define CSB_WAIT_SHIFT  0
-#define CSB_RO          0x00000008      /* Read-Only */
-#define CSB_AM_MASK     0x0000ff00      /* Address Mask (bits 23-16) */
-#define CSB_AM_SHIFT    8
-#define CSB_BUSW        0x00010000      /* Bus Width Select */
-#define CSB_AC_MASK     0xff000000      /* Address Compare (bits 23-16) */
-#define CSB_AC_SHIFT    24
-
-/*
- * Chip-Select Option Registers (group C)
- */
-#define CSC0_ADDR       0xfffff130
-#define CSC1_ADDR       0xfffff134
-#define CSC2_ADDR       0xfffff138
-#define CSC3_ADDR       0xfffff13c
-
-#define CSC0            LONG_REF(CSC0_ADDR)
-#define CSC1            LONG_REF(CSC1_ADDR)
-#define CSC2            LONG_REF(CSC2_ADDR)
-#define CSC3            LONG_REF(CSC3_ADDR)
-
-#define CSC_WAIT_MASK   0x00000007      /* Wait State Selection */
-#define CSC_WAIT_SHIFT  0
-#define CSC_RO          0x00000008      /* Read-Only */
-#define CSC_AM_MASK     0x0000fff0      /* Address Mask (bits 23-12) */
-#define CSC_AM_SHIFT    4
-#define CSC_BUSW        0x00010000      /* Bus Width Select */
-#define CSC_AC_MASK     0xfff00000      /* Address Compare (bits 23-12) */
-#define CSC_AC_SHIFT    20
-
-/*
- * Chip-Select Option Registers (group D)
- */
-#define CSD0_ADDR       0xfffff140
-#define CSD1_ADDR       0xfffff144
-#define CSD2_ADDR       0xfffff148
-#define CSD3_ADDR       0xfffff14c
-
-#define CSD0            LONG_REF(CSD0_ADDR)
-#define CSD1            LONG_REF(CSD1_ADDR)
-#define CSD2            LONG_REF(CSD2_ADDR)
-#define CSD3            LONG_REF(CSD3_ADDR)
-
-#define CSD_WAIT_MASK   0x00000007      /* Wait State Selection */
-#define CSD_WAIT_SHIFT  0
-#define CSD_RO          0x00000008      /* Read-Only */
-#define CSD_AM_MASK     0x0000fff0      /* Address Mask (bits 23-12) */
-#define CSD_AM_SHIFT    4
-#define CSD_BUSW        0x00010000      /* Bus Width Select */
-#define CSD_AC_MASK     0xfff00000      /* Address Compare (bits 23-12) */
-#define CSD_AC_SHIFT    20
-
-/**********
- *
- * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
- *
- **********/
- 
-/*
- * PLL Control Register 
- */
-#define PLLCR_ADDR      0xfffff200
-#define PLLCR           WORD_REF(PLLCR_ADDR)
-
-#define PLLCR_DISPLL           0x0008   /* Disable PLL */
-#define PLLCR_CLKEN            0x0010   /* Clock (CLKO pin) enable */
-#define PLLCR_SYSCLK_SEL_MASK  0x0700   /* System Clock Selection */
-#define PLLCR_SYSCLK_SEL_SHIFT 8
-#define PLLCR_PIXCLK_SEL_MASK  0x3800   /* LCD Clock Selection */
-#define PLLCR_PIXCLK_SEL_SHIFT 11
-
-/* 'EZ328-compatible definitions */
-#define PLLCR_LCDCLK_SEL_MASK   PLLCR_PIXCLK_SEL_MASK
-#define PLLCR_LCDCLK_SEL_SHIFT  PLLCR_PIXCLK_SEL_SHIFT
-
-/*
- * PLL Frequency Select Register
- */
-#define PLLFSR_ADDR     0xfffff202
-#define PLLFSR          WORD_REF(PLLFSR_ADDR)
-
-#define PLLFSR_PC_MASK  0x00ff          /* P Count */
-#define PLLFSR_PC_SHIFT 0
-#define PLLFSR_QC_MASK  0x0f00          /* Q Count */
-#define PLLFSR_QC_SHIFT 8
-#define PLLFSR_PROT     0x4000          /* Protect P & Q */
-#define PLLFSR_CLK32    0x8000          /* Clock 32 (kHz) */
-
-/*
- * Power Control Register
- */
-#define PCTRL_ADDR      0xfffff207
-#define PCTRL           BYTE_REF(PCTRL_ADDR)
-
-#define PCTRL_WIDTH_MASK        0x1f    /* CPU Clock bursts width */
-#define PCTRL_WIDTH_SHIFT       0
-#define PCTRL_STOP              0x40    /* Enter power-save mode immediately */ 
-#define PCTRL_PCEN              0x80    /* Power Control Enable */
-
-/**********
- *
- * 0xFFFFF3xx -- Interrupt Controller
- *
- **********/
-
-/* 
- * Interrupt Vector Register
- */
-#define IVR_ADDR        0xfffff300
-#define IVR             BYTE_REF(IVR_ADDR)
-
-#define IVR_VECTOR_MASK 0xF8
-
-/*
- * Interrupt control Register
- */
-#define ICR_ADRR        0xfffff302
-#define ICR             WORD_REF(ICR_ADDR)
-
-#define ICR_ET6         0x0100  /* Edge Trigger Select for IRQ6 */
-#define ICR_ET3         0x0200  /* Edge Trigger Select for IRQ3 */
-#define ICR_ET2         0x0400  /* Edge Trigger Select for IRQ2 */
-#define ICR_ET1         0x0800  /* Edge Trigger Select for IRQ1 */
-#define ICR_POL6        0x1000  /* Polarity Control for IRQ6 */
-#define ICR_POL3        0x2000  /* Polarity Control for IRQ3 */
-#define ICR_POL2        0x4000  /* Polarity Control for IRQ2 */
-#define ICR_POL1        0x8000  /* Polarity Control for IRQ1 */
-
-/*
- * Interrupt Mask Register
- */
-#define IMR_ADDR        0xfffff304
-#define IMR             LONG_REF(IMR_ADDR)
- 
-/*
- * Define the names for bit positions first. This is useful for
- * request_irq
- */
-#define SPIM_IRQ_NUM    0       /* SPI Master interrupt */
-#define TMR2_IRQ_NUM    1       /* Timer 2 interrupt */
-#define UART_IRQ_NUM    2       /* UART interrupt */    
-#define WDT_IRQ_NUM     3       /* Watchdog Timer interrupt */
-#define RTC_IRQ_NUM     4       /* RTC interrupt */
-#define KB_IRQ_NUM      6       /* Keyboard Interrupt */
-#define PWM_IRQ_NUM     7       /* Pulse-Width Modulator int. */
-#define INT0_IRQ_NUM    8       /* External INT0 */
-#define INT1_IRQ_NUM    9       /* External INT1 */
-#define INT2_IRQ_NUM    10      /* External INT2 */
-#define INT3_IRQ_NUM    11      /* External INT3 */
-#define INT4_IRQ_NUM    12      /* External INT4 */
-#define INT5_IRQ_NUM    13      /* External INT5 */
-#define INT6_IRQ_NUM    14      /* External INT6 */
-#define INT7_IRQ_NUM    15      /* External INT7 */
-#define IRQ1_IRQ_NUM    16      /* IRQ1 */
-#define IRQ2_IRQ_NUM    17      /* IRQ2 */
-#define IRQ3_IRQ_NUM    18      /* IRQ3 */
-#define IRQ6_IRQ_NUM    19      /* IRQ6 */
-#define PEN_IRQ_NUM     20      /* Pen Interrupt */
-#define SPIS_IRQ_NUM    21      /* SPI Slave Interrupt */
-#define TMR1_IRQ_NUM    22      /* Timer 1 interrupt */
-#define IRQ7_IRQ_NUM    23      /* IRQ7 */
-
-/* '328-compatible definitions */
-#define SPI_IRQ_NUM     SPIM_IRQ_NUM
-#define TMR_IRQ_NUM     TMR1_IRQ_NUM
- 
-/*
- * Here go the bitmasks themselves
- */
-#define IMR_MSPIM       (1 << SPIM _IRQ_NUM)    /* Mask SPI Master interrupt */
-#define IMR_MTMR2       (1 << TMR2_IRQ_NUM)     /* Mask Timer 2 interrupt */
-#define IMR_MUART       (1 << UART_IRQ_NUM)     /* Mask UART interrupt */       
-#define IMR_MWDT        (1 << WDT_IRQ_NUM)      /* Mask Watchdog Timer interrupt */
-#define IMR_MRTC        (1 << RTC_IRQ_NUM)      /* Mask RTC interrupt */
-#define IMR_MKB         (1 << KB_IRQ_NUM)       /* Mask Keyboard Interrupt */
-#define IMR_MPWM        (1 << PWM_IRQ_NUM)      /* Mask Pulse-Width Modulator int. */
-#define IMR_MINT0       (1 << INT0_IRQ_NUM)     /* Mask External INT0 */
-#define IMR_MINT1       (1 << INT1_IRQ_NUM)     /* Mask External INT1 */
-#define IMR_MINT2       (1 << INT2_IRQ_NUM)     /* Mask External INT2 */
-#define IMR_MINT3       (1 << INT3_IRQ_NUM)     /* Mask External INT3 */
-#define IMR_MINT4       (1 << INT4_IRQ_NUM)     /* Mask External INT4 */
-#define IMR_MINT5       (1 << INT5_IRQ_NUM)     /* Mask External INT5 */
-#define IMR_MINT6       (1 << INT6_IRQ_NUM)     /* Mask External INT6 */
-#define IMR_MINT7       (1 << INT7_IRQ_NUM)     /* Mask External INT7 */
-#define IMR_MIRQ1       (1 << IRQ1_IRQ_NUM)     /* Mask IRQ1 */
-#define IMR_MIRQ2       (1 << IRQ2_IRQ_NUM)     /* Mask IRQ2 */
-#define IMR_MIRQ3       (1 << IRQ3_IRQ_NUM)     /* Mask IRQ3 */
-#define IMR_MIRQ6       (1 << IRQ6_IRQ_NUM)     /* Mask IRQ6 */
-#define IMR_MPEN        (1 << PEN_IRQ_NUM)      /* Mask Pen Interrupt */
-#define IMR_MSPIS       (1 << SPIS_IRQ_NUM)     /* Mask SPI Slave Interrupt */
-#define IMR_MTMR1       (1 << TMR1_IRQ_NUM)     /* Mask Timer 1 interrupt */
-#define IMR_MIRQ7       (1 << IRQ7_IRQ_NUM)     /* Mask IRQ7 */
-
-/* 'EZ328-compatible definitions */
-#define IMR_MSPI        IMR_MSPIM
-#define IMR_MTMR        IMR_MTMR1
-
-/* 
- * Interrupt Wake-Up Enable Register
- */
-#define IWR_ADDR        0xfffff308
-#define IWR             LONG_REF(IWR_ADDR)
-
-#define IWR_SPIM        (1 << SPIM _IRQ_NUM)    /* SPI Master interrupt */
-#define IWR_TMR2        (1 << TMR2_IRQ_NUM)     /* Timer 2 interrupt */
-#define IWR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */    
-#define IWR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
-#define IWR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
-#define IWR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
-#define IWR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator int. */
-#define IWR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
-#define IWR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
-#define IWR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
-#define IWR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
-#define IWR_INT4        (1 << INT4_IRQ_NUM)     /* External INT4 */
-#define IWR_INT5        (1 << INT5_IRQ_NUM)     /* External INT5 */
-#define IWR_INT6        (1 << INT6_IRQ_NUM)     /* External INT6 */
-#define IWR_INT7        (1 << INT7_IRQ_NUM)     /* External INT7 */
-#define IWR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
-#define IWR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
-#define IWR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
-#define IWR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
-#define IWR_PEN         (1 << PEN_IRQ_NUM)      /* Pen Interrupt */
-#define IWR_SPIS        (1 << SPIS_IRQ_NUM)     /* SPI Slave Interrupt */
-#define IWR_TMR1        (1 << TMR1_IRQ_NUM)     /* Timer 1 interrupt */
-#define IWR_IRQ7        (1 << IRQ7_IRQ_NUM)     /* IRQ7 */
-
-/* 
- * Interrupt Status Register 
- */
-#define ISR_ADDR        0xfffff30c
-#define ISR             LONG_REF(ISR_ADDR)
-
-#define ISR_SPIM        (1 << SPIM _IRQ_NUM)    /* SPI Master interrupt */
-#define ISR_TMR2        (1 << TMR2_IRQ_NUM)     /* Timer 2 interrupt */
-#define ISR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */    
-#define ISR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
-#define ISR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
-#define ISR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
-#define ISR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator int. */
-#define ISR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
-#define ISR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
-#define ISR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
-#define ISR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
-#define ISR_INT4        (1 << INT4_IRQ_NUM)     /* External INT4 */
-#define ISR_INT5        (1 << INT5_IRQ_NUM)     /* External INT5 */
-#define ISR_INT6        (1 << INT6_IRQ_NUM)     /* External INT6 */
-#define ISR_INT7        (1 << INT7_IRQ_NUM)     /* External INT7 */
-#define ISR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
-#define ISR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
-#define ISR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
-#define ISR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
-#define ISR_PEN         (1 << PEN_IRQ_NUM)      /* Pen Interrupt */
-#define ISR_SPIS        (1 << SPIS_IRQ_NUM)     /* SPI Slave Interrupt */
-#define ISR_TMR1        (1 << TMR1_IRQ_NUM)     /* Timer 1 interrupt */
-#define ISR_IRQ7        (1 << IRQ7_IRQ_NUM)     /* IRQ7 */
-
-/* 'EZ328-compatible definitions */
-#define ISR_SPI ISR_SPIM
-#define ISR_TMR ISR_TMR1
-
-/* 
- * Interrupt Pending Register 
- */
-#define IPR_ADDR        0xfffff310
-#define IPR             LONG_REF(IPR_ADDR)
-
-#define IPR_SPIM        (1 << SPIM _IRQ_NUM)    /* SPI Master interrupt */
-#define IPR_TMR2        (1 << TMR2_IRQ_NUM)     /* Timer 2 interrupt */
-#define IPR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */    
-#define IPR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
-#define IPR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
-#define IPR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
-#define IPR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator int. */
-#define IPR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
-#define IPR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
-#define IPR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
-#define IPR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
-#define IPR_INT4        (1 << INT4_IRQ_NUM)     /* External INT4 */
-#define IPR_INT5        (1 << INT5_IRQ_NUM)     /* External INT5 */
-#define IPR_INT6        (1 << INT6_IRQ_NUM)     /* External INT6 */
-#define IPR_INT7        (1 << INT7_IRQ_NUM)     /* External INT7 */
-#define IPR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
-#define IPR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
-#define IPR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
-#define IPR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
-#define IPR_PEN         (1 << PEN_IRQ_NUM)      /* Pen Interrupt */
-#define IPR_SPIS        (1 << SPIS_IRQ_NUM)     /* SPI Slave Interrupt */
-#define IPR_TMR1        (1 << TMR1_IRQ_NUM)     /* Timer 1 interrupt */
-#define IPR_IRQ7        (1 << IRQ7_IRQ_NUM)     /* IRQ7 */
-
-/* 'EZ328-compatible definitions */
-#define IPR_SPI IPR_SPIM
-#define IPR_TMR IPR_TMR1
-
-/**********
- *
- * 0xFFFFF4xx -- Parallel Ports
- *
- **********/
-
-/*
- * Port A
- */
-#define PADIR_ADDR      0xfffff400              /* Port A direction reg */
-#define PADATA_ADDR     0xfffff401              /* Port A data register */
-#define PASEL_ADDR      0xfffff403              /* Port A Select register */
-
-#define PADIR           BYTE_REF(PADIR_ADDR)
-#define PADATA          BYTE_REF(PADATA_ADDR)
-#define PASEL           BYTE_REF(PASEL_ADDR)
-
-#define PA(x)           (1 << (x))
-#define PA_A(x)         PA((x) - 16)    /* This is specific to PA only! */
-
-#define PA_A16          PA(0)           /* Use A16 as PA(0) */
-#define PA_A17          PA(1)           /* Use A17 as PA(1) */
-#define PA_A18          PA(2)           /* Use A18 as PA(2) */
-#define PA_A19          PA(3)           /* Use A19 as PA(3) */
-#define PA_A20          PA(4)           /* Use A20 as PA(4) */
-#define PA_A21          PA(5)           /* Use A21 as PA(5) */
-#define PA_A22          PA(6)           /* Use A22 as PA(6) */
-#define PA_A23          PA(7)           /* Use A23 as PA(7) */
-
-/* 
- * Port B
- */
-#define PBDIR_ADDR      0xfffff408              /* Port B direction reg */
-#define PBDATA_ADDR     0xfffff409              /* Port B data register */
-#define PBSEL_ADDR      0xfffff40b              /* Port B Select Register */
-
-#define PBDIR           BYTE_REF(PBDIR_ADDR)
-#define PBDATA          BYTE_REF(PBDATA_ADDR)
-#define PBSEL           BYTE_REF(PBSEL_ADDR)
-
-#define PB(x)           (1 << (x))
-#define PB_D(x)         PB(x)           /* This is specific to port B only */
-
-#define PB_D0           PB(0)           /* Use D0 as PB(0) */
-#define PB_D1           PB(1)           /* Use D1 as PB(1) */
-#define PB_D2           PB(2)           /* Use D2 as PB(2) */
-#define PB_D3           PB(3)           /* Use D3 as PB(3) */
-#define PB_D4           PB(4)           /* Use D4 as PB(4) */
-#define PB_D5           PB(5)           /* Use D5 as PB(5) */
-#define PB_D6           PB(6)           /* Use D6 as PB(6) */
-#define PB_D7           PB(7)           /* Use D7 as PB(7) */
-
-/* 
- * Port C
- */
-#define PCDIR_ADDR      0xfffff410              /* Port C direction reg */
-#define PCDATA_ADDR     0xfffff411              /* Port C data register */
-#define PCSEL_ADDR      0xfffff413              /* Port C Select Register */
-
-#define PCDIR           BYTE_REF(PCDIR_ADDR)
-#define PCDATA          BYTE_REF(PCDATA_ADDR)
-#define PCSEL           BYTE_REF(PCSEL_ADDR)
-
-#define PC(x)           (1 << (x))
-
-#define PC_WE           PC(6)           /* Use WE    as PC(6) */
-#define PC_DTACK        PC(5)           /* Use DTACK as PC(5) */
-#define PC_IRQ7         PC(4)           /* Use IRQ7  as PC(4) */
-#define PC_LDS          PC(2)           /* Use LDS   as PC(2) */
-#define PC_UDS          PC(1)           /* Use UDS   as PC(1) */
-#define PC_MOCLK        PC(0)           /* Use MOCLK as PC(0) */
-
-/* 
- * Port D
- */
-#define PDDIR_ADDR      0xfffff418              /* Port D direction reg */
-#define PDDATA_ADDR     0xfffff419              /* Port D data register */
-#define PDPUEN_ADDR     0xfffff41a              /* Port D Pull-Up enable reg */
-#define PDPOL_ADDR      0xfffff41c              /* Port D Polarity Register */
-#define PDIRQEN_ADDR    0xfffff41d              /* Port D IRQ enable register */
-#define PDIQEG_ADDR     0xfffff41f              /* Port D IRQ Edge Register */
-
-#define PDDIR           BYTE_REF(PDDIR_ADDR)
-#define PDDATA          BYTE_REF(PDDATA_ADDR)
-#define PDPUEN          BYTE_REF(PDPUEN_ADDR)
-#define PDPOL           BYTE_REF(PDPOL_ADDR)
-#define PDIRQEN         BYTE_REF(PDIRQEN_ADDR)
-#define PDIQEG          BYTE_REF(PDIQEG_ADDR)
-
-#define PD(x)           (1 << (x))
-#define PD_KB(x)        PD(x)           /* This is specific for Port D only */
-
-#define PD_KB0          PD(0)   /* Use KB0 as PD(0) */
-#define PD_KB1          PD(1)   /* Use KB1 as PD(1) */
-#define PD_KB2          PD(2)   /* Use KB2 as PD(2) */
-#define PD_KB3          PD(3)   /* Use KB3 as PD(3) */
-#define PD_KB4          PD(4)   /* Use KB4 as PD(4) */
-#define PD_KB5          PD(5)   /* Use KB5 as PD(5) */
-#define PD_KB6          PD(6)   /* Use KB6 as PD(6) */
-#define PD_KB7          PD(7)   /* Use KB7 as PD(7) */
-
-/* 
- * Port E
- */
-#define PEDIR_ADDR      0xfffff420              /* Port E direction reg */
-#define PEDATA_ADDR     0xfffff421              /* Port E data register */
-#define PEPUEN_ADDR     0xfffff422              /* Port E Pull-Up enable reg */
-#define PESEL_ADDR      0xfffff423              /* Port E Select Register */
-
-#define PEDIR           BYTE_REF(PEDIR_ADDR)
-#define PEDATA          BYTE_REF(PEDATA_ADDR)
-#define PEPUEN          BYTE_REF(PEPUEN_ADDR)
-#define PESEL           BYTE_REF(PESEL_ADDR)
-
-#define PE(x)           (1 << (x))
-
-#define PE_CSA1         PE(1)   /* Use CSA1 as PE(1) */
-#define PE_CSA2         PE(2)   /* Use CSA2 as PE(2) */
-#define PE_CSA3         PE(3)   /* Use CSA3 as PE(3) */
-#define PE_CSB0         PE(4)   /* Use CSB0 as PE(4) */
-#define PE_CSB1         PE(5)   /* Use CSB1 as PE(5) */
-#define PE_CSB2         PE(6)   /* Use CSB2 as PE(6) */
-#define PE_CSB3         PE(7)   /* Use CSB3 as PE(7) */
-
-/* 
- * Port F
- */
-#define PFDIR_ADDR      0xfffff428              /* Port F direction reg */
-#define PFDATA_ADDR     0xfffff429              /* Port F data register */
-#define PFPUEN_ADDR     0xfffff42a              /* Port F Pull-Up enable reg */
-#define PFSEL_ADDR      0xfffff42b              /* Port F Select Register */
-
-#define PFDIR           BYTE_REF(PFDIR_ADDR)
-#define PFDATA          BYTE_REF(PFDATA_ADDR)
-#define PFPUEN          BYTE_REF(PFPUEN_ADDR)
-#define PFSEL           BYTE_REF(PFSEL_ADDR)
-
-#define PF(x)           (1 << (x))
-#define PF_A(x)         PF((x) - 24)    /* This is Port F specific only */
-
-#define PF_A24          PF(0)   /* Use A24 as PF(0) */
-#define PF_A25          PF(1)   /* Use A25 as PF(1) */
-#define PF_A26          PF(2)   /* Use A26 as PF(2) */
-#define PF_A27          PF(3)   /* Use A27 as PF(3) */
-#define PF_A28          PF(4)   /* Use A28 as PF(4) */
-#define PF_A29          PF(5)   /* Use A29 as PF(5) */
-#define PF_A30          PF(6)   /* Use A30 as PF(6) */
-#define PF_A31          PF(7)   /* Use A31 as PF(7) */
-
-/* 
- * Port G
- */
-#define PGDIR_ADDR      0xfffff430              /* Port G direction reg */
-#define PGDATA_ADDR     0xfffff431              /* Port G data register */
-#define PGPUEN_ADDR     0xfffff432              /* Port G Pull-Up enable reg */
-#define PGSEL_ADDR      0xfffff433              /* Port G Select Register */
-
-#define PGDIR           BYTE_REF(PGDIR_ADDR)
-#define PGDATA          BYTE_REF(PGDATA_ADDR)
-#define PGPUEN          BYTE_REF(PGPUEN_ADDR)
-#define PGSEL           BYTE_REF(PGSEL_ADDR)
-
-#define PG(x)           (1 << (x))
-
-#define PG_UART_TXD     PG(0)   /* Use UART_TXD as PG(0) */
-#define PG_UART_RXD     PG(1)   /* Use UART_RXD as PG(1) */
-#define PG_PWMOUT       PG(2)   /* Use PWMOUT   as PG(2) */
-#define PG_TOUT2        PG(3)   /* Use TOUT2    as PG(3) */
-#define PG_TIN2         PG(4)   /* Use TIN2     as PG(4) */
-#define PG_TOUT1        PG(5)   /* Use TOUT1    as PG(5) */
-#define PG_TIN1         PG(6)   /* Use TIN1     as PG(6) */
-#define PG_RTCOUT       PG(7)   /* Use RTCOUT   as PG(7) */
-
-/* 
- * Port J
- */
-#define PJDIR_ADDR      0xfffff438              /* Port J direction reg */
-#define PJDATA_ADDR     0xfffff439              /* Port J data register */
-#define PJSEL_ADDR      0xfffff43b              /* Port J Select Register */
-
-#define PJDIR           BYTE_REF(PJDIR_ADDR)
-#define PJDATA          BYTE_REF(PJDATA_ADDR)
-#define PJSEL           BYTE_REF(PJSEL_ADDR)
-
-#define PJ(x)           (1 << (x)) 
-
-#define PJ_CSD3         PJ(7)   /* Use CSD3 as PJ(7) */
-
-/* 
- * Port K
- */
-#define PKDIR_ADDR      0xfffff440              /* Port K direction reg */
-#define PKDATA_ADDR     0xfffff441              /* Port K data register */
-#define PKPUEN_ADDR     0xfffff442              /* Port K Pull-Up enable reg */
-#define PKSEL_ADDR      0xfffff443              /* Port K Select Register */
-
-#define PKDIR           BYTE_REF(PKDIR_ADDR)
-#define PKDATA          BYTE_REF(PKDATA_ADDR)
-#define PKPUEN          BYTE_REF(PKPUEN_ADDR)
-#define PKSEL           BYTE_REF(PKSEL_ADDR)
-
-#define PK(x)           (1 << (x))
-
-/* 
- * Port M
- */
-#define PMDIR_ADDR      0xfffff438              /* Port M direction reg */
-#define PMDATA_ADDR     0xfffff439              /* Port M data register */
-#define PMPUEN_ADDR     0xfffff43a              /* Port M Pull-Up enable reg */
-#define PMSEL_ADDR      0xfffff43b              /* Port M Select Register */
-
-#define PMDIR           BYTE_REF(PMDIR_ADDR)
-#define PMDATA          BYTE_REF(PMDATA_ADDR)
-#define PMPUEN          BYTE_REF(PMPUEN_ADDR)
-#define PMSEL           BYTE_REF(PMSEL_ADDR)
-
-#define PM(x)           (1 << (x))
-
-/**********
- *
- * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
- *
- **********/
-
-/*
- * PWM Control Register 
- */
-#define PWMC_ADDR       0xfffff500
-#define PWMC            WORD_REF(PWMC_ADDR)
-
-#define PWMC_CLKSEL_MASK        0x0007  /* Clock Selection */
-#define PWMC_CLKSEL_SHIFT       0
-#define PWMC_PWMEN              0x0010  /* Enable PWM */
-#define PMNC_POL                0x0020  /* PWM Output Bit Polarity */
-#define PWMC_PIN                0x0080  /* Current PWM output pin status */
-#define PWMC_LOAD               0x0100  /* Force a new period */
-#define PWMC_IRQEN              0x4000  /* Interrupt Request Enable */
-#define PWMC_CLKSRC             0x8000  /* Clock Source Select */
-
-/* 'EZ328-compatible definitions */
-#define PWMC_EN PWMC_PWMEN
-
-/*
- * PWM Period Register
- */
-#define PWMP_ADDR       0xfffff502
-#define PWMP            WORD_REF(PWMP_ADDR)
-
-/* 
- * PWM Width Register 
- */
-#define PWMW_ADDR       0xfffff504
-#define PWMW            WORD_REF(PWMW_ADDR)
-
-/*
- * PWM Counter Register
- */
-#define PWMCNT_ADDR     0xfffff506
-#define PWMCNT          WORD_REF(PWMCNT_ADDR)
-
-/**********
- *
- * 0xFFFFF6xx -- General-Purpose Timers
- *
- **********/
-
-/* 
- * Timer Unit 1 and 2 Control Registers
- */
-#define TCTL1_ADDR      0xfffff600
-#define TCTL1           WORD_REF(TCTL1_ADDR)
-#define TCTL2_ADDR      0xfffff60c
-#define TCTL2           WORD_REF(TCTL2_ADDR)
-
-#define TCTL_TEN                0x0001  /* Timer Enable  */
-#define TCTL_CLKSOURCE_MASK     0x000e  /* Clock Source: */
-#define   TCTL_CLKSOURCE_STOP      0x0000       /* Stop count (disabled)    */
-#define   TCTL_CLKSOURCE_SYSCLK    0x0002       /* SYSCLK to prescaler      */
-#define   TCTL_CLKSOURCE_SYSCLK_16 0x0004       /* SYSCLK/16 to prescaler   */
-#define   TCTL_CLKSOURCE_TIN       0x0006       /* TIN to prescaler         */
-#define   TCTL_CLKSOURCE_32KHZ     0x0008       /* 32kHz clock to prescaler */
-#define TCTL_IRQEN              0x0010  /* IRQ Enable    */
-#define TCTL_OM                 0x0020  /* Output Mode   */
-#define TCTL_CAP_MASK           0x00c0  /* Capture Edge: */
-#define   TCTL_CAP_RE           0x0040          /* Capture on rizing edge   */
-#define   TCTL_CAP_FE           0x0080          /* Capture on falling edge  */
-#define TCTL_FRR                0x0010  /* Free-Run Mode */
-
-/* 'EZ328-compatible definitions */
-#define TCTL_ADDR       TCTL1_ADDR
-#define TCTL            TCTL1
-
-/*
- * Timer Unit 1 and 2 Prescaler Registers
- */
-#define TPRER1_ADDR     0xfffff602
-#define TPRER1          WORD_REF(TPRER1_ADDR)
-#define TPRER2_ADDR     0xfffff60e
-#define TPRER2          WORD_REF(TPRER2_ADDR)
-
-/* 'EZ328-compatible definitions */
-#define TPRER_ADDR      TPRER1_ADDR
-#define TPRER           TPRER1
-
-/*
- * Timer Unit 1 and 2 Compare Registers
- */
-#define TCMP1_ADDR      0xfffff604
-#define TCMP1           WORD_REF(TCMP1_ADDR)
-#define TCMP2_ADDR      0xfffff610
-#define TCMP2           WORD_REF(TCMP2_ADDR)
-
-/* 'EZ328-compatible definitions */
-#define TCMP_ADDR       TCMP1_ADDR
-#define TCMP            TCMP1
-
-/*
- * Timer Unit 1 and 2 Capture Registers
- */
-#define TCR1_ADDR       0xfffff606
-#define TCR1            WORD_REF(TCR1_ADDR)
-#define TCR2_ADDR       0xfffff612
-#define TCR2            WORD_REF(TCR2_ADDR)
-
-/* 'EZ328-compatible definitions */
-#define TCR_ADDR        TCR1_ADDR
-#define TCR             TCR1
-
-/*
- * Timer Unit 1 and 2 Counter Registers
- */
-#define TCN1_ADDR       0xfffff608
-#define TCN1            WORD_REF(TCN1_ADDR)
-#define TCN2_ADDR       0xfffff614
-#define TCN2            WORD_REF(TCN2_ADDR)
-
-/* 'EZ328-compatible definitions */
-#define TCN_ADDR        TCN1_ADDR
-#define TCN             TCN
-
-/*
- * Timer Unit 1 and 2 Status Registers
- */
-#define TSTAT1_ADDR     0xfffff60a
-#define TSTAT1          WORD_REF(TSTAT1_ADDR)
-#define TSTAT2_ADDR     0xfffff616
-#define TSTAT2          WORD_REF(TSTAT2_ADDR)
-
-#define TSTAT_COMP      0x0001          /* Compare Event occurred */
-#define TSTAT_CAPT      0x0001          /* Capture Event occurred */
-
-/* 'EZ328-compatible definitions */
-#define TSTAT_ADDR      TSTAT1_ADDR
-#define TSTAT           TSTAT1
-
-/*
- * Watchdog Compare Register 
- */
-#define WRR_ADDR        0xfffff61a
-#define WRR             WORD_REF(WRR_ADDR)
-
-/*
- * Watchdog Counter Register 
- */
-#define WCN_ADDR        0xfffff61c
-#define WCN             WORD_REF(WCN_ADDR)
-
-/*
- * Watchdog Control and Status Register
- */
-#define WCSR_ADDR       0xfffff618
-#define WCSR            WORD_REF(WCSR_ADDR)
-
-#define WCSR_WDEN       0x0001  /* Watchdog Enable */
-#define WCSR_FI         0x0002  /* Forced Interrupt (instead of SW reset)*/
-#define WCSR_WRST       0x0004  /* Watchdog Reset */
-
-/**********
- *
- * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
- *
- **********/
-
-/*
- * SPI Slave Register
- */
-#define SPISR_ADDR      0xfffff700
-#define SPISR           WORD_REF(SPISR_ADDR)
-
-#define SPISR_DATA_ADDR 0xfffff701
-#define SPISR_DATA      BYTE_REF(SPISR_DATA_ADDR)
-
-#define SPISR_DATA_MASK  0x00ff /* Shifted data from the external device */
-#define SPISR_DATA_SHIFT 0
-#define SPISR_SPISEN     0x0100 /* SPIS module enable */
-#define SPISR_POL        0x0200 /* SPSCLK polarity control */
-#define SPISR_PHA        0x0400 /* Phase relationship between SPSCLK & SPSRxD */
-#define SPISR_OVWR       0x0800 /* Data buffer has been overwritten */
-#define SPISR_DATARDY    0x1000 /* Data ready */
-#define SPISR_ENPOL      0x2000 /* Enable Polarity */
-#define SPISR_IRQEN      0x4000 /* SPIS IRQ Enable */
-#define SPISR_SPISIRQ    0x8000 /* SPIS IRQ posted */
-
-/**********
- *
- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
- *
- **********/
-
-/*
- * SPIM Data Register
- */
-#define SPIMDATA_ADDR   0xfffff800
-#define SPIMDATA        WORD_REF(SPIMDATA_ADDR)
-
-/*
- * SPIM Control/Status Register
- */
-#define SPIMCONT_ADDR   0xfffff802
-#define SPIMCONT        WORD_REF(SPIMCONT_ADDR)
-
-#define SPIMCONT_BIT_COUNT_MASK  0x000f /* Transfer Length in Bytes */
-#define SPIMCONT_BIT_COUNT_SHIFT 0
-#define SPIMCONT_POL             0x0010 /* SPMCLK Signel Polarity */
-#define SPIMCONT_PHA             0x0020 /* Clock/Data phase relationship */
-#define SPIMCONT_IRQEN           0x0040 /* IRQ Enable */
-#define SPIMCONT_SPIMIRQ         0x0080 /* Interrupt Request */
-#define SPIMCONT_XCH             0x0100 /* Exchange */
-#define SPIMCONT_RSPIMEN         0x0200 /* Enable SPIM */
-#define SPIMCONT_DATA_RATE_MASK  0xe000 /* SPIM Data Rate */
-#define SPIMCONT_DATA_RATE_SHIFT 13
-
-/* 'EZ328-compatible definitions */
-#define SPIMCONT_IRQ    SPIMCONT_SPIMIRQ
-#define SPIMCONT_ENABLE SPIMCONT_SPIMEN
-/**********
- *
- * 0xFFFFF9xx -- UART
- *
- **********/
-
-/*
- * UART Status/Control Register
- */
-#define USTCNT_ADDR     0xfffff900
-#define USTCNT          WORD_REF(USTCNT_ADDR)
-
-#define USTCNT_TXAVAILEN        0x0001  /* Transmitter Available Int Enable */
-#define USTCNT_TXHALFEN         0x0002  /* Transmitter Half Empty Int Enable */
-#define USTCNT_TXEMPTYEN        0x0004  /* Transmitter Empty Int Enable */
-#define USTCNT_RXREADYEN        0x0008  /* Receiver Ready Interrupt Enable */
-#define USTCNT_RXHALFEN         0x0010  /* Receiver Half-Full Int Enable */
-#define USTCNT_RXFULLEN         0x0020  /* Receiver Full Interrupt Enable */
-#define USTCNT_CTSDELTAEN       0x0040  /* CTS Delta Interrupt Enable */
-#define USTCNT_GPIODELTAEN      0x0080  /* Old Data Interrupt Enable */
-#define USTCNT_8_7              0x0100  /* Eight or seven-bit transmission */
-#define USTCNT_STOP             0x0200  /* Stop bit transmission */
-#define USTCNT_ODD_EVEN         0x0400  /* Odd Parity */
-#define USTCNT_PARITYEN         0x0800  /* Parity Enable */
-#define USTCNT_CLKMODE          0x1000  /* Clock Mode Select */
-#define USTCNT_TXEN             0x2000  /* Transmitter Enable */
-#define USTCNT_RXEN             0x4000  /* Receiver Enable */
-#define USTCNT_UARTEN           0x8000  /* UART Enable */
-
-/* 'EZ328-compatible definitions */
-#define USTCNT_TXAE     USTCNT_TXAVAILEN 
-#define USTCNT_TXHE     USTCNT_TXHALFEN
-#define USTCNT_TXEE     USTCNT_TXEMPTYEN
-#define USTCNT_RXRE     USTCNT_RXREADYEN
-#define USTCNT_RXHE     USTCNT_RXHALFEN
-#define USTCNT_RXFE     USTCNT_RXFULLEN
-#define USTCNT_CTSD     USTCNT_CTSDELTAEN
-#define USTCNT_ODD      USTCNT_ODD_EVEN
-#define USTCNT_PEN      USTCNT_PARITYEN
-#define USTCNT_CLKM     USTCNT_CLKMODE
-#define USTCNT_UEN      USTCNT_UARTEN
-
-/*
- * UART Baud Control Register
- */
-#define UBAUD_ADDR      0xfffff902
-#define UBAUD           WORD_REF(UBAUD_ADDR)
-
-#define UBAUD_PRESCALER_MASK    0x003f  /* Actual divisor is 65 - PRESCALER */
-#define UBAUD_PRESCALER_SHIFT   0
-#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divizor */
-#define UBAUD_DIVIDE_SHIFT      8
-#define UBAUD_BAUD_SRC          0x0800  /* Baud Rate Source */
-#define UBAUD_GPIOSRC           0x1000  /* GPIO source */
-#define UBAUD_GPIODIR           0x2000  /* GPIO Direction */
-#define UBAUD_GPIO              0x4000  /* Current GPIO pin status */
-#define UBAUD_GPIODELTA         0x8000  /* GPIO pin value changed */
-
-/*
- * UART Receiver Register 
- */
-#define URX_ADDR        0xfffff904
-#define URX             WORD_REF(URX_ADDR)
-
-#define URX_RXDATA_ADDR 0xfffff905
-#define URX_RXDATA      BYTE_REF(URX_RXDATA_ADDR)
-
-#define URX_RXDATA_MASK  0x00ff /* Received data */
-#define URX_RXDATA_SHIFT 0
-#define URX_PARITY_ERROR 0x0100 /* Parity Error */
-#define URX_BREAK        0x0200 /* Break Detected */
-#define URX_FRAME_ERROR  0x0400 /* Framing Error */
-#define URX_OVRUN        0x0800 /* Serial Overrun */
-#define URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */
-#define URX_FIFO_HALF    0x4000 /* FIFO is Half-Full */
-#define URX_FIFO_FULL    0x8000 /* FIFO is Full */
-
-/*
- * UART Transmitter Register 
- */
-#define UTX_ADDR        0xfffff906
-#define UTX             WORD_REF(UTX_ADDR)
-
-#define UTX_TXDATA_ADDR 0xfffff907
-#define UTX_TXDATA      BYTE_REF(UTX_TXDATA_ADDR)
-
-#define UTX_TXDATA_MASK  0x00ff /* Data to be transmitted */
-#define UTX_TXDATA_SHIFT 0
-#define UTX_CTS_DELTA    0x0100 /* CTS changed */
-#define UTX_CTS_STATUS   0x0200 /* CTS State */
-#define UTX_IGNORE_CTS   0x0800 /* Ignore CTS */
-#define UTX_SEND_BREAK   0x1000 /* Send a BREAK */
-#define UTX_TX_AVAIL     0x2000 /* Transmit FIFO has a slot available */
-#define UTX_FIFO_HALF    0x4000 /* Transmit FIFO is half empty */
-#define UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */
-
-/* 'EZ328-compatible definitions */
-#define UTX_CTS_STAT    UTX_CTS_STATUS
-#define UTX_NOCTS       UTX_IGNORE_CTS
-
-/*
- * UART Miscellaneous Register 
- */
-#define UMISC_ADDR      0xfffff908
-#define UMISC           WORD_REF(UMISC_ADDR)
-
-#define UMISC_TX_POL     0x0004 /* Transmit Polarity */
-#define UMISC_RX_POL     0x0008 /* Receive Polarity */
-#define UMISC_IRDA_LOOP  0x0010 /* IrDA Loopback Enable */
-#define UMISC_IRDA_EN    0x0020 /* Infra-Red Enable */
-#define UMISC_RTS        0x0040 /* Set RTS status */
-#define UMISC_RTSCONT    0x0080 /* Choose RTS control */
-#define UMISC_LOOP       0x1000 /* Serial Loopback Enable */
-#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
-#define UMISC_CLKSRC     0x4000 /* Clock Source */
-
-
-/* generalization of uart control registers to support multiple ports: */
-typedef volatile struct {
-  volatile unsigned short int ustcnt;
-  volatile unsigned short int ubaud;
-  union {
-    volatile unsigned short int w;
-    struct {
-      volatile unsigned char status;
-      volatile unsigned char rxdata;
-    } b;
-  } urx;
-  union {
-    volatile unsigned short int w;
-    struct {
-      volatile unsigned char status;
-      volatile unsigned char txdata;
-    } b;
-  } utx;
-  volatile unsigned short int umisc;
-  volatile unsigned short int pad1;
-  volatile unsigned short int pad2;
-  volatile unsigned short int pad3;
-} __attribute__((packed)) m68328_uart;
-
-
-/**********
- *
- * 0xFFFFFAxx -- LCD Controller
- *
- **********/
-
-/*
- * LCD Screen Starting Address Register 
- */
-#define LSSA_ADDR       0xfffffa00
-#define LSSA            LONG_REF(LSSA_ADDR)
-
-#define LSSA_SSA_MASK   0xfffffffe      /* Bit 0 is reserved */
-
-/*
- * LCD Virtual Page Width Register 
- */
-#define LVPW_ADDR       0xfffffa05
-#define LVPW            BYTE_REF(LVPW_ADDR)
-
-/*
- * LCD Screen Width Register (not compatible with 'EZ328 !!!)
- */
-#define LXMAX_ADDR      0xfffffa08
-#define LXMAX           WORD_REF(LXMAX_ADDR)
-
-#define LXMAX_XM_MASK   0x02ff          /* Bits 0-3 are reserved */
-
-/*
- * LCD Screen Height Register
- */
-#define LYMAX_ADDR      0xfffffa0a
-#define LYMAX           WORD_REF(LYMAX_ADDR)
-
-#define LYMAX_YM_MASK   0x02ff          /* Bits 10-15 are reserved */
-
-/*
- * LCD Cursor X Position Register
- */
-#define LCXP_ADDR       0xfffffa18
-#define LCXP            WORD_REF(LCXP_ADDR)
-
-#define LCXP_CC_MASK    0xc000          /* Cursor Control */
-#define   LCXP_CC_TRAMSPARENT   0x0000
-#define   LCXP_CC_BLACK         0x4000
-#define   LCXP_CC_REVERSED      0x8000
-#define   LCXP_CC_WHITE         0xc000
-#define LCXP_CXP_MASK   0x02ff          /* Cursor X position */
-
-/*
- * LCD Cursor Y Position Register
- */
-#define LCYP_ADDR       0xfffffa1a
-#define LCYP            WORD_REF(LCYP_ADDR)
-
-#define LCYP_CYP_MASK   0x01ff          /* Cursor Y Position */
-
-/*
- * LCD Cursor Width and Heigth Register
- */
-#define LCWCH_ADDR      0xfffffa1c
-#define LCWCH           WORD_REF(LCWCH_ADDR)
-
-#define LCWCH_CH_MASK   0x001f          /* Cursor Height */
-#define LCWCH_CH_SHIFT  0
-#define LCWCH_CW_MASK   0x1f00          /* Cursor Width */
-#define LCWCH_CW_SHIFT  8
-
-/*
- * LCD Blink Control Register
- */
-#define LBLKC_ADDR      0xfffffa1f
-#define LBLKC           BYTE_REF(LBLKC_ADDR)
-
-#define LBLKC_BD_MASK   0x7f    /* Blink Divisor */
-#define LBLKC_BD_SHIFT  0
-#define LBLKC_BKEN      0x80    /* Blink Enabled */
-
-/*
- * LCD Panel Interface Configuration Register 
- */
-#define LPICF_ADDR      0xfffffa20
-#define LPICF           BYTE_REF(LPICF_ADDR)
-
-#define LPICF_GS_MASK    0x01    /* Gray-Scale Mode */
-#define   LPICF_GS_BW      0x00
-#define   LPICF_GS_GRAY_4  0x01
-#define LPICF_PBSIZ_MASK 0x06   /* Panel Bus Width */
-#define   LPICF_PBSIZ_1    0x00
-#define   LPICF_PBSIZ_2    0x02
-#define   LPICF_PBSIZ_4    0x04
-
-/*
- * LCD Polarity Configuration Register 
- */
-#define LPOLCF_ADDR     0xfffffa21
-#define LPOLCF          BYTE_REF(LPOLCF_ADDR)
-
-#define LPOLCF_PIXPOL   0x01    /* Pixel Polarity */
-#define LPOLCF_LPPOL    0x02    /* Line Pulse Polarity */
-#define LPOLCF_FLMPOL   0x04    /* Frame Marker Polarity */
-#define LPOLCF_LCKPOL   0x08    /* LCD Shift Lock Polarity */
-
-/*
- * LACD (LCD Alternate Crystal Direction) Rate Control Register
- */
-#define LACDRC_ADDR     0xfffffa23
-#define LACDRC          BYTE_REF(LACDRC_ADDR)
-
-#define LACDRC_ACD_MASK  0x0f   /* Alternate Crystal Direction Control */
-#define LACDRC_ACD_SHIFT 0
-
-/*
- * LCD Pixel Clock Divider Register
- */
-#define LPXCD_ADDR      0xfffffa25
-#define LPXCD           BYTE_REF(LPXCD_ADDR)
-
-#define LPXCD_PCD_MASK  0x3f    /* Pixel Clock Divider */
-#define LPXCD_PCD_SHIFT 0
-
-/*
- * LCD Clocking Control Register
- */
-#define LCKCON_ADDR     0xfffffa27
-#define LCKCON          BYTE_REF(LCKCON_ADDR)
-
-#define LCKCON_PCDS      0x01   /* Pixel Clock Divider Source Select */
-#define LCKCON_DWIDTH    0x02   /* Display Memory Width  */
-#define LCKCON_DWS_MASK  0x3c   /* Display Wait-State */
-#define LCKCON_DWS_SHIFT 2
-#define LCKCON_DMA16     0x40   /* DMA burst length */
-#define LCKCON_LCDON     0x80   /* Enable LCD Controller */
-
-/* 'EZ328-compatible definitions */
-#define LCKCON_DW_MASK  LCKCON_DWS_MASK
-#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
-
-/*
- * LCD Last Buffer Address Register
- */
-#define LLBAR_ADDR      0xfffffa29
-#define LLBAR           BYTE_REF(LLBAR_ADDR)
-
-#define LLBAR_LBAR_MASK  0x7f   /* Number of memory words to fill 1 line */
-#define LLBAR_LBAR_SHIFT 0
-
-/*
- * LCD Octet Terminal Count Register 
- */
-#define LOTCR_ADDR      0xfffffa2b
-#define LOTCR           BYTE_REF(LOTCR_ADDR)
-
-/*
- * LCD Panning Offset Register
- */
-#define LPOSR_ADDR      0xfffffa2d
-#define LPOSR           BYTE_REF(LPOSR_ADDR)
-
-#define LPOSR_BOS       0x08    /* Byte offset (for B/W mode only */
-#define LPOSR_POS_MASK  0x07    /* Pixel Offset Code */
-#define LPOSR_POS_SHIFT 0
-
-/*
- * LCD Frame Rate Control Modulation Register
- */
-#define LFRCM_ADDR      0xfffffa31
-#define LFRCM           BYTE_REF(LFRCM_ADDR)
-
-#define LFRCM_YMOD_MASK  0x0f   /* Vertical Modulation */
-#define LFRCM_YMOD_SHIFT 0
-#define LFRCM_XMOD_MASK  0xf0   /* Horizontal Modulation */
-#define LFRCM_XMOD_SHIFT 4
-
-/*
- * LCD Gray Palette Mapping Register
- */
-#define LGPMR_ADDR      0xfffffa32
-#define LGPMR           WORD_REF(LGPMR_ADDR)
-
-#define LGPMR_GLEVEL3_MASK      0x000f
-#define LGPMR_GLEVEL3_SHIFT     0 
-#define LGPMR_GLEVEL2_MASK      0x00f0
-#define LGPMR_GLEVEL2_SHIFT     4 
-#define LGPMR_GLEVEL0_MASK      0x0f00
-#define LGPMR_GLEVEL0_SHIFT     8 
-#define LGPMR_GLEVEL1_MASK      0xf000
-#define LGPMR_GLEVEL1_SHIFT     12
-
-/**********
- *
- * 0xFFFFFBxx -- Real-Time Clock (RTC)
- *
- **********/
-
-/*
- * RTC Hours Minutes and Seconds Register
- */
-#define RTCTIME_ADDR    0xfffffb00
-#define RTCTIME         LONG_REF(RTCTIME_ADDR)
-
-#define RTCTIME_SECONDS_MASK    0x0000003f      /* Seconds */
-#define RTCTIME_SECONDS_SHIFT   0
-#define RTCTIME_MINUTES_MASK    0x003f0000      /* Minutes */
-#define RTCTIME_MINUTES_SHIFT   16
-#define RTCTIME_HOURS_MASK      0x1f000000      /* Hours */
-#define RTCTIME_HOURS_SHIFT     24
-
-/*
- *  RTC Alarm Register 
- */
-#define RTCALRM_ADDR    0xfffffb04
-#define RTCALRM         LONG_REF(RTCALRM_ADDR)
-
-#define RTCALRM_SECONDS_MASK    0x0000003f      /* Seconds */
-#define RTCALRM_SECONDS_SHIFT   0
-#define RTCALRM_MINUTES_MASK    0x003f0000      /* Minutes */
-#define RTCALRM_MINUTES_SHIFT   16
-#define RTCALRM_HOURS_MASK      0x1f000000      /* Hours */
-#define RTCALRM_HOURS_SHIFT     24
-
-/*
- * RTC Control Register
- */
-#define RTCCTL_ADDR     0xfffffb0c
-#define RTCCTL          WORD_REF(RTCCTL_ADDR)
-
-#define RTCCTL_384      0x0020  /* Crystal Selection */
-#define RTCCTL_ENABLE   0x0080  /* RTC Enable */
-
-/* 'EZ328-compatible definitions */
-#define RTCCTL_XTL      RTCCTL_384
-#define RTCCTL_EN       RTCCTL_ENABLE
-
-/*
- * RTC Interrupt Status Register 
- */
-#define RTCISR_ADDR     0xfffffb0e
-#define RTCISR          WORD_REF(RTCISR_ADDR)
-
-#define RTCISR_SW       0x0001  /* Stopwatch timed out */
-#define RTCISR_MIN      0x0002  /* 1-minute interrupt has occurred */
-#define RTCISR_ALM      0x0004  /* Alarm interrupt has occurred */
-#define RTCISR_DAY      0x0008  /* 24-hour rollover interrupt has occurred */
-#define RTCISR_1HZ      0x0010  /* 1Hz interrupt has occurred */
-
-/*
- * RTC Interrupt Enable Register
- */
-#define RTCIENR_ADDR    0xfffffb10
-#define RTCIENR         WORD_REF(RTCIENR_ADDR)
-
-#define RTCIENR_SW      0x0001  /* Stopwatch interrupt enable */
-#define RTCIENR_MIN     0x0002  /* 1-minute interrupt enable */
-#define RTCIENR_ALM     0x0004  /* Alarm interrupt enable */
-#define RTCIENR_DAY     0x0008  /* 24-hour rollover interrupt enable */
-#define RTCIENR_1HZ     0x0010  /* 1Hz interrupt enable */
-
-/* 
- * Stopwatch Minutes Register
- */
-#define STPWCH_ADDR     0xfffffb12
-#define STPWCH          WORD_REF(STPWCH)
-
-#define STPWCH_CNT_MASK  0x00ff /* Stopwatch countdown value */
-#define SPTWCH_CNT_SHIFT 0
-
-#endif /* _MC68328_H_ */
diff --git a/arch/m68knommu/include/asm/MC68332.h b/arch/m68knommu/include/asm/MC68332.h
deleted file mode 100644
index 6bb8f02685a2..000000000000
--- a/arch/m68knommu/include/asm/MC68332.h
+++ /dev/null
@@ -1,152 +0,0 @@
-
-/* include/asm-m68knommu/MC68332.h: '332 control registers
- *
- * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
- *
- */
-
-#ifndef _MC68332_H_
-#define _MC68332_H_
-
-#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
-#define WORD_REF(addr) (*((volatile unsigned short*)addr))
-
-#define PORTE_ADDR      0xfffa11
-#define PORTE   BYTE_REF(PORTE_ADDR)
-#define DDRE_ADDR       0xfffa15
-#define DDRE    BYTE_REF(DDRE_ADDR)
-#define PEPAR_ADDR      0xfffa17
-#define PEPAR   BYTE_REF(PEPAR_ADDR)
-
-#define PORTF_ADDR      0xfffa19
-#define PORTF   BYTE_REF(PORTF_ADDR)
-#define DDRF_ADDR       0xfffa1d
-#define DDRF    BYTE_REF(DDRF_ADDR)
-#define PFPAR_ADDR      0xfffa1f
-#define PFPAR   BYTE_REF(PFPAR_ADDR)
-
-#define PORTQS_ADDR     0xfffc15
-#define PORTQS  BYTE_REF(PORTQS_ADDR)
-#define DDRQS_ADDR      0xfffc17
-#define DDRQS   BYTE_REF(DDRQS_ADDR)
-#define PQSPAR_ADDR     0xfffc16
-#define PQSPAR  BYTE_REF(PQSPAR_ADDR)
-
-#define CSPAR0_ADDR 0xFFFA44
-#define CSPAR0 WORD_REF(CSPAR0_ADDR)
-#define CSPAR1_ADDR 0xFFFA46
-#define CSPAR1 WORD_REF(CSPAR1_ADDR)
-#define CSARBT_ADDR 0xFFFA48
-#define CSARBT WORD_REF(CSARBT_ADDR)
-#define CSOPBT_ADDR 0xFFFA4A
-#define CSOPBT WORD_REF(CSOPBT_ADDR)
-#define CSBAR0_ADDR 0xFFFA4C
-#define CSBAR0 WORD_REF(CSBAR0_ADDR)
-#define CSOR0_ADDR 0xFFFA4E
-#define CSOR0 WORD_REF(CSOR0_ADDR)
-#define CSBAR1_ADDR 0xFFFA50
-#define CSBAR1 WORD_REF(CSBAR1_ADDR)
-#define CSOR1_ADDR 0xFFFA52
-#define CSOR1 WORD_REF(CSOR1_ADDR)
-#define CSBAR2_ADDR 0xFFFA54
-#define CSBAR2 WORD_REF(CSBAR2_ADDR)
-#define CSOR2_ADDR 0xFFFA56
-#define CSOR2 WORD_REF(CSOR2_ADDR)
-#define CSBAR3_ADDR 0xFFFA58
-#define CSBAR3 WORD_REF(CSBAR3_ADDR)
-#define CSOR3_ADDR 0xFFFA5A
-#define CSOR3 WORD_REF(CSOR3_ADDR)
-#define CSBAR4_ADDR 0xFFFA5C
-#define CSBAR4 WORD_REF(CSBAR4_ADDR)
-#define CSOR4_ADDR 0xFFFA5E
-#define CSOR4 WORD_REF(CSOR4_ADDR)
-#define CSBAR5_ADDR 0xFFFA60
-#define CSBAR5 WORD_REF(CSBAR5_ADDR)
-#define CSOR5_ADDR 0xFFFA62
-#define CSOR5 WORD_REF(CSOR5_ADDR)
-#define CSBAR6_ADDR 0xFFFA64
-#define CSBAR6 WORD_REF(CSBAR6_ADDR)
-#define CSOR6_ADDR 0xFFFA66
-#define CSOR6 WORD_REF(CSOR6_ADDR)
-#define CSBAR7_ADDR 0xFFFA68
-#define CSBAR7 WORD_REF(CSBAR7_ADDR)
-#define CSOR7_ADDR 0xFFFA6A
-#define CSOR7 WORD_REF(CSOR7_ADDR)
-#define CSBAR8_ADDR 0xFFFA6C
-#define CSBAR8 WORD_REF(CSBAR8_ADDR)
-#define CSOR8_ADDR 0xFFFA6E
-#define CSOR8 WORD_REF(CSOR8_ADDR)
-#define CSBAR9_ADDR 0xFFFA70
-#define CSBAR9 WORD_REF(CSBAR9_ADDR)
-#define CSOR9_ADDR 0xFFFA72
-#define CSOR9 WORD_REF(CSOR9_ADDR)
-#define CSBAR10_ADDR 0xFFFA74
-#define CSBAR10 WORD_REF(CSBAR10_ADDR)
-#define CSOR10_ADDR 0xFFFA76
-#define CSOR10 WORD_REF(CSOR10_ADDR)
-
-#define CSOR_MODE_ASYNC 0x0000
-#define CSOR_MODE_SYNC  0x8000
-#define CSOR_MODE_MASK  0x8000
-#define CSOR_BYTE_DISABLE       0x0000
-#define CSOR_BYTE_UPPER         0x4000
-#define CSOR_BYTE_LOWER         0x2000
-#define CSOR_BYTE_BOTH          0x6000
-#define CSOR_BYTE_MASK          0x6000
-#define CSOR_RW_RSVD            0x0000
-#define CSOR_RW_READ            0x0800
-#define CSOR_RW_WRITE           0x1000
-#define CSOR_RW_BOTH            0x1800
-#define CSOR_RW_MASK            0x1800
-#define CSOR_STROBE_DS          0x0400
-#define CSOR_STROBE_AS          0x0000
-#define CSOR_STROBE_MASK        0x0400
-#define CSOR_DSACK_WAIT(x)      (wait << 6)
-#define CSOR_DSACK_FTERM        (14 << 6)
-#define CSOR_DSACK_EXTERNAL     (15 << 6)
-#define CSOR_DSACK_MASK         0x03c0
-#define CSOR_SPACE_CPU          0x0000
-#define CSOR_SPACE_USER         0x0010
-#define CSOR_SPACE_SU           0x0020
-#define CSOR_SPACE_BOTH         0x0030
-#define CSOR_SPACE_MASK         0x0030
-#define CSOR_IPL_ALL            0x0000
-#define CSOR_IPL_PRIORITY(x)    (x << 1)
-#define CSOR_IPL_MASK           0x000e
-#define CSOR_AVEC_ON            0x0001
-#define CSOR_AVEC_OFF           0x0000
-#define CSOR_AVEC_MASK          0x0001
-
-#define CSBAR_ADDR(x)           ((addr >> 11) << 3) 
-#define CSBAR_ADDR_MASK         0xfff8
-#define CSBAR_BLKSIZE_2K        0x0000
-#define CSBAR_BLKSIZE_8K        0x0001
-#define CSBAR_BLKSIZE_16K       0x0002
-#define CSBAR_BLKSIZE_64K       0x0003
-#define CSBAR_BLKSIZE_128K      0x0004
-#define CSBAR_BLKSIZE_256K      0x0005
-#define CSBAR_BLKSIZE_512K      0x0006
-#define CSBAR_BLKSIZE_1M        0x0007
-#define CSBAR_BLKSIZE_MASK      0x0007
-
-#define CSPAR_DISC      0
-#define CSPAR_ALT       1
-#define CSPAR_CS8       2
-#define CSPAR_CS16      3
-#define CSPAR_MASK      3
-
-#define CSPAR0_CSBOOT(x) (x << 0)
-#define CSPAR0_CS0(x)   (x << 2)
-#define CSPAR0_CS1(x)   (x << 4)
-#define CSPAR0_CS2(x)   (x << 6)
-#define CSPAR0_CS3(x)   (x << 8)
-#define CSPAR0_CS4(x)   (x << 10)
-#define CSPAR0_CS5(x)   (x << 12)
-
-#define CSPAR1_CS6(x)   (x << 0)
-#define CSPAR1_CS7(x)   (x << 2)
-#define CSPAR1_CS8(x)   (x << 4)
-#define CSPAR1_CS9(x)   (x << 6)
-#define CSPAR1_CS10(x)  (x << 8)
-
-#endif
diff --git a/arch/m68knommu/include/asm/MC68EZ328.h b/arch/m68knommu/include/asm/MC68EZ328.h
deleted file mode 100644
index 69b7f9139e5e..000000000000
--- a/arch/m68knommu/include/asm/MC68EZ328.h
+++ /dev/null
@@ -1,1253 +0,0 @@
-
-/* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
- *
- * Copyright (C) 1999  Vladimir Gurevich <vgurevic@cisco.com>
- *                     Bear & Hare Software, Inc.
- *
- * Based on include/asm-m68knommu/MC68332.h
- * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
- *                     The Silver Hammer Group, Ltd.
- *
- */
-
-#ifndef _MC68EZ328_H_
-#define _MC68EZ328_H_
-
-#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
-#define WORD_REF(addr) (*((volatile unsigned short*)addr))
-#define LONG_REF(addr) (*((volatile unsigned long*)addr))
-
-#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
-#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
-
-/********** 
- *
- * 0xFFFFF0xx -- System Control
- *
- **********/
- 
-/*
- * System Control Register (SCR)
- */
-#define SCR_ADDR        0xfffff000
-#define SCR             BYTE_REF(SCR_ADDR)
-
-#define SCR_WDTH8       0x01    /* 8-Bit Width Select */
-#define SCR_DMAP        0x04    /* Double Map */
-#define SCR_SO          0x08    /* Supervisor Only */
-#define SCR_BETEN       0x10    /* Bus-Error Time-Out Enable */
-#define SCR_PRV         0x20    /* Privilege Violation */
-#define SCR_WPV         0x40    /* Write Protect Violation */
-#define SCR_BETO        0x80    /* Bus-Error TimeOut */
-
-/*
- * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
- */
-#define MRR_ADDR 0xfffff004
-#define MRR      LONG_REF(MRR_ADDR)
-
-/********** 
- *
- * 0xFFFFF1xx -- Chip-Select logic
- *
- **********/
- 
-/*
- * Chip Select Group Base Registers 
- */
-#define CSGBA_ADDR      0xfffff100
-#define CSGBB_ADDR      0xfffff102
-
-#define CSGBC_ADDR      0xfffff104
-#define CSGBD_ADDR      0xfffff106
-
-#define CSGBA           WORD_REF(CSGBA_ADDR)
-#define CSGBB           WORD_REF(CSGBB_ADDR)
-#define CSGBC           WORD_REF(CSGBC_ADDR)
-#define CSGBD           WORD_REF(CSGBD_ADDR)
-
-/*
- * Chip Select Registers 
- */
-#define CSA_ADDR        0xfffff110
-#define CSB_ADDR        0xfffff112
-#define CSC_ADDR        0xfffff114
-#define CSD_ADDR        0xfffff116
-
-#define CSA             WORD_REF(CSA_ADDR)
-#define CSB             WORD_REF(CSB_ADDR)
-#define CSC             WORD_REF(CSC_ADDR)
-#define CSD             WORD_REF(CSD_ADDR)
-
-#define CSA_EN          0x0001          /* Chip-Select Enable */
-#define CSA_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSA_SIZ_SHIFT   1
-#define CSA_WS_MASK     0x0070          /* Wait State */
-#define CSA_WS_SHIFT    4
-#define CSA_BSW         0x0080          /* Data Bus Width */
-#define CSA_FLASH       0x0100          /* FLASH Memory Support */
-#define CSA_RO          0x8000          /* Read-Only */
-
-#define CSB_EN          0x0001          /* Chip-Select Enable */
-#define CSB_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSB_SIZ_SHIFT   1
-#define CSB_WS_MASK     0x0070          /* Wait State */
-#define CSB_WS_SHIFT    4
-#define CSB_BSW         0x0080          /* Data Bus Width */
-#define CSB_FLASH       0x0100          /* FLASH Memory Support */
-#define CSB_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
-#define CSB_UPSIZ_SHIFT 11
-#define CSB_ROP         0x2000          /* Readonly if protected */
-#define CSB_SOP         0x4000          /* Supervisor only if protected */
-#define CSB_RO          0x8000          /* Read-Only */
-
-#define CSC_EN          0x0001          /* Chip-Select Enable */
-#define CSC_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSC_SIZ_SHIFT   1
-#define CSC_WS_MASK     0x0070          /* Wait State */
-#define CSC_WS_SHIFT    4
-#define CSC_BSW         0x0080          /* Data Bus Width */
-#define CSC_FLASH       0x0100          /* FLASH Memory Support */
-#define CSC_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
-#define CSC_UPSIZ_SHIFT 11
-#define CSC_ROP         0x2000          /* Readonly if protected */
-#define CSC_SOP         0x4000          /* Supervisor only if protected */
-#define CSC_RO          0x8000          /* Read-Only */
-
-#define CSD_EN          0x0001          /* Chip-Select Enable */
-#define CSD_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSD_SIZ_SHIFT   1
-#define CSD_WS_MASK     0x0070          /* Wait State */
-#define CSD_WS_SHIFT    4
-#define CSD_BSW         0x0080          /* Data Bus Width */
-#define CSD_FLASH       0x0100          /* FLASH Memory Support */
-#define CSD_DRAM        0x0200          /* Dram Selection */
-#define CSD_COMB        0x0400          /* Combining */
-#define CSD_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
-#define CSD_UPSIZ_SHIFT 11
-#define CSD_ROP         0x2000          /* Readonly if protected */
-#define CSD_SOP         0x4000          /* Supervisor only if protected */
-#define CSD_RO          0x8000          /* Read-Only */
-
-/*
- * Emulation Chip-Select Register 
- */
-#define EMUCS_ADDR      0xfffff118
-#define EMUCS           WORD_REF(EMUCS_ADDR)
-
-#define EMUCS_WS_MASK   0x0070
-#define EMUCS_WS_SHIFT  4
-
-/********** 
- *
- * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
- *
- **********/
-
-/*
- * PLL Control Register 
- */
-#define PLLCR_ADDR      0xfffff200
-#define PLLCR           WORD_REF(PLLCR_ADDR)
-
-#define PLLCR_DISPLL           0x0008   /* Disable PLL */
-#define PLLCR_CLKEN            0x0010   /* Clock (CLKO pin) enable */
-#define PLLCR_PRESC            0x0020   /* VCO prescaler */
-#define PLLCR_SYSCLK_SEL_MASK  0x0700   /* System Clock Selection */
-#define PLLCR_SYSCLK_SEL_SHIFT 8
-#define PLLCR_LCDCLK_SEL_MASK  0x3800   /* LCD Clock Selection */
-#define PLLCR_LCDCLK_SEL_SHIFT 11
-
-/* '328-compatible definitions */
-#define PLLCR_PIXCLK_SEL_MASK   PLLCR_LCDCLK_SEL_MASK
-#define PLLCR_PIXCLK_SEL_SHIFT  PLLCR_LCDCLK_SEL_SHIFT
-
-/*
- * PLL Frequency Select Register
- */
-#define PLLFSR_ADDR     0xfffff202
-#define PLLFSR          WORD_REF(PLLFSR_ADDR)
-
-#define PLLFSR_PC_MASK  0x00ff          /* P Count */
-#define PLLFSR_PC_SHIFT 0
-#define PLLFSR_QC_MASK  0x0f00          /* Q Count */
-#define PLLFSR_QC_SHIFT 8
-#define PLLFSR_PROT     0x4000          /* Protect P & Q */
-#define PLLFSR_CLK32    0x8000          /* Clock 32 (kHz) */
-
-/*
- * Power Control Register
- */
-#define PCTRL_ADDR      0xfffff207
-#define PCTRL           BYTE_REF(PCTRL_ADDR)
-
-#define PCTRL_WIDTH_MASK        0x1f    /* CPU Clock bursts width */
-#define PCTRL_WIDTH_SHIFT       0
-#define PCTRL_PCEN              0x80    /* Power Control Enable */
-
-/**********
- *
- * 0xFFFFF3xx -- Interrupt Controller
- *
- **********/
-
-/* 
- * Interrupt Vector Register
- */
-#define IVR_ADDR        0xfffff300
-#define IVR             BYTE_REF(IVR_ADDR)
-
-#define IVR_VECTOR_MASK 0xF8
-
-/*
- * Interrupt control Register
- */
-#define ICR_ADDR        0xfffff302
-#define ICR             WORD_REF(ICR_ADDR)
-
-#define ICR_POL5        0x0080  /* Polarity Control for IRQ5 */
-#define ICR_ET6         0x0100  /* Edge Trigger Select for IRQ6 */
-#define ICR_ET3         0x0200  /* Edge Trigger Select for IRQ3 */
-#define ICR_ET2         0x0400  /* Edge Trigger Select for IRQ2 */
-#define ICR_ET1         0x0800  /* Edge Trigger Select for IRQ1 */
-#define ICR_POL6        0x1000  /* Polarity Control for IRQ6 */
-#define ICR_POL3        0x2000  /* Polarity Control for IRQ3 */
-#define ICR_POL2        0x4000  /* Polarity Control for IRQ2 */
-#define ICR_POL1        0x8000  /* Polarity Control for IRQ1 */
-
-/*
- * Interrupt Mask Register
- */
-#define IMR_ADDR        0xfffff304
-#define IMR             LONG_REF(IMR_ADDR)
-
-/*
- * Define the names for bit positions first. This is useful for 
- * request_irq
- */
-#define SPI_IRQ_NUM     0       /* SPI interrupt */
-#define TMR_IRQ_NUM     1       /* Timer interrupt */
-#define UART_IRQ_NUM    2       /* UART interrupt */    
-#define WDT_IRQ_NUM     3       /* Watchdog Timer interrupt */
-#define RTC_IRQ_NUM     4       /* RTC interrupt */
-#define KB_IRQ_NUM      6       /* Keyboard Interrupt */
-#define PWM_IRQ_NUM     7       /* Pulse-Width Modulator int. */
-#define INT0_IRQ_NUM    8       /* External INT0 */
-#define INT1_IRQ_NUM    9       /* External INT1 */
-#define INT2_IRQ_NUM    10      /* External INT2 */
-#define INT3_IRQ_NUM    11      /* External INT3 */
-#define IRQ1_IRQ_NUM    16      /* IRQ1 */
-#define IRQ2_IRQ_NUM    17      /* IRQ2 */
-#define IRQ3_IRQ_NUM    18      /* IRQ3 */
-#define IRQ6_IRQ_NUM    19      /* IRQ6 */
-#define IRQ5_IRQ_NUM    20      /* IRQ5 */
-#define SAM_IRQ_NUM     22      /* Sampling Timer for RTC */
-#define EMIQ_IRQ_NUM    23      /* Emulator Interrupt */
-
-/* '328-compatible definitions */
-#define SPIM_IRQ_NUM    SPI_IRQ_NUM
-#define TMR1_IRQ_NUM    TMR_IRQ_NUM
-
-/* 
- * Here go the bitmasks themselves
- */
-#define IMR_MSPI        (1 << SPI_IRQ_NUM)      /* Mask SPI interrupt */
-#define IMR_MTMR        (1 << TMR_IRQ_NUM)      /* Mask Timer interrupt */
-#define IMR_MUART       (1 << UART_IRQ_NUM)     /* Mask UART interrupt */       
-#define IMR_MWDT        (1 << WDT_IRQ_NUM)      /* Mask Watchdog Timer interrupt */
-#define IMR_MRTC        (1 << RTC_IRQ_NUM)      /* Mask RTC interrupt */
-#define IMR_MKB         (1 << KB_IRQ_NUM)       /* Mask Keyboard Interrupt */
-#define IMR_MPWM        (1 << PWM_IRQ_NUM)      /* Mask Pulse-Width Modulator int. */
-#define IMR_MINT0       (1 << INT0_IRQ_NUM)     /* Mask External INT0 */
-#define IMR_MINT1       (1 << INT1_IRQ_NUM)     /* Mask External INT1 */
-#define IMR_MINT2       (1 << INT2_IRQ_NUM)     /* Mask External INT2 */
-#define IMR_MINT3       (1 << INT3_IRQ_NUM)     /* Mask External INT3 */
-#define IMR_MIRQ1       (1 << IRQ1_IRQ_NUM)     /* Mask IRQ1 */
-#define IMR_MIRQ2       (1 << IRQ2_IRQ_NUM)     /* Mask IRQ2 */
-#define IMR_MIRQ3       (1 << IRQ3_IRQ_NUM)     /* Mask IRQ3 */
-#define IMR_MIRQ6       (1 << IRQ6_IRQ_NUM)     /* Mask IRQ6 */
-#define IMR_MIRQ5       (1 << IRQ5_IRQ_NUM)     /* Mask IRQ5 */
-#define IMR_MSAM        (1 << SAM_IRQ_NUM)      /* Mask Sampling Timer for RTC */
-#define IMR_MEMIQ       (1 << EMIQ_IRQ_NUM)     /* Mask Emulator Interrupt */
-
-/* '328-compatible definitions */
-#define IMR_MSPIM       IMR_MSPI
-#define IMR_MTMR1       IMR_MTMR
-
-/* 
- * Interrupt Status Register 
- */
-#define ISR_ADDR        0xfffff30c
-#define ISR             LONG_REF(ISR_ADDR)
-
-#define ISR_SPI         (1 << SPI_IRQ_NUM)      /* SPI interrupt */
-#define ISR_TMR         (1 << TMR_IRQ_NUM)      /* Timer interrupt */
-#define ISR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */    
-#define ISR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
-#define ISR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
-#define ISR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
-#define ISR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator interrupt */
-#define ISR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
-#define ISR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
-#define ISR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
-#define ISR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
-#define ISR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
-#define ISR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
-#define ISR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
-#define ISR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
-#define ISR_IRQ5        (1 << IRQ5_IRQ_NUM)     /* IRQ5 */
-#define ISR_SAM         (1 << SAM_IRQ_NUM)      /* Sampling Timer for RTC */
-#define ISR_EMIQ        (1 << EMIQ_IRQ_NUM)     /* Emulator Interrupt */
-
-/* '328-compatible definitions */
-#define ISR_SPIM        ISR_SPI
-#define ISR_TMR1        ISR_TMR
-
-/* 
- * Interrupt Pending Register 
- */
-#define IPR_ADDR        0xfffff30c
-#define IPR             LONG_REF(IPR_ADDR)
-
-#define IPR_SPI         (1 << SPI_IRQ_NUM)      /* SPI interrupt */
-#define IPR_TMR         (1 << TMR_IRQ_NUM)      /* Timer interrupt */
-#define IPR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */    
-#define IPR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
-#define IPR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
-#define IPR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
-#define IPR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator interrupt */
-#define IPR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
-#define IPR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
-#define IPR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
-#define IPR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
-#define IPR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
-#define IPR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
-#define IPR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
-#define IPR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
-#define IPR_IRQ5        (1 << IRQ5_IRQ_NUM)     /* IRQ5 */
-#define IPR_SAM         (1 << SAM_IRQ_NUM)      /* Sampling Timer for RTC */
-#define IPR_EMIQ        (1 << EMIQ_IRQ_NUM)     /* Emulator Interrupt */
-
-/* '328-compatible definitions */
-#define IPR_SPIM        IPR_SPI
-#define IPR_TMR1        IPR_TMR
-
-/**********
- *
- * 0xFFFFF4xx -- Parallel Ports
- *
- **********/
-
-/*
- * Port A
- */
-#define PADIR_ADDR      0xfffff400              /* Port A direction reg */
-#define PADATA_ADDR     0xfffff401              /* Port A data register */
-#define PAPUEN_ADDR     0xfffff402              /* Port A Pull-Up enable reg */
-
-#define PADIR           BYTE_REF(PADIR_ADDR)
-#define PADATA          BYTE_REF(PADATA_ADDR)
-#define PAPUEN          BYTE_REF(PAPUEN_ADDR)
-
-#define PA(x)           (1 << (x))
-
-/* 
- * Port B
- */
-#define PBDIR_ADDR      0xfffff408              /* Port B direction reg */
-#define PBDATA_ADDR     0xfffff409              /* Port B data register */
-#define PBPUEN_ADDR     0xfffff40a              /* Port B Pull-Up enable reg */
-#define PBSEL_ADDR      0xfffff40b              /* Port B Select Register */
-
-#define PBDIR           BYTE_REF(PBDIR_ADDR)
-#define PBDATA          BYTE_REF(PBDATA_ADDR)
-#define PBPUEN          BYTE_REF(PBPUEN_ADDR)
-#define PBSEL           BYTE_REF(PBSEL_ADDR)
-
-#define PB(x)           (1 << (x))
-
-#define PB_CSB0         0x01    /* Use CSB0      as PB[0] */
-#define PB_CSB1         0x02    /* Use CSB1      as PB[1] */
-#define PB_CSC0_RAS0    0x04    /* Use CSC0/RAS0 as PB[2] */    
-#define PB_CSC1_RAS1    0x08    /* Use CSC1/RAS1 as PB[3] */    
-#define PB_CSD0_CAS0    0x10    /* Use CSD0/CAS0 as PB[4] */    
-#define PB_CSD1_CAS1    0x20    /* Use CSD1/CAS1 as PB[5] */
-#define PB_TIN_TOUT     0x40    /* Use TIN/TOUT  as PB[6] */
-#define PB_PWMO         0x80    /* Use PWMO      as PB[7] */
-
-/* 
- * Port C
- */
-#define PCDIR_ADDR      0xfffff410              /* Port C direction reg */
-#define PCDATA_ADDR     0xfffff411              /* Port C data register */
-#define PCPDEN_ADDR     0xfffff412              /* Port C Pull-Down enb. reg */
-#define PCSEL_ADDR      0xfffff413              /* Port C Select Register */
-
-#define PCDIR           BYTE_REF(PCDIR_ADDR)
-#define PCDATA          BYTE_REF(PCDATA_ADDR)
-#define PCPDEN          BYTE_REF(PCPDEN_ADDR)
-#define PCSEL           BYTE_REF(PCSEL_ADDR)
-
-#define PC(x)           (1 << (x))
-
-#define PC_LD0          0x01    /* Use LD0  as PC[0] */
-#define PC_LD1          0x02    /* Use LD1  as PC[1] */
-#define PC_LD2          0x04    /* Use LD2  as PC[2] */
-#define PC_LD3          0x08    /* Use LD3  as PC[3] */
-#define PC_LFLM         0x10    /* Use LFLM as PC[4] */
-#define PC_LLP          0x20    /* Use LLP  as PC[5] */
-#define PC_LCLK         0x40    /* Use LCLK as PC[6] */
-#define PC_LACD         0x80    /* Use LACD as PC[7] */
-
-/* 
- * Port D
- */
-#define PDDIR_ADDR      0xfffff418              /* Port D direction reg */
-#define PDDATA_ADDR     0xfffff419              /* Port D data register */
-#define PDPUEN_ADDR     0xfffff41a              /* Port D Pull-Up enable reg */
-#define PDSEL_ADDR      0xfffff41b              /* Port D Select Register */
-#define PDPOL_ADDR      0xfffff41c              /* Port D Polarity Register */
-#define PDIRQEN_ADDR    0xfffff41d              /* Port D IRQ enable register */
-#define PDKBEN_ADDR     0xfffff41e              /* Port D Keyboard Enable reg */
-#define PDIQEG_ADDR     0xfffff41f              /* Port D IRQ Edge Register */
-
-#define PDDIR           BYTE_REF(PDDIR_ADDR)
-#define PDDATA          BYTE_REF(PDDATA_ADDR)
-#define PDPUEN          BYTE_REF(PDPUEN_ADDR)
-#define PDSEL           BYTE_REF(PDSEL_ADDR)
-#define PDPOL           BYTE_REF(PDPOL_ADDR)
-#define PDIRQEN         BYTE_REF(PDIRQEN_ADDR)
-#define PDKBEN          BYTE_REF(PDKBEN_ADDR)
-#define PDIQEG          BYTE_REF(PDIQEG_ADDR)
-
-#define PD(x)           (1 << (x))
-
-#define PD_INT0         0x01    /* Use INT0 as PD[0] */
-#define PD_INT1         0x02    /* Use INT1 as PD[1] */
-#define PD_INT2         0x04    /* Use INT2 as PD[2] */
-#define PD_INT3         0x08    /* Use INT3 as PD[3] */
-#define PD_IRQ1         0x10    /* Use IRQ1 as PD[4] */
-#define PD_IRQ2         0x20    /* Use IRQ2 as PD[5] */
-#define PD_IRQ3         0x40    /* Use IRQ3 as PD[6] */
-#define PD_IRQ6         0x80    /* Use IRQ6 as PD[7] */
-
-/* 
- * Port E
- */
-#define PEDIR_ADDR      0xfffff420              /* Port E direction reg */
-#define PEDATA_ADDR     0xfffff421              /* Port E data register */
-#define PEPUEN_ADDR     0xfffff422              /* Port E Pull-Up enable reg */
-#define PESEL_ADDR      0xfffff423              /* Port E Select Register */
-
-#define PEDIR           BYTE_REF(PEDIR_ADDR)
-#define PEDATA          BYTE_REF(PEDATA_ADDR)
-#define PEPUEN          BYTE_REF(PEPUEN_ADDR)
-#define PESEL           BYTE_REF(PESEL_ADDR)
-
-#define PE(x)           (1 << (x))
-
-#define PE_SPMTXD       0x01    /* Use SPMTXD as PE[0] */
-#define PE_SPMRXD       0x02    /* Use SPMRXD as PE[1] */
-#define PE_SPMCLK       0x04    /* Use SPMCLK as PE[2] */
-#define PE_DWE          0x08    /* Use DWE    as PE[3] */
-#define PE_RXD          0x10    /* Use RXD    as PE[4] */
-#define PE_TXD          0x20    /* Use TXD    as PE[5] */
-#define PE_RTS          0x40    /* Use RTS    as PE[6] */
-#define PE_CTS          0x80    /* Use CTS    as PE[7] */
-
-/* 
- * Port F
- */
-#define PFDIR_ADDR      0xfffff428              /* Port F direction reg */
-#define PFDATA_ADDR     0xfffff429              /* Port F data register */
-#define PFPUEN_ADDR     0xfffff42a              /* Port F Pull-Up enable reg */
-#define PFSEL_ADDR      0xfffff42b              /* Port F Select Register */
-
-#define PFDIR           BYTE_REF(PFDIR_ADDR)
-#define PFDATA          BYTE_REF(PFDATA_ADDR)
-#define PFPUEN          BYTE_REF(PFPUEN_ADDR)
-#define PFSEL           BYTE_REF(PFSEL_ADDR)
-
-#define PF(x)           (1 << (x))
-
-#define PF_LCONTRAST    0x01    /* Use LCONTRAST as PF[0] */
-#define PF_IRQ5         0x02    /* Use IRQ5      as PF[1] */
-#define PF_CLKO         0x04    /* Use CLKO      as PF[2] */
-#define PF_A20          0x08    /* Use A20       as PF[3] */
-#define PF_A21          0x10    /* Use A21       as PF[4] */
-#define PF_A22          0x20    /* Use A22       as PF[5] */
-#define PF_A23          0x40    /* Use A23       as PF[6] */
-#define PF_CSA1         0x80    /* Use CSA1      as PF[7] */
-
-/* 
- * Port G
- */
-#define PGDIR_ADDR      0xfffff430              /* Port G direction reg */
-#define PGDATA_ADDR     0xfffff431              /* Port G data register */
-#define PGPUEN_ADDR     0xfffff432              /* Port G Pull-Up enable reg */
-#define PGSEL_ADDR      0xfffff433              /* Port G Select Register */
-
-#define PGDIR           BYTE_REF(PGDIR_ADDR)
-#define PGDATA          BYTE_REF(PGDATA_ADDR)
-#define PGPUEN          BYTE_REF(PGPUEN_ADDR)
-#define PGSEL           BYTE_REF(PGSEL_ADDR)
-
-#define PG(x)           (1 << (x))
-
-#define PG_BUSW_DTACK   0x01    /* Use BUSW/DTACK as PG[0] */
-#define PG_A0           0x02    /* Use A0         as PG[1] */
-#define PG_EMUIRQ       0x04    /* Use EMUIRQ     as PG[2] */
-#define PG_HIZ_P_D      0x08    /* Use HIZ/P/D    as PG[3] */
-#define PG_EMUCS        0x10    /* Use EMUCS      as PG[4] */
-#define PG_EMUBRK       0x20    /* Use EMUBRK     as PG[5] */
-
-/**********
- *
- * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
- *
- **********/
-
-/*
- * PWM Control Register 
- */
-#define PWMC_ADDR       0xfffff500
-#define PWMC            WORD_REF(PWMC_ADDR)
-
-#define PWMC_CLKSEL_MASK        0x0003  /* Clock Selection */
-#define PWMC_CLKSEL_SHIFT       0
-#define PWMC_REPEAT_MASK        0x000c  /* Sample Repeats */
-#define PWMC_REPEAT_SHIFT       2
-#define PWMC_EN                 0x0010  /* Enable PWM */
-#define PMNC_FIFOAV             0x0020  /* FIFO Available */
-#define PWMC_IRQEN              0x0040  /* Interrupt Request Enable */
-#define PWMC_IRQ                0x0080  /* Interrupt Request (FIFO empty) */
-#define PWMC_PRESCALER_MASK     0x7f00  /* Incoming Clock prescaler */
-#define PWMC_PRESCALER_SHIFT    8
-#define PWMC_CLKSRC             0x8000  /* Clock Source Select */
-
-/* '328-compatible definitions */
-#define PWMC_PWMEN      PWMC_EN
-
-/*
- * PWM Sample Register 
- */
-#define PWMS_ADDR       0xfffff502
-#define PWMS            WORD_REF(PWMS_ADDR)
-
-/*
- * PWM Period Register
- */
-#define PWMP_ADDR       0xfffff504
-#define PWMP            BYTE_REF(PWMP_ADDR)
-
-/*
- * PWM Counter Register
- */
-#define PWMCNT_ADDR     0xfffff505
-#define PWMCNT          BYTE_REF(PWMCNT_ADDR)
-
-/**********
- *
- * 0xFFFFF6xx -- General-Purpose Timer
- *
- **********/
-
-/* 
- * Timer Control register
- */
-#define TCTL_ADDR       0xfffff600
-#define TCTL            WORD_REF(TCTL_ADDR)
-
-#define TCTL_TEN                0x0001  /* Timer Enable  */
-#define TCTL_CLKSOURCE_MASK     0x000e  /* Clock Source: */
-#define   TCTL_CLKSOURCE_STOP      0x0000       /* Stop count (disabled)    */
-#define   TCTL_CLKSOURCE_SYSCLK    0x0002       /* SYSCLK to prescaler      */
-#define   TCTL_CLKSOURCE_SYSCLK_16 0x0004       /* SYSCLK/16 to prescaler   */
-#define   TCTL_CLKSOURCE_TIN       0x0006       /* TIN to prescaler         */
-#define   TCTL_CLKSOURCE_32KHZ     0x0008       /* 32kHz clock to prescaler */
-#define TCTL_IRQEN              0x0010  /* IRQ Enable    */
-#define TCTL_OM                 0x0020  /* Output Mode   */
-#define TCTL_CAP_MASK           0x00c0  /* Capture Edge: */
-#define   TCTL_CAP_RE           0x0040          /* Capture on rizing edge   */
-#define   TCTL_CAP_FE           0x0080          /* Capture on falling edge  */
-#define TCTL_FRR                0x0010  /* Free-Run Mode */
-
-/* '328-compatible definitions */
-#define TCTL1_ADDR      TCTL_ADDR
-#define TCTL1           TCTL
-
-/*
- * Timer Prescaler Register
- */
-#define TPRER_ADDR      0xfffff602
-#define TPRER           WORD_REF(TPRER_ADDR)
-
-/* '328-compatible definitions */
-#define TPRER1_ADDR     TPRER_ADDR
-#define TPRER1          TPRER
-
-/*
- * Timer Compare Register
- */
-#define TCMP_ADDR       0xfffff604
-#define TCMP            WORD_REF(TCMP_ADDR)
-
-/* '328-compatible definitions */
-#define TCMP1_ADDR      TCMP_ADDR
-#define TCMP1           TCMP
-
-/*
- * Timer Capture register
- */
-#define TCR_ADDR        0xfffff606
-#define TCR             WORD_REF(TCR_ADDR)
-
-/* '328-compatible definitions */
-#define TCR1_ADDR       TCR_ADDR
-#define TCR1            TCR
-
-/*
- * Timer Counter Register
- */
-#define TCN_ADDR        0xfffff608
-#define TCN             WORD_REF(TCN_ADDR)
-
-/* '328-compatible definitions */
-#define TCN1_ADDR       TCN_ADDR
-#define TCN1            TCN
-
-/*
- * Timer Status Register
- */
-#define TSTAT_ADDR      0xfffff60a
-#define TSTAT           WORD_REF(TSTAT_ADDR)
-
-#define TSTAT_COMP      0x0001          /* Compare Event occurred */
-#define TSTAT_CAPT      0x0001          /* Capture Event occurred */
-
-/* '328-compatible definitions */
-#define TSTAT1_ADDR     TSTAT_ADDR
-#define TSTAT1          TSTAT
-
-/**********
- *
- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
- *
- **********/
-
-/*
- * SPIM Data Register
- */
-#define SPIMDATA_ADDR   0xfffff800
-#define SPIMDATA        WORD_REF(SPIMDATA_ADDR)
-
-/*
- * SPIM Control/Status Register
- */
-#define SPIMCONT_ADDR   0xfffff802
-#define SPIMCONT        WORD_REF(SPIMCONT_ADDR)
-
-#define SPIMCONT_BIT_COUNT_MASK  0x000f /* Transfer Length in Bytes */
-#define SPIMCONT_BIT_COUNT_SHIFT 0
-#define SPIMCONT_POL             0x0010 /* SPMCLK Signel Polarity */
-#define SPIMCONT_PHA             0x0020 /* Clock/Data phase relationship */
-#define SPIMCONT_IRQEN           0x0040 /* IRQ Enable */
-#define SPIMCONT_IRQ             0x0080 /* Interrupt Request */
-#define SPIMCONT_XCH             0x0100 /* Exchange */
-#define SPIMCONT_ENABLE          0x0200 /* Enable SPIM */
-#define SPIMCONT_DATA_RATE_MASK  0xe000 /* SPIM Data Rate */
-#define SPIMCONT_DATA_RATE_SHIFT 13
-
-/* '328-compatible definitions */
-#define SPIMCONT_SPIMIRQ        SPIMCONT_IRQ
-#define SPIMCONT_SPIMEN         SPIMCONT_ENABLE
-
-/**********
- *
- * 0xFFFFF9xx -- UART
- *
- **********/
-
-/*
- * UART Status/Control Register
- */
-#define USTCNT_ADDR     0xfffff900
-#define USTCNT          WORD_REF(USTCNT_ADDR)
-
-#define USTCNT_TXAE     0x0001  /* Transmitter Available Interrupt Enable */
-#define USTCNT_TXHE     0x0002  /* Transmitter Half Empty Enable */
-#define USTCNT_TXEE     0x0004  /* Transmitter Empty Interrupt Enable */
-#define USTCNT_RXRE     0x0008  /* Receiver Ready Interrupt Enable */
-#define USTCNT_RXHE     0x0010  /* Receiver Half-Full Interrupt Enable */
-#define USTCNT_RXFE     0x0020  /* Receiver Full Interrupt Enable */
-#define USTCNT_CTSD     0x0040  /* CTS Delta Interrupt Enable */
-#define USTCNT_ODEN     0x0080  /* Old Data Interrupt Enable */
-#define USTCNT_8_7      0x0100  /* Eight or seven-bit transmission */
-#define USTCNT_STOP     0x0200  /* Stop bit transmission */
-#define USTCNT_ODD      0x0400  /* Odd Parity */
-#define USTCNT_PEN      0x0800  /* Parity Enable */
-#define USTCNT_CLKM     0x1000  /* Clock Mode Select */
-#define USTCNT_TXEN     0x2000  /* Transmitter Enable */
-#define USTCNT_RXEN     0x4000  /* Receiver Enable */
-#define USTCNT_UEN      0x8000  /* UART Enable */
-
-/* '328-compatible definitions */
-#define USTCNT_TXAVAILEN        USTCNT_TXAE
-#define USTCNT_TXHALFEN         USTCNT_TXHE
-#define USTCNT_TXEMPTYEN        USTCNT_TXEE
-#define USTCNT_RXREADYEN        USTCNT_RXRE
-#define USTCNT_RXHALFEN         USTCNT_RXHE
-#define USTCNT_RXFULLEN         USTCNT_RXFE
-#define USTCNT_CTSDELTAEN       USTCNT_CTSD
-#define USTCNT_ODD_EVEN         USTCNT_ODD
-#define USTCNT_PARITYEN         USTCNT_PEN
-#define USTCNT_CLKMODE          USTCNT_CLKM
-#define USTCNT_UARTEN           USTCNT_UEN
-
-/*
- * UART Baud Control Register
- */
-#define UBAUD_ADDR      0xfffff902
-#define UBAUD           WORD_REF(UBAUD_ADDR)
-
-#define UBAUD_PRESCALER_MASK    0x003f  /* Actual divisor is 65 - PRESCALER */
-#define UBAUD_PRESCALER_SHIFT   0
-#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divizor */
-#define UBAUD_DIVIDE_SHIFT      8
-#define UBAUD_BAUD_SRC          0x0800  /* Baud Rate Source */
-#define UBAUD_UCLKDIR           0x2000  /* UCLK Direction */
-
-/*
- * UART Receiver Register 
- */
-#define URX_ADDR        0xfffff904
-#define URX             WORD_REF(URX_ADDR)
-
-#define URX_RXDATA_ADDR 0xfffff905
-#define URX_RXDATA      BYTE_REF(URX_RXDATA_ADDR)
-
-#define URX_RXDATA_MASK  0x00ff /* Received data */
-#define URX_RXDATA_SHIFT 0
-#define URX_PARITY_ERROR 0x0100 /* Parity Error */
-#define URX_BREAK        0x0200 /* Break Detected */
-#define URX_FRAME_ERROR  0x0400 /* Framing Error */
-#define URX_OVRUN        0x0800 /* Serial Overrun */
-#define URX_OLD_DATA     0x1000 /* Old data in FIFO */
-#define URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */
-#define URX_FIFO_HALF    0x4000 /* FIFO is Half-Full */
-#define URX_FIFO_FULL    0x8000 /* FIFO is Full */
-
-/*
- * UART Transmitter Register 
- */
-#define UTX_ADDR        0xfffff906
-#define UTX             WORD_REF(UTX_ADDR)
-
-#define UTX_TXDATA_ADDR 0xfffff907
-#define UTX_TXDATA      BYTE_REF(UTX_TXDATA_ADDR)
-
-#define UTX_TXDATA_MASK  0x00ff /* Data to be transmitted */
-#define UTX_TXDATA_SHIFT 0
-#define UTX_CTS_DELTA    0x0100 /* CTS changed */
-#define UTX_CTS_STAT     0x0200 /* CTS State */
-#define UTX_BUSY         0x0400 /* FIFO is busy, sending a character */
-#define UTX_NOCTS        0x0800 /* Ignore CTS */
-#define UTX_SEND_BREAK   0x1000 /* Send a BREAK */
-#define UTX_TX_AVAIL     0x2000 /* Transmit FIFO has a slot available */
-#define UTX_FIFO_HALF    0x4000 /* Transmit FIFO is half empty */
-#define UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */
-
-/* '328-compatible definitions */
-#define UTX_CTS_STATUS  UTX_CTS_STAT
-#define UTX_IGNORE_CTS  UTX_NOCTS
-
-/*
- * UART Miscellaneous Register 
- */
-#define UMISC_ADDR      0xfffff908
-#define UMISC           WORD_REF(UMISC_ADDR)
-
-#define UMISC_TX_POL     0x0004 /* Transmit Polarity */
-#define UMISC_RX_POL     0x0008 /* Receive Polarity */
-#define UMISC_IRDA_LOOP  0x0010 /* IrDA Loopback Enable */
-#define UMISC_IRDA_EN    0x0020 /* Infra-Red Enable */
-#define UMISC_RTS        0x0040 /* Set RTS status */
-#define UMISC_RTSCONT    0x0080 /* Choose RTS control */
-#define UMISC_IR_TEST    0x0400 /* IRDA Test Enable */
-#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
-#define UMISC_LOOP       0x1000 /* Serial Loopback Enable */
-#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
-#define UMISC_CLKSRC     0x4000 /* Clock Source */
-#define UMISC_BAUD_TEST  0x8000 /* Enable Baud Test Mode */
-
-/* 
- * UART Non-integer Prescaler Register
- */
-#define NIPR_ADDR       0xfffff90a
-#define NIPR            WORD_REF(NIPR_ADDR)
-
-#define NIPR_STEP_VALUE_MASK    0x00ff  /* NI prescaler step value */
-#define NIPR_STEP_VALUE_SHIFT   0
-#define NIPR_SELECT_MASK        0x0700  /* Tap Selection */
-#define NIPR_SELECT_SHIFT       8
-#define NIPR_PRE_SEL            0x8000  /* Non-integer prescaler select */
-
-
-/* generalization of uart control registers to support multiple ports: */
-typedef volatile struct {
-  volatile unsigned short int ustcnt;
-  volatile unsigned short int ubaud;
-  union {
-    volatile unsigned short int w;
-    struct {
-      volatile unsigned char status;
-      volatile unsigned char rxdata;
-    } b;
-  } urx;
-  union {
-    volatile unsigned short int w;
-    struct {
-      volatile unsigned char status;
-      volatile unsigned char txdata;
-    } b;
-  } utx;
-  volatile unsigned short int umisc;
-  volatile unsigned short int nipr;
-  volatile unsigned short int pad1;
-  volatile unsigned short int pad2;
-} __attribute__((packed)) m68328_uart;
-
-
-/**********
- *
- * 0xFFFFFAxx -- LCD Controller
- *
- **********/
-
-/*
- * LCD Screen Starting Address Register 
- */
-#define LSSA_ADDR       0xfffffa00
-#define LSSA            LONG_REF(LSSA_ADDR)
-
-#define LSSA_SSA_MASK   0x1ffffffe      /* Bits 0 and 29-31 are reserved */
-
-/*
- * LCD Virtual Page Width Register 
- */
-#define LVPW_ADDR       0xfffffa05
-#define LVPW            BYTE_REF(LVPW_ADDR)
-
-/*
- * LCD Screen Width Register (not compatible with '328 !!!) 
- */
-#define LXMAX_ADDR      0xfffffa08
-#define LXMAX           WORD_REF(LXMAX_ADDR)
-
-#define LXMAX_XM_MASK   0x02f0          /* Bits 0-3 and 10-15 are reserved */
-
-/*
- * LCD Screen Height Register
- */
-#define LYMAX_ADDR      0xfffffa0a
-#define LYMAX           WORD_REF(LYMAX_ADDR)
-
-#define LYMAX_YM_MASK   0x01ff          /* Bits 9-15 are reserved */
-
-/*
- * LCD Cursor X Position Register
- */
-#define LCXP_ADDR       0xfffffa18
-#define LCXP            WORD_REF(LCXP_ADDR)
-
-#define LCXP_CC_MASK    0xc000          /* Cursor Control */
-#define   LCXP_CC_TRAMSPARENT   0x0000
-#define   LCXP_CC_BLACK         0x4000
-#define   LCXP_CC_REVERSED      0x8000
-#define   LCXP_CC_WHITE         0xc000
-#define LCXP_CXP_MASK   0x02ff          /* Cursor X position */
-
-/*
- * LCD Cursor Y Position Register
- */
-#define LCYP_ADDR       0xfffffa1a
-#define LCYP            WORD_REF(LCYP_ADDR)
-
-#define LCYP_CYP_MASK   0x01ff          /* Cursor Y Position */
-
-/*
- * LCD Cursor Width and Heigth Register
- */
-#define LCWCH_ADDR      0xfffffa1c
-#define LCWCH           WORD_REF(LCWCH_ADDR)
-
-#define LCWCH_CH_MASK   0x001f          /* Cursor Height */
-#define LCWCH_CH_SHIFT  0
-#define LCWCH_CW_MASK   0x1f00          /* Cursor Width */
-#define LCWCH_CW_SHIFT  8
-
-/*
- * LCD Blink Control Register
- */
-#define LBLKC_ADDR      0xfffffa1f
-#define LBLKC           BYTE_REF(LBLKC_ADDR)
-
-#define LBLKC_BD_MASK   0x7f    /* Blink Divisor */
-#define LBLKC_BD_SHIFT  0
-#define LBLKC_BKEN      0x80    /* Blink Enabled */
-
-/*
- * LCD Panel Interface Configuration Register 
- */
-#define LPICF_ADDR      0xfffffa20
-#define LPICF           BYTE_REF(LPICF_ADDR)
-
-#define LPICF_GS_MASK    0x03    /* Gray-Scale Mode */
-#define   LPICF_GS_BW      0x00
-#define   LPICF_GS_GRAY_4  0x01
-#define   LPICF_GS_GRAY_16 0x02
-#define LPICF_PBSIZ_MASK 0x0c   /* Panel Bus Width */
-#define   LPICF_PBSIZ_1    0x00
-#define   LPICF_PBSIZ_2    0x04
-#define   LPICF_PBSIZ_4    0x08
-
-/*
- * LCD Polarity Configuration Register 
- */
-#define LPOLCF_ADDR     0xfffffa21
-#define LPOLCF          BYTE_REF(LPOLCF_ADDR)
-
-#define LPOLCF_PIXPOL   0x01    /* Pixel Polarity */
-#define LPOLCF_LPPOL    0x02    /* Line Pulse Polarity */
-#define LPOLCF_FLMPOL   0x04    /* Frame Marker Polarity */
-#define LPOLCF_LCKPOL   0x08    /* LCD Shift Lock Polarity */
-
-/*
- * LACD (LCD Alternate Crystal Direction) Rate Control Register
- */
-#define LACDRC_ADDR     0xfffffa23
-#define LACDRC          BYTE_REF(LACDRC_ADDR)
-
-#define LACDRC_ACDSLT    0x80   /* Signal Source Select */
-#define LACDRC_ACD_MASK  0x0f   /* Alternate Crystal Direction Control */
-#define LACDRC_ACD_SHIFT 0
-
-/*
- * LCD Pixel Clock Divider Register
- */
-#define LPXCD_ADDR      0xfffffa25
-#define LPXCD           BYTE_REF(LPXCD_ADDR)
-
-#define LPXCD_PCD_MASK  0x3f    /* Pixel Clock Divider */
-#define LPXCD_PCD_SHIFT 0
-
-/*
- * LCD Clocking Control Register
- */
-#define LCKCON_ADDR     0xfffffa27
-#define LCKCON          BYTE_REF(LCKCON_ADDR)
-
-#define LCKCON_DWS_MASK  0x0f   /* Display Wait-State */
-#define LCKCON_DWS_SHIFT 0
-#define LCKCON_DWIDTH    0x40   /* Display Memory Width  */
-#define LCKCON_LCDON     0x80   /* Enable LCD Controller */
-
-/* '328-compatible definitions */
-#define LCKCON_DW_MASK  LCKCON_DWS_MASK
-#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
- 
-/*
- * LCD Refresh Rate Adjustment Register 
- */
-#define LRRA_ADDR       0xfffffa29
-#define LRRA            BYTE_REF(LRRA_ADDR)
-
-/*
- * LCD Panning Offset Register
- */
-#define LPOSR_ADDR      0xfffffa2d
-#define LPOSR           BYTE_REF(LPOSR_ADDR)
-
-#define LPOSR_POS_MASK  0x0f    /* Pixel Offset Code */
-#define LPOSR_POS_SHIFT 0
-
-/*
- * LCD Frame Rate Control Modulation Register
- */
-#define LFRCM_ADDR      0xfffffa31
-#define LFRCM           BYTE_REF(LFRCM_ADDR)
-
-#define LFRCM_YMOD_MASK  0x0f   /* Vertical Modulation */
-#define LFRCM_YMOD_SHIFT 0
-#define LFRCM_XMOD_MASK  0xf0   /* Horizontal Modulation */
-#define LFRCM_XMOD_SHIFT 4
-
-/*
- * LCD Gray Palette Mapping Register
- */
-#define LGPMR_ADDR      0xfffffa33
-#define LGPMR           BYTE_REF(LGPMR_ADDR)
-
-#define LGPMR_G1_MASK   0x0f
-#define LGPMR_G1_SHIFT  0
-#define LGPMR_G2_MASK   0xf0
-#define LGPMR_G2_SHIFT  4
-
-/* 
- * PWM Contrast Control Register
- */
-#define PWMR_ADDR       0xfffffa36
-#define PWMR            WORD_REF(PWMR_ADDR)
-
-#define PWMR_PW_MASK    0x00ff  /* Pulse Width */
-#define PWMR_PW_SHIFT   0
-#define PWMR_CCPEN      0x0100  /* Contrast Control Enable */
-#define PWMR_SRC_MASK   0x0600  /* Input Clock Source */
-#define   PWMR_SRC_LINE   0x0000        /* Line Pulse  */
-#define   PWMR_SRC_PIXEL  0x0200        /* Pixel Clock */
-#define   PWMR_SRC_LCD    0x4000        /* LCD clock   */
-
-/**********
- *
- * 0xFFFFFBxx -- Real-Time Clock (RTC)
- *
- **********/
-
-/*
- * RTC Hours Minutes and Seconds Register
- */
-#define RTCTIME_ADDR    0xfffffb00
-#define RTCTIME         LONG_REF(RTCTIME_ADDR)
-
-#define RTCTIME_SECONDS_MASK    0x0000003f      /* Seconds */
-#define RTCTIME_SECONDS_SHIFT   0
-#define RTCTIME_MINUTES_MASK    0x003f0000      /* Minutes */
-#define RTCTIME_MINUTES_SHIFT   16
-#define RTCTIME_HOURS_MASK      0x1f000000      /* Hours */
-#define RTCTIME_HOURS_SHIFT     24
-
-/*
- *  RTC Alarm Register 
- */
-#define RTCALRM_ADDR    0xfffffb04
-#define RTCALRM         LONG_REF(RTCALRM_ADDR)
-
-#define RTCALRM_SECONDS_MASK    0x0000003f      /* Seconds */
-#define RTCALRM_SECONDS_SHIFT   0
-#define RTCALRM_MINUTES_MASK    0x003f0000      /* Minutes */
-#define RTCALRM_MINUTES_SHIFT   16
-#define RTCALRM_HOURS_MASK      0x1f000000      /* Hours */
-#define RTCALRM_HOURS_SHIFT     24
-
-/*
- * Watchdog Timer Register 
- */
-#define WATCHDOG_ADDR   0xfffffb0a
-#define WATCHDOG        WORD_REF(WATCHDOG_ADDR)
-
-#define WATCHDOG_EN     0x0001  /* Watchdog Enabled */
-#define WATCHDOG_ISEL   0x0002  /* Select the watchdog interrupt */
-#define WATCHDOG_INTF   0x0080  /* Watchdog interrupt occcured */
-#define WATCHDOG_CNT_MASK  0x0300       /* Watchdog Counter */
-#define WATCHDOG_CNT_SHIFT 8
-
-/*
- * RTC Control Register
- */
-#define RTCCTL_ADDR     0xfffffb0c
-#define RTCCTL          WORD_REF(RTCCTL_ADDR)
-
-#define RTCCTL_XTL      0x0020  /* Crystal Selection */
-#define RTCCTL_EN       0x0080  /* RTC Enable */
-
-/* '328-compatible definitions */
-#define RTCCTL_384      RTCCTL_XTL
-#define RTCCTL_ENABLE   RTCCTL_EN
-
-/*
- * RTC Interrupt Status Register 
- */
-#define RTCISR_ADDR     0xfffffb0e
-#define RTCISR          WORD_REF(RTCISR_ADDR)
-
-#define RTCISR_SW       0x0001  /* Stopwatch timed out */
-#define RTCISR_MIN      0x0002  /* 1-minute interrupt has occurred */
-#define RTCISR_ALM      0x0004  /* Alarm interrupt has occurred */
-#define RTCISR_DAY      0x0008  /* 24-hour rollover interrupt has occurred */
-#define RTCISR_1HZ      0x0010  /* 1Hz interrupt has occurred */
-#define RTCISR_HR       0x0020  /* 1-hour interrupt has occurred */
-#define RTCISR_SAM0     0x0100  /*   4Hz /   4.6875Hz interrupt has occurred */ 
-#define RTCISR_SAM1     0x0200  /*   8Hz /   9.3750Hz interrupt has occurred */ 
-#define RTCISR_SAM2     0x0400  /*  16Hz /  18.7500Hz interrupt has occurred */ 
-#define RTCISR_SAM3     0x0800  /*  32Hz /  37.5000Hz interrupt has occurred */ 
-#define RTCISR_SAM4     0x1000  /*  64Hz /  75.0000Hz interrupt has occurred */ 
-#define RTCISR_SAM5     0x2000  /* 128Hz / 150.0000Hz interrupt has occurred */ 
-#define RTCISR_SAM6     0x4000  /* 256Hz / 300.0000Hz interrupt has occurred */ 
-#define RTCISR_SAM7     0x8000  /* 512Hz / 600.0000Hz interrupt has occurred */ 
-
-/*
- * RTC Interrupt Enable Register
- */
-#define RTCIENR_ADDR    0xfffffb10
-#define RTCIENR         WORD_REF(RTCIENR_ADDR)
-
-#define RTCIENR_SW      0x0001  /* Stopwatch interrupt enable */
-#define RTCIENR_MIN     0x0002  /* 1-minute interrupt enable */
-#define RTCIENR_ALM     0x0004  /* Alarm interrupt enable */
-#define RTCIENR_DAY     0x0008  /* 24-hour rollover interrupt enable */
-#define RTCIENR_1HZ     0x0010  /* 1Hz interrupt enable */
-#define RTCIENR_HR      0x0020  /* 1-hour interrupt enable */
-#define RTCIENR_SAM0    0x0100  /*   4Hz /   4.6875Hz interrupt enable */ 
-#define RTCIENR_SAM1    0x0200  /*   8Hz /   9.3750Hz interrupt enable */ 
-#define RTCIENR_SAM2    0x0400  /*  16Hz /  18.7500Hz interrupt enable */ 
-#define RTCIENR_SAM3    0x0800  /*  32Hz /  37.5000Hz interrupt enable */ 
-#define RTCIENR_SAM4    0x1000  /*  64Hz /  75.0000Hz interrupt enable */ 
-#define RTCIENR_SAM5    0x2000  /* 128Hz / 150.0000Hz interrupt enable */ 
-#define RTCIENR_SAM6    0x4000  /* 256Hz / 300.0000Hz interrupt enable */ 
-#define RTCIENR_SAM7    0x8000  /* 512Hz / 600.0000Hz interrupt enable */ 
-
-/* 
- * Stopwatch Minutes Register
- */
-#define STPWCH_ADDR     0xfffffb12
-#define STPWCH          WORD_REF(STPWCH)
-
-#define STPWCH_CNT_MASK  0x003f /* Stopwatch countdown value */
-#define SPTWCH_CNT_SHIFT 0
-
-/*
- * RTC Day Count Register 
- */
-#define DAYR_ADDR       0xfffffb1a
-#define DAYR            WORD_REF(DAYR_ADDR)
-
-#define DAYR_DAYS_MASK  0x1ff   /* Day Setting */
-#define DAYR_DAYS_SHIFT 0
-
-/*
- * RTC Day Alarm Register 
- */
-#define DAYALARM_ADDR   0xfffffb1c
-#define DAYALARM        WORD_REF(DAYALARM_ADDR)
-
-#define DAYALARM_DAYSAL_MASK    0x01ff  /* Day Setting of the Alarm */
-#define DAYALARM_DAYSAL_SHIFT   0
-
-/**********
- *
- * 0xFFFFFCxx -- DRAM Controller
- *
- **********/
-
-/*
- * DRAM Memory Configuration Register 
- */
-#define DRAMMC_ADDR     0xfffffc00
-#define DRAMMC          WORD_REF(DRAMMC_ADDR)
-
-#define DRAMMC_ROW12_MASK       0xc000  /* Row address bit for MD12 */
-#define   DRAMMC_ROW12_PA10     0x0000
-#define   DRAMMC_ROW12_PA21     0x4000  
-#define   DRAMMC_ROW12_PA23     0x8000
-#define DRAMMC_ROW0_MASK        0x3000  /* Row address bit for MD0 */
-#define   DRAMMC_ROW0_PA11      0x0000
-#define   DRAMMC_ROW0_PA22      0x1000
-#define   DRAMMC_ROW0_PA23      0x2000
-#define DRAMMC_ROW11            0x0800  /* Row address bit for MD11 PA20/PA22 */
-#define DRAMMC_ROW10            0x0400  /* Row address bit for MD10 PA19/PA21 */
-#define DRAMMC_ROW9             0x0200  /* Row address bit for MD9  PA9/PA19  */
-#define DRAMMC_ROW8             0x0100  /* Row address bit for MD8  PA10/PA20 */
-#define DRAMMC_COL10            0x0080  /* Col address bit for MD10 PA11/PA0  */
-#define DRAMMC_COL9             0x0040  /* Col address bit for MD9  PA10/PA0  */
-#define DRAMMC_COL8             0x0020  /* Col address bit for MD8  PA9/PA0   */
-#define DRAMMC_REF_MASK         0x001f  /* Reresh Cycle */
-#define DRAMMC_REF_SHIFT        0
-
-/*
- * DRAM Control Register
- */
-#define DRAMC_ADDR      0xfffffc02
-#define DRAMC           WORD_REF(DRAMC_ADDR)
-
-#define DRAMC_DWE          0x0001       /* DRAM Write Enable */
-#define DRAMC_RST          0x0002       /* Reset Burst Refresh Enable */
-#define DRAMC_LPR          0x0004       /* Low-Power Refresh Enable */
-#define DRAMC_SLW          0x0008       /* Slow RAM */
-#define DRAMC_LSP          0x0010       /* Light Sleep */
-#define DRAMC_MSW          0x0020       /* Slow Multiplexing */
-#define DRAMC_WS_MASK      0x00c0       /* Wait-states */
-#define DRAMC_WS_SHIFT     6
-#define DRAMC_PGSZ_MASK    0x0300       /* Page Size for fast page mode */
-#define DRAMC_PGSZ_SHIFT   8
-#define   DRAMC_PGSZ_256K  0x0000       
-#define   DRAMC_PGSZ_512K  0x0100
-#define   DRAMC_PGSZ_1024K 0x0200
-#define   DRAMC_PGSZ_2048K 0x0300
-#define DRAMC_EDO          0x0400       /* EDO DRAM */
-#define DRAMC_CLK          0x0800       /* Refresh Timer Clock source select */
-#define DRAMC_BC_MASK      0x3000       /* Page Access Clock Cycle (FP mode) */
-#define DRAMC_BC_SHIFT     12
-#define DRAMC_RM           0x4000       /* Refresh Mode */
-#define DRAMC_EN           0x8000       /* DRAM Controller enable */
-
-
-/**********
- *
- * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
- *
- **********/
-
-/*
- * ICE Module Address Compare Register
- */
-#define ICEMACR_ADDR    0xfffffd00
-#define ICEMACR         LONG_REF(ICEMACR_ADDR)
-
-/*
- * ICE Module Address Mask Register
- */
-#define ICEMAMR_ADDR    0xfffffd04
-#define ICEMAMR         LONG_REF(ICEMAMR_ADDR)
-
-/*
- * ICE Module Control Compare Register
- */
-#define ICEMCCR_ADDR    0xfffffd08
-#define ICEMCCR         WORD_REF(ICEMCCR_ADDR)
-
-#define ICEMCCR_PD      0x0001  /* Program/Data Cycle Selection */
-#define ICEMCCR_RW      0x0002  /* Read/Write Cycle Selection */
-
-/*
- * ICE Module Control Mask Register
- */
-#define ICEMCMR_ADDR    0xfffffd0a
-#define ICEMCMR         WORD_REF(ICEMCMR_ADDR)
-
-#define ICEMCMR_PDM     0x0001  /* Program/Data Cycle Mask */
-#define ICEMCMR_RWM     0x0002  /* Read/Write Cycle Mask */
-
-/*
- * ICE Module Control Register 
- */
-#define ICEMCR_ADDR     0xfffffd0c
-#define ICEMCR          WORD_REF(ICEMCR_ADDR)
-
-#define ICEMCR_CEN      0x0001  /* Compare Enable */
-#define ICEMCR_PBEN     0x0002  /* Program Break Enable */
-#define ICEMCR_SB       0x0004  /* Single Breakpoint */
-#define ICEMCR_HMDIS    0x0008  /* HardMap disable */
-#define ICEMCR_BBIEN    0x0010  /* Bus Break Interrupt Enable */
-
-/*
- * ICE Module Status Register 
- */
-#define ICEMSR_ADDR     0xfffffd0e
-#define ICEMSR          WORD_REF(ICEMSR_ADDR)
-
-#define ICEMSR_EMUEN    0x0001  /* Emulation Enable */
-#define ICEMSR_BRKIRQ   0x0002  /* A-Line Vector Fetch Detected */
-#define ICEMSR_BBIRQ    0x0004  /* Bus Break Interrupt Detected */
-#define ICEMSR_EMIRQ    0x0008  /* EMUIRQ Falling Edge Detected */
-
-#endif /* _MC68EZ328_H_ */
diff --git a/arch/m68knommu/include/asm/MC68VZ328.h b/arch/m68knommu/include/asm/MC68VZ328.h
deleted file mode 100644
index 2b9bf626a0a5..000000000000
--- a/arch/m68knommu/include/asm/MC68VZ328.h
+++ /dev/null
@@ -1,1349 +0,0 @@
-
-/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
- *
- * Copyright (c) 2000-2001      Lineo Inc. <www.lineo.com>
- * Copyright (c) 2000-2001      Lineo Canada Corp. <www.lineo.ca>
- * Copyright (C) 1999           Vladimir Gurevich <vgurevic@cisco.com>
- *                              Bare & Hare Software, Inc.
- * Based on include/asm-m68knommu/MC68332.h
- * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
- *                     The Silver Hammer Group, Ltd.
- *
- * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
- * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
- */
-
-#ifndef _MC68VZ328_H_
-#define _MC68VZ328_H_
-
-#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
-#define WORD_REF(addr) (*((volatile unsigned short*)addr))
-#define LONG_REF(addr) (*((volatile unsigned long*)addr))
-
-#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
-#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
-
-/********** 
- *
- * 0xFFFFF0xx -- System Control
- *
- **********/
- 
-/*
- * System Control Register (SCR)
- */
-#define SCR_ADDR        0xfffff000
-#define SCR             BYTE_REF(SCR_ADDR)
-
-#define SCR_WDTH8       0x01    /* 8-Bit Width Select */
-#define SCR_DMAP        0x04    /* Double Map */
-#define SCR_SO          0x08    /* Supervisor Only */
-#define SCR_BETEN       0x10    /* Bus-Error Time-Out Enable */
-#define SCR_PRV         0x20    /* Privilege Violation */
-#define SCR_WPV         0x40    /* Write Protect Violation */
-#define SCR_BETO        0x80    /* Bus-Error TimeOut */
-
-/*
- * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
- */
-#define MRR_ADDR 0xfffff004
-#define MRR      LONG_REF(MRR_ADDR)
-
-/********** 
- *
- * 0xFFFFF1xx -- Chip-Select logic
- *
- **********/
- 
-/*
- * Chip Select Group Base Registers 
- */
-#define CSGBA_ADDR      0xfffff100
-#define CSGBB_ADDR      0xfffff102
-
-#define CSGBC_ADDR      0xfffff104
-#define CSGBD_ADDR      0xfffff106
-
-#define CSGBA           WORD_REF(CSGBA_ADDR)
-#define CSGBB           WORD_REF(CSGBB_ADDR)
-#define CSGBC           WORD_REF(CSGBC_ADDR)
-#define CSGBD           WORD_REF(CSGBD_ADDR)
-
-/*
- * Chip Select Registers 
- */
-#define CSA_ADDR        0xfffff110
-#define CSB_ADDR        0xfffff112
-#define CSC_ADDR        0xfffff114
-#define CSD_ADDR        0xfffff116
-
-#define CSA             WORD_REF(CSA_ADDR)
-#define CSB             WORD_REF(CSB_ADDR)
-#define CSC             WORD_REF(CSC_ADDR)
-#define CSD             WORD_REF(CSD_ADDR)
-
-#define CSA_EN          0x0001          /* Chip-Select Enable */
-#define CSA_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSA_SIZ_SHIFT   1
-#define CSA_WS_MASK     0x0070          /* Wait State */
-#define CSA_WS_SHIFT    4
-#define CSA_BSW         0x0080          /* Data Bus Width */
-#define CSA_FLASH       0x0100          /* FLASH Memory Support */
-#define CSA_RO          0x8000          /* Read-Only */
-
-#define CSB_EN          0x0001          /* Chip-Select Enable */
-#define CSB_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSB_SIZ_SHIFT   1
-#define CSB_WS_MASK     0x0070          /* Wait State */
-#define CSB_WS_SHIFT    4
-#define CSB_BSW         0x0080          /* Data Bus Width */
-#define CSB_FLASH       0x0100          /* FLASH Memory Support */
-#define CSB_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
-#define CSB_UPSIZ_SHIFT 11
-#define CSB_ROP         0x2000          /* Readonly if protected */
-#define CSB_SOP         0x4000          /* Supervisor only if protected */
-#define CSB_RO          0x8000          /* Read-Only */
-
-#define CSC_EN          0x0001          /* Chip-Select Enable */
-#define CSC_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSC_SIZ_SHIFT   1
-#define CSC_WS_MASK     0x0070          /* Wait State */
-#define CSC_WS_SHIFT    4
-#define CSC_BSW         0x0080          /* Data Bus Width */
-#define CSC_FLASH       0x0100          /* FLASH Memory Support */
-#define CSC_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
-#define CSC_UPSIZ_SHIFT 11
-#define CSC_ROP         0x2000          /* Readonly if protected */
-#define CSC_SOP         0x4000          /* Supervisor only if protected */
-#define CSC_RO          0x8000          /* Read-Only */
-
-#define CSD_EN          0x0001          /* Chip-Select Enable */
-#define CSD_SIZ_MASK    0x000e          /* Chip-Select Size */
-#define CSD_SIZ_SHIFT   1
-#define CSD_WS_MASK     0x0070          /* Wait State */
-#define CSD_WS_SHIFT    4
-#define CSD_BSW         0x0080          /* Data Bus Width */
-#define CSD_FLASH       0x0100          /* FLASH Memory Support */
-#define CSD_DRAM        0x0200          /* Dram Selection */
-#define CSD_COMB        0x0400          /* Combining */
-#define CSD_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
-#define CSD_UPSIZ_SHIFT 11
-#define CSD_ROP         0x2000          /* Readonly if protected */
-#define CSD_SOP         0x4000          /* Supervisor only if protected */
-#define CSD_RO          0x8000          /* Read-Only */
-
-/*
- * Emulation Chip-Select Register 
- */
-#define EMUCS_ADDR      0xfffff118
-#define EMUCS           WORD_REF(EMUCS_ADDR)
-
-#define EMUCS_WS_MASK   0x0070
-#define EMUCS_WS_SHIFT  4
-
-/********** 
- *
- * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
- *
- **********/
-
-/*
- * PLL Control Register 
- */
-#define PLLCR_ADDR      0xfffff200
-#define PLLCR           WORD_REF(PLLCR_ADDR)
-
-#define PLLCR_DISPLL           0x0008   /* Disable PLL */
-#define PLLCR_CLKEN            0x0010   /* Clock (CLKO pin) enable */
-#define PLLCR_PRESC            0x0020   /* VCO prescaler */
-#define PLLCR_SYSCLK_SEL_MASK  0x0700   /* System Clock Selection */
-#define PLLCR_SYSCLK_SEL_SHIFT 8
-#define PLLCR_LCDCLK_SEL_MASK  0x3800   /* LCD Clock Selection */
-#define PLLCR_LCDCLK_SEL_SHIFT 11
-
-/* '328-compatible definitions */
-#define PLLCR_PIXCLK_SEL_MASK   PLLCR_LCDCLK_SEL_MASK
-#define PLLCR_PIXCLK_SEL_SHIFT  PLLCR_LCDCLK_SEL_SHIFT
-
-/*
- * PLL Frequency Select Register
- */
-#define PLLFSR_ADDR     0xfffff202
-#define PLLFSR          WORD_REF(PLLFSR_ADDR)
-
-#define PLLFSR_PC_MASK  0x00ff          /* P Count */
-#define PLLFSR_PC_SHIFT 0
-#define PLLFSR_QC_MASK  0x0f00          /* Q Count */
-#define PLLFSR_QC_SHIFT 8
-#define PLLFSR_PROT     0x4000          /* Protect P & Q */
-#define PLLFSR_CLK32    0x8000          /* Clock 32 (kHz) */
-
-/*
- * Power Control Register
- */
-#define PCTRL_ADDR      0xfffff207
-#define PCTRL           BYTE_REF(PCTRL_ADDR)
-
-#define PCTRL_WIDTH_MASK        0x1f    /* CPU Clock bursts width */
-#define PCTRL_WIDTH_SHIFT       0
-#define PCTRL_PCEN              0x80    /* Power Control Enable */
-
-/**********
- *
- * 0xFFFFF3xx -- Interrupt Controller
- *
- **********/
-
-/* 
- * Interrupt Vector Register
- */
-#define IVR_ADDR        0xfffff300
-#define IVR             BYTE_REF(IVR_ADDR)
-
-#define IVR_VECTOR_MASK 0xF8
-
-/*
- * Interrupt control Register
- */
-#define ICR_ADDR        0xfffff302
-#define ICR             WORD_REF(ICR_ADDR)
-
-#define ICR_POL5        0x0080  /* Polarity Control for IRQ5 */
-#define ICR_ET6         0x0100  /* Edge Trigger Select for IRQ6 */
-#define ICR_ET3         0x0200  /* Edge Trigger Select for IRQ3 */
-#define ICR_ET2         0x0400  /* Edge Trigger Select for IRQ2 */
-#define ICR_ET1         0x0800  /* Edge Trigger Select for IRQ1 */
-#define ICR_POL6        0x1000  /* Polarity Control for IRQ6 */
-#define ICR_POL3        0x2000  /* Polarity Control for IRQ3 */
-#define ICR_POL2        0x4000  /* Polarity Control for IRQ2 */
-#define ICR_POL1        0x8000  /* Polarity Control for IRQ1 */
-
-/*
- * Interrupt Mask Register
- */
-#define IMR_ADDR        0xfffff304
-#define IMR             LONG_REF(IMR_ADDR)
-
-/*
- * Define the names for bit positions first. This is useful for 
- * request_irq
- */
-#define SPI2_IRQ_NUM    0       /* SPI 2 interrupt */
-#define TMR_IRQ_NUM     1       /* Timer 1 interrupt */
-#define UART1_IRQ_NUM   2       /* UART 1 interrupt */  
-#define WDT_IRQ_NUM     3       /* Watchdog Timer interrupt */
-#define RTC_IRQ_NUM     4       /* RTC interrupt */
-#define TMR2_IRQ_NUM    5       /* Timer 2 interrupt */
-#define KB_IRQ_NUM      6       /* Keyboard Interrupt */
-#define PWM1_IRQ_NUM    7       /* Pulse-Width Modulator 1 int. */
-#define INT0_IRQ_NUM    8       /* External INT0 */
-#define INT1_IRQ_NUM    9       /* External INT1 */
-#define INT2_IRQ_NUM    10      /* External INT2 */
-#define INT3_IRQ_NUM    11      /* External INT3 */
-#define UART2_IRQ_NUM   12      /* UART 2 interrupt */  
-#define PWM2_IRQ_NUM    13      /* Pulse-Width Modulator 1 int. */
-#define IRQ1_IRQ_NUM    16      /* IRQ1 */
-#define IRQ2_IRQ_NUM    17      /* IRQ2 */
-#define IRQ3_IRQ_NUM    18      /* IRQ3 */
-#define IRQ6_IRQ_NUM    19      /* IRQ6 */
-#define IRQ5_IRQ_NUM    20      /* IRQ5 */
-#define SPI1_IRQ_NUM    21      /* SPI 1 interrupt */
-#define SAM_IRQ_NUM     22      /* Sampling Timer for RTC */
-#define EMIQ_IRQ_NUM    23      /* Emulator Interrupt */
-
-#define SPI_IRQ_NUM     SPI2_IRQ_NUM
-
-/* '328-compatible definitions */
-#define SPIM_IRQ_NUM    SPI_IRQ_NUM
-#define TMR1_IRQ_NUM    TMR_IRQ_NUM
-#define UART_IRQ_NUM    UART1_IRQ_NUM
-
-/* 
- * Here go the bitmasks themselves
- */
-#define IMR_MSPI        (1 << SPI_IRQ_NUM)      /* Mask SPI interrupt */
-#define IMR_MTMR        (1 << TMR_IRQ_NUM)      /* Mask Timer interrupt */
-#define IMR_MUART       (1 << UART_IRQ_NUM)     /* Mask UART interrupt */       
-#define IMR_MWDT        (1 << WDT_IRQ_NUM)      /* Mask Watchdog Timer interrupt */
-#define IMR_MRTC        (1 << RTC_IRQ_NUM)      /* Mask RTC interrupt */
-#define IMR_MKB         (1 << KB_IRQ_NUM)       /* Mask Keyboard Interrupt */
-#define IMR_MPWM        (1 << PWM_IRQ_NUM)      /* Mask Pulse-Width Modulator int. */
-#define IMR_MINT0       (1 << INT0_IRQ_NUM)     /* Mask External INT0 */
-#define IMR_MINT1       (1 << INT1_IRQ_NUM)     /* Mask External INT1 */
-#define IMR_MINT2       (1 << INT2_IRQ_NUM)     /* Mask External INT2 */
-#define IMR_MINT3       (1 << INT3_IRQ_NUM)     /* Mask External INT3 */
-#define IMR_MIRQ1       (1 << IRQ1_IRQ_NUM)     /* Mask IRQ1 */
-#define IMR_MIRQ2       (1 << IRQ2_IRQ_NUM)     /* Mask IRQ2 */
-#define IMR_MIRQ3       (1 << IRQ3_IRQ_NUM)     /* Mask IRQ3 */
-#define IMR_MIRQ6       (1 << IRQ6_IRQ_NUM)     /* Mask IRQ6 */
-#define IMR_MIRQ5       (1 << IRQ5_IRQ_NUM)     /* Mask IRQ5 */
-#define IMR_MSAM        (1 << SAM_IRQ_NUM)      /* Mask Sampling Timer for RTC */
-#define IMR_MEMIQ       (1 << EMIQ_IRQ_NUM)     /* Mask Emulator Interrupt */
-
-/* '328-compatible definitions */
-#define IMR_MSPIM       IMR_MSPI
-#define IMR_MTMR1       IMR_MTMR
-
-/* 
- * Interrupt Status Register 
- */
-#define ISR_ADDR        0xfffff30c
-#define ISR             LONG_REF(ISR_ADDR)
-
-#define ISR_SPI         (1 << SPI_IRQ_NUM)      /* SPI interrupt */
-#define ISR_TMR         (1 << TMR_IRQ_NUM)      /* Timer interrupt */
-#define ISR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */    
-#define ISR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
-#define ISR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
-#define ISR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
-#define ISR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator interrupt */
-#define ISR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
-#define ISR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
-#define ISR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
-#define ISR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
-#define ISR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
-#define ISR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
-#define ISR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
-#define ISR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
-#define ISR_IRQ5        (1 << IRQ5_IRQ_NUM)     /* IRQ5 */
-#define ISR_SAM         (1 << SAM_IRQ_NUM)      /* Sampling Timer for RTC */
-#define ISR_EMIQ        (1 << EMIQ_IRQ_NUM)     /* Emulator Interrupt */
-
-/* '328-compatible definitions */
-#define ISR_SPIM        ISR_SPI
-#define ISR_TMR1        ISR_TMR
-
-/* 
- * Interrupt Pending Register 
- */
-#define IPR_ADDR        0xfffff30c
-#define IPR             LONG_REF(IPR_ADDR)
-
-#define IPR_SPI         (1 << SPI_IRQ_NUM)      /* SPI interrupt */
-#define IPR_TMR         (1 << TMR_IRQ_NUM)      /* Timer interrupt */
-#define IPR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */    
-#define IPR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
-#define IPR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
-#define IPR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
-#define IPR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator interrupt */
-#define IPR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
-#define IPR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
-#define IPR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
-#define IPR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
-#define IPR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
-#define IPR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
-#define IPR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
-#define IPR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
-#define IPR_IRQ5        (1 << IRQ5_IRQ_NUM)     /* IRQ5 */
-#define IPR_SAM         (1 << SAM_IRQ_NUM)      /* Sampling Timer for RTC */
-#define IPR_EMIQ        (1 << EMIQ_IRQ_NUM)     /* Emulator Interrupt */
-
-/* '328-compatible definitions */
-#define IPR_SPIM        IPR_SPI
-#define IPR_TMR1        IPR_TMR
-
-/**********
- *
- * 0xFFFFF4xx -- Parallel Ports
- *
- **********/
-
-/*
- * Port A
- */
-#define PADIR_ADDR      0xfffff400              /* Port A direction reg */
-#define PADATA_ADDR     0xfffff401              /* Port A data register */
-#define PAPUEN_ADDR     0xfffff402              /* Port A Pull-Up enable reg */
-
-#define PADIR           BYTE_REF(PADIR_ADDR)
-#define PADATA          BYTE_REF(PADATA_ADDR)
-#define PAPUEN          BYTE_REF(PAPUEN_ADDR)
-
-#define PA(x)           (1 << (x))
-
-/* 
- * Port B
- */
-#define PBDIR_ADDR      0xfffff408              /* Port B direction reg */
-#define PBDATA_ADDR     0xfffff409              /* Port B data register */
-#define PBPUEN_ADDR     0xfffff40a              /* Port B Pull-Up enable reg */
-#define PBSEL_ADDR      0xfffff40b              /* Port B Select Register */
-
-#define PBDIR           BYTE_REF(PBDIR_ADDR)
-#define PBDATA          BYTE_REF(PBDATA_ADDR)
-#define PBPUEN          BYTE_REF(PBPUEN_ADDR)
-#define PBSEL           BYTE_REF(PBSEL_ADDR)
-
-#define PB(x)           (1 << (x))
-
-#define PB_CSB0         0x01    /* Use CSB0      as PB[0] */
-#define PB_CSB1         0x02    /* Use CSB1      as PB[1] */
-#define PB_CSC0_RAS0    0x04    /* Use CSC0/RAS0 as PB[2] */    
-#define PB_CSC1_RAS1    0x08    /* Use CSC1/RAS1 as PB[3] */    
-#define PB_CSD0_CAS0    0x10    /* Use CSD0/CAS0 as PB[4] */    
-#define PB_CSD1_CAS1    0x20    /* Use CSD1/CAS1 as PB[5] */
-#define PB_TIN_TOUT     0x40    /* Use TIN/TOUT  as PB[6] */
-#define PB_PWMO         0x80    /* Use PWMO      as PB[7] */
-
-/* 
- * Port C
- */
-#define PCDIR_ADDR      0xfffff410              /* Port C direction reg */
-#define PCDATA_ADDR     0xfffff411              /* Port C data register */
-#define PCPDEN_ADDR     0xfffff412              /* Port C Pull-Down enb. reg */
-#define PCSEL_ADDR      0xfffff413              /* Port C Select Register */
-
-#define PCDIR           BYTE_REF(PCDIR_ADDR)
-#define PCDATA          BYTE_REF(PCDATA_ADDR)
-#define PCPDEN          BYTE_REF(PCPDEN_ADDR)
-#define PCSEL           BYTE_REF(PCSEL_ADDR)
-
-#define PC(x)           (1 << (x))
-
-#define PC_LD0          0x01    /* Use LD0  as PC[0] */
-#define PC_LD1          0x02    /* Use LD1  as PC[1] */
-#define PC_LD2          0x04    /* Use LD2  as PC[2] */
-#define PC_LD3          0x08    /* Use LD3  as PC[3] */
-#define PC_LFLM         0x10    /* Use LFLM as PC[4] */
-#define PC_LLP          0x20    /* Use LLP  as PC[5] */
-#define PC_LCLK         0x40    /* Use LCLK as PC[6] */
-#define PC_LACD         0x80    /* Use LACD as PC[7] */
-
-/* 
- * Port D
- */
-#define PDDIR_ADDR      0xfffff418              /* Port D direction reg */
-#define PDDATA_ADDR     0xfffff419              /* Port D data register */
-#define PDPUEN_ADDR     0xfffff41a              /* Port D Pull-Up enable reg */
-#define PDSEL_ADDR      0xfffff41b              /* Port D Select Register */
-#define PDPOL_ADDR      0xfffff41c              /* Port D Polarity Register */
-#define PDIRQEN_ADDR    0xfffff41d              /* Port D IRQ enable register */
-#define PDKBEN_ADDR     0xfffff41e              /* Port D Keyboard Enable reg */
-#define PDIQEG_ADDR     0xfffff41f              /* Port D IRQ Edge Register */
-
-#define PDDIR           BYTE_REF(PDDIR_ADDR)
-#define PDDATA          BYTE_REF(PDDATA_ADDR)
-#define PDPUEN          BYTE_REF(PDPUEN_ADDR)
-#define PDSEL           BYTE_REF(PDSEL_ADDR)
-#define PDPOL           BYTE_REF(PDPOL_ADDR)
-#define PDIRQEN         BYTE_REF(PDIRQEN_ADDR)
-#define PDKBEN          BYTE_REF(PDKBEN_ADDR)
-#define PDIQEG          BYTE_REF(PDIQEG_ADDR)
-
-#define PD(x)           (1 << (x))
-
-#define PD_INT0         0x01    /* Use INT0 as PD[0] */
-#define PD_INT1         0x02    /* Use INT1 as PD[1] */
-#define PD_INT2         0x04    /* Use INT2 as PD[2] */
-#define PD_INT3         0x08    /* Use INT3 as PD[3] */
-#define PD_IRQ1         0x10    /* Use IRQ1 as PD[4] */
-#define PD_IRQ2         0x20    /* Use IRQ2 as PD[5] */
-#define PD_IRQ3         0x40    /* Use IRQ3 as PD[6] */
-#define PD_IRQ6         0x80    /* Use IRQ6 as PD[7] */
-
-/* 
- * Port E
- */
-#define PEDIR_ADDR      0xfffff420              /* Port E direction reg */
-#define PEDATA_ADDR     0xfffff421              /* Port E data register */
-#define PEPUEN_ADDR     0xfffff422              /* Port E Pull-Up enable reg */
-#define PESEL_ADDR      0xfffff423              /* Port E Select Register */
-
-#define PEDIR           BYTE_REF(PEDIR_ADDR)
-#define PEDATA          BYTE_REF(PEDATA_ADDR)
-#define PEPUEN          BYTE_REF(PEPUEN_ADDR)
-#define PESEL           BYTE_REF(PESEL_ADDR)
-
-#define PE(x)           (1 << (x))
-
-#define PE_SPMTXD       0x01    /* Use SPMTXD as PE[0] */
-#define PE_SPMRXD       0x02    /* Use SPMRXD as PE[1] */
-#define PE_SPMCLK       0x04    /* Use SPMCLK as PE[2] */
-#define PE_DWE          0x08    /* Use DWE    as PE[3] */
-#define PE_RXD          0x10    /* Use RXD    as PE[4] */
-#define PE_TXD          0x20    /* Use TXD    as PE[5] */
-#define PE_RTS          0x40    /* Use RTS    as PE[6] */
-#define PE_CTS          0x80    /* Use CTS    as PE[7] */
-
-/* 
- * Port F
- */
-#define PFDIR_ADDR      0xfffff428              /* Port F direction reg */
-#define PFDATA_ADDR     0xfffff429              /* Port F data register */
-#define PFPUEN_ADDR     0xfffff42a              /* Port F Pull-Up enable reg */
-#define PFSEL_ADDR      0xfffff42b              /* Port F Select Register */
-
-#define PFDIR           BYTE_REF(PFDIR_ADDR)
-#define PFDATA          BYTE_REF(PFDATA_ADDR)
-#define PFPUEN          BYTE_REF(PFPUEN_ADDR)
-#define PFSEL           BYTE_REF(PFSEL_ADDR)
-
-#define PF(x)           (1 << (x))
-
-#define PF_LCONTRAST    0x01    /* Use LCONTRAST as PF[0] */
-#define PF_IRQ5         0x02    /* Use IRQ5      as PF[1] */
-#define PF_CLKO         0x04    /* Use CLKO      as PF[2] */
-#define PF_A20          0x08    /* Use A20       as PF[3] */
-#define PF_A21          0x10    /* Use A21       as PF[4] */
-#define PF_A22          0x20    /* Use A22       as PF[5] */
-#define PF_A23          0x40    /* Use A23       as PF[6] */
-#define PF_CSA1         0x80    /* Use CSA1      as PF[7] */
-
-/* 
- * Port G
- */
-#define PGDIR_ADDR      0xfffff430              /* Port G direction reg */
-#define PGDATA_ADDR     0xfffff431              /* Port G data register */
-#define PGPUEN_ADDR     0xfffff432              /* Port G Pull-Up enable reg */
-#define PGSEL_ADDR      0xfffff433              /* Port G Select Register */
-
-#define PGDIR           BYTE_REF(PGDIR_ADDR)
-#define PGDATA          BYTE_REF(PGDATA_ADDR)
-#define PGPUEN          BYTE_REF(PGPUEN_ADDR)
-#define PGSEL           BYTE_REF(PGSEL_ADDR)
-
-#define PG(x)           (1 << (x))
-
-#define PG_BUSW_DTACK   0x01    /* Use BUSW/DTACK as PG[0] */
-#define PG_A0           0x02    /* Use A0         as PG[1] */
-#define PG_EMUIRQ       0x04    /* Use EMUIRQ     as PG[2] */
-#define PG_HIZ_P_D      0x08    /* Use HIZ/P/D    as PG[3] */
-#define PG_EMUCS        0x10    /* Use EMUCS      as PG[4] */
-#define PG_EMUBRK       0x20    /* Use EMUBRK     as PG[5] */
-
-/* 
- * Port J
- */
-#define PJDIR_ADDR      0xfffff438              /* Port J direction reg */
-#define PJDATA_ADDR     0xfffff439              /* Port J data register */
-#define PJPUEN_ADDR     0xfffff43A              /* Port J Pull-Up enb. reg */
-#define PJSEL_ADDR      0xfffff43B              /* Port J Select Register */
-
-#define PJDIR           BYTE_REF(PJDIR_ADDR)
-#define PJDATA          BYTE_REF(PJDATA_ADDR)
-#define PJPUEN          BYTE_REF(PJPUEN_ADDR)
-#define PJSEL           BYTE_REF(PJSEL_ADDR)
-
-#define PJ(x)           (1 << (x))
-
-/*
- * Port K
- */
-#define PKDIR_ADDR      0xfffff440              /* Port K direction reg */
-#define PKDATA_ADDR     0xfffff441              /* Port K data register */
-#define PKPUEN_ADDR     0xfffff442              /* Port K Pull-Up enb. reg */
-#define PKSEL_ADDR      0xfffff443              /* Port K Select Register */
-
-#define PKDIR           BYTE_REF(PKDIR_ADDR)
-#define PKDATA          BYTE_REF(PKDATA_ADDR)
-#define PKPUEN          BYTE_REF(PKPUEN_ADDR)
-#define PKSEL           BYTE_REF(PKSEL_ADDR)
-
-#define PK(x)           (1 << (x))
-
-#define PK_DATAREADY            0x01    /* Use ~DATA_READY  as PK[0] */
-#define PK_PWM2         0x01    /* Use PWM2  as PK[0] */
-#define PK_R_W          0x02    /* Use R/W  as PK[1] */
-#define PK_LDS          0x04    /* Use /LDS  as PK[2] */
-#define PK_UDS          0x08    /* Use /UDS  as PK[3] */
-#define PK_LD4          0x10    /* Use LD4 as PK[4] */
-#define PK_LD5          0x20    /* Use LD5  as PK[5] */
-#define PK_LD6          0x40    /* Use LD6 as PK[6] */
-#define PK_LD7          0x80    /* Use LD7 as PK[7] */
-
-#define PJDIR_ADDR      0xfffff438              /* Port J direction reg */
-#define PJDATA_ADDR     0xfffff439              /* Port J data register */
-#define PJPUEN_ADDR     0xfffff43A              /* Port J Pull-Up enable reg */
-#define PJSEL_ADDR      0xfffff43B              /* Port J Select Register */
-
-#define PJDIR           BYTE_REF(PJDIR_ADDR)
-#define PJDATA          BYTE_REF(PJDATA_ADDR)
-#define PJPUEN          BYTE_REF(PJPUEN_ADDR)
-#define PJSEL           BYTE_REF(PJSEL_ADDR)
-
-#define PJ(x)           (1 << (x))
-
-#define PJ_MOSI         0x01    /* Use MOSI       as PJ[0] */
-#define PJ_MISO         0x02    /* Use MISO       as PJ[1] */
-#define PJ_SPICLK1      0x04    /* Use SPICLK1    as PJ[2] */
-#define PJ_SS           0x08    /* Use SS         as PJ[3] */
-#define PJ_RXD2         0x10    /* Use RXD2       as PJ[4] */
-#define PJ_TXD2         0x20    /* Use TXD2       as PJ[5] */
-#define PJ_RTS2         0x40    /* Use RTS2       as PJ[5] */
-#define PJ_CTS2         0x80    /* Use CTS2       as PJ[5] */
-
-/*
- * Port M
- */
-#define PMDIR_ADDR      0xfffff448              /* Port M direction reg */
-#define PMDATA_ADDR     0xfffff449              /* Port M data register */
-#define PMPUEN_ADDR     0xfffff44a              /* Port M Pull-Up enable reg */
-#define PMSEL_ADDR      0xfffff44b              /* Port M Select Register */
-
-#define PMDIR           BYTE_REF(PMDIR_ADDR)
-#define PMDATA          BYTE_REF(PMDATA_ADDR)
-#define PMPUEN          BYTE_REF(PMPUEN_ADDR)
-#define PMSEL           BYTE_REF(PMSEL_ADDR)
-
-#define PM(x)           (1 << (x))
-
-#define PM_SDCLK        0x01    /* Use SDCLK      as PM[0] */
-#define PM_SDCE         0x02    /* Use SDCE       as PM[1] */
-#define PM_DQMH         0x04    /* Use DQMH       as PM[2] */
-#define PM_DQML         0x08    /* Use DQML       as PM[3] */
-#define PM_SDA10        0x10    /* Use SDA10      as PM[4] */
-#define PM_DMOE         0x20    /* Use DMOE       as PM[5] */
-
-/**********
- *
- * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
- *
- **********/
-
-/*
- * PWM Control Register
- */
-#define PWMC_ADDR       0xfffff500
-#define PWMC            WORD_REF(PWMC_ADDR)
-
-#define PWMC_CLKSEL_MASK        0x0003  /* Clock Selection */
-#define PWMC_CLKSEL_SHIFT       0
-#define PWMC_REPEAT_MASK        0x000c  /* Sample Repeats */
-#define PWMC_REPEAT_SHIFT       2
-#define PWMC_EN                 0x0010  /* Enable PWM */
-#define PMNC_FIFOAV             0x0020  /* FIFO Available */
-#define PWMC_IRQEN              0x0040  /* Interrupt Request Enable */
-#define PWMC_IRQ                0x0080  /* Interrupt Request (FIFO empty) */
-#define PWMC_PRESCALER_MASK     0x7f00  /* Incoming Clock prescaler */
-#define PWMC_PRESCALER_SHIFT    8
-#define PWMC_CLKSRC             0x8000  /* Clock Source Select */
-
-/* '328-compatible definitions */
-#define PWMC_PWMEN      PWMC_EN
-
-/*
- * PWM Sample Register 
- */
-#define PWMS_ADDR       0xfffff502
-#define PWMS            WORD_REF(PWMS_ADDR)
-
-/*
- * PWM Period Register
- */
-#define PWMP_ADDR       0xfffff504
-#define PWMP            BYTE_REF(PWMP_ADDR)
-
-/*
- * PWM Counter Register
- */
-#define PWMCNT_ADDR     0xfffff505
-#define PWMCNT          BYTE_REF(PWMCNT_ADDR)
-
-/**********
- *
- * 0xFFFFF6xx -- General-Purpose Timer
- *
- **********/
-
-/* 
- * Timer Control register
- */
-#define TCTL_ADDR       0xfffff600
-#define TCTL            WORD_REF(TCTL_ADDR)
-
-#define TCTL_TEN                0x0001  /* Timer Enable  */
-#define TCTL_CLKSOURCE_MASK     0x000e  /* Clock Source: */
-#define   TCTL_CLKSOURCE_STOP      0x0000       /* Stop count (disabled)    */
-#define   TCTL_CLKSOURCE_SYSCLK    0x0002       /* SYSCLK to prescaler      */
-#define   TCTL_CLKSOURCE_SYSCLK_16 0x0004       /* SYSCLK/16 to prescaler   */
-#define   TCTL_CLKSOURCE_TIN       0x0006       /* TIN to prescaler         */
-#define   TCTL_CLKSOURCE_32KHZ     0x0008       /* 32kHz clock to prescaler */
-#define TCTL_IRQEN              0x0010  /* IRQ Enable    */
-#define TCTL_OM                 0x0020  /* Output Mode   */
-#define TCTL_CAP_MASK           0x00c0  /* Capture Edge: */
-#define   TCTL_CAP_RE           0x0040          /* Capture on rizing edge   */
-#define   TCTL_CAP_FE           0x0080          /* Capture on falling edge  */
-#define TCTL_FRR                0x0010  /* Free-Run Mode */
-
-/* '328-compatible definitions */
-#define TCTL1_ADDR      TCTL_ADDR
-#define TCTL1           TCTL
-
-/*
- * Timer Prescaler Register
- */
-#define TPRER_ADDR      0xfffff602
-#define TPRER           WORD_REF(TPRER_ADDR)
-
-/* '328-compatible definitions */
-#define TPRER1_ADDR     TPRER_ADDR
-#define TPRER1          TPRER
-
-/*
- * Timer Compare Register
- */
-#define TCMP_ADDR       0xfffff604
-#define TCMP            WORD_REF(TCMP_ADDR)
-
-/* '328-compatible definitions */
-#define TCMP1_ADDR      TCMP_ADDR
-#define TCMP1           TCMP
-
-/*
- * Timer Capture register
- */
-#define TCR_ADDR        0xfffff606
-#define TCR             WORD_REF(TCR_ADDR)
-
-/* '328-compatible definitions */
-#define TCR1_ADDR       TCR_ADDR
-#define TCR1            TCR
-
-/*
- * Timer Counter Register
- */
-#define TCN_ADDR        0xfffff608
-#define TCN             WORD_REF(TCN_ADDR)
-
-/* '328-compatible definitions */
-#define TCN1_ADDR       TCN_ADDR
-#define TCN1            TCN
-
-/*
- * Timer Status Register
- */
-#define TSTAT_ADDR      0xfffff60a
-#define TSTAT           WORD_REF(TSTAT_ADDR)
-
-#define TSTAT_COMP      0x0001          /* Compare Event occurred */
-#define TSTAT_CAPT      0x0001          /* Capture Event occurred */
-
-/* '328-compatible definitions */
-#define TSTAT1_ADDR     TSTAT_ADDR
-#define TSTAT1          TSTAT
-
-/**********
- *
- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
- *
- **********/
-
-/*
- * SPIM Data Register
- */
-#define SPIMDATA_ADDR   0xfffff800
-#define SPIMDATA        WORD_REF(SPIMDATA_ADDR)
-
-/*
- * SPIM Control/Status Register
- */
-#define SPIMCONT_ADDR   0xfffff802
-#define SPIMCONT        WORD_REF(SPIMCONT_ADDR)
-
-#define SPIMCONT_BIT_COUNT_MASK  0x000f /* Transfer Length in Bytes */
-#define SPIMCONT_BIT_COUNT_SHIFT 0
-#define SPIMCONT_POL             0x0010 /* SPMCLK Signel Polarity */
-#define SPIMCONT_PHA             0x0020 /* Clock/Data phase relationship */
-#define SPIMCONT_IRQEN           0x0040 /* IRQ Enable */
-#define SPIMCONT_IRQ             0x0080 /* Interrupt Request */
-#define SPIMCONT_XCH             0x0100 /* Exchange */
-#define SPIMCONT_ENABLE          0x0200 /* Enable SPIM */
-#define SPIMCONT_DATA_RATE_MASK  0xe000 /* SPIM Data Rate */
-#define SPIMCONT_DATA_RATE_SHIFT 13
-
-/* '328-compatible definitions */
-#define SPIMCONT_SPIMIRQ        SPIMCONT_IRQ
-#define SPIMCONT_SPIMEN         SPIMCONT_ENABLE
-
-/**********
- *
- * 0xFFFFF9xx -- UART
- *
- **********/
-
-/*
- * UART Status/Control Register
- */
-
-#define USTCNT_ADDR     0xfffff900
-#define USTCNT          WORD_REF(USTCNT_ADDR)
-
-#define USTCNT_TXAE     0x0001  /* Transmitter Available Interrupt Enable */
-#define USTCNT_TXHE     0x0002  /* Transmitter Half Empty Enable */
-#define USTCNT_TXEE     0x0004  /* Transmitter Empty Interrupt Enable */
-#define USTCNT_RXRE     0x0008  /* Receiver Ready Interrupt Enable */
-#define USTCNT_RXHE     0x0010  /* Receiver Half-Full Interrupt Enable */
-#define USTCNT_RXFE     0x0020  /* Receiver Full Interrupt Enable */
-#define USTCNT_CTSD     0x0040  /* CTS Delta Interrupt Enable */
-#define USTCNT_ODEN     0x0080  /* Old Data Interrupt Enable */
-#define USTCNT_8_7      0x0100  /* Eight or seven-bit transmission */
-#define USTCNT_STOP     0x0200  /* Stop bit transmission */
-#define USTCNT_ODD      0x0400  /* Odd Parity */
-#define USTCNT_PEN      0x0800  /* Parity Enable */
-#define USTCNT_CLKM     0x1000  /* Clock Mode Select */
-#define USTCNT_TXEN     0x2000  /* Transmitter Enable */
-#define USTCNT_RXEN     0x4000  /* Receiver Enable */
-#define USTCNT_UEN      0x8000  /* UART Enable */
-
-/* '328-compatible definitions */
-#define USTCNT_TXAVAILEN        USTCNT_TXAE
-#define USTCNT_TXHALFEN         USTCNT_TXHE
-#define USTCNT_TXEMPTYEN        USTCNT_TXEE
-#define USTCNT_RXREADYEN        USTCNT_RXRE
-#define USTCNT_RXHALFEN         USTCNT_RXHE
-#define USTCNT_RXFULLEN         USTCNT_RXFE
-#define USTCNT_CTSDELTAEN       USTCNT_CTSD
-#define USTCNT_ODD_EVEN         USTCNT_ODD
-#define USTCNT_PARITYEN         USTCNT_PEN
-#define USTCNT_CLKMODE          USTCNT_CLKM
-#define USTCNT_UARTEN           USTCNT_UEN
-
-/*
- * UART Baud Control Register
- */
-#define UBAUD_ADDR      0xfffff902
-#define UBAUD           WORD_REF(UBAUD_ADDR)
-
-#define UBAUD_PRESCALER_MASK    0x003f  /* Actual divisor is 65 - PRESCALER */
-#define UBAUD_PRESCALER_SHIFT   0
-#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divizor */
-#define UBAUD_DIVIDE_SHIFT      8
-#define UBAUD_BAUD_SRC          0x0800  /* Baud Rate Source */
-#define UBAUD_UCLKDIR           0x2000  /* UCLK Direction */
-
-/*
- * UART Receiver Register 
- */
-#define URX_ADDR        0xfffff904
-#define URX             WORD_REF(URX_ADDR)
-
-#define URX_RXDATA_ADDR 0xfffff905
-#define URX_RXDATA      BYTE_REF(URX_RXDATA_ADDR)
-
-#define URX_RXDATA_MASK  0x00ff /* Received data */
-#define URX_RXDATA_SHIFT 0
-#define URX_PARITY_ERROR 0x0100 /* Parity Error */
-#define URX_BREAK        0x0200 /* Break Detected */
-#define URX_FRAME_ERROR  0x0400 /* Framing Error */
-#define URX_OVRUN        0x0800 /* Serial Overrun */
-#define URX_OLD_DATA     0x1000 /* Old data in FIFO */
-#define URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */
-#define URX_FIFO_HALF    0x4000 /* FIFO is Half-Full */
-#define URX_FIFO_FULL    0x8000 /* FIFO is Full */
-
-/*
- * UART Transmitter Register 
- */
-#define UTX_ADDR        0xfffff906
-#define UTX             WORD_REF(UTX_ADDR)
-
-#define UTX_TXDATA_ADDR 0xfffff907
-#define UTX_TXDATA      BYTE_REF(UTX_TXDATA_ADDR)
-
-#define UTX_TXDATA_MASK  0x00ff /* Data to be transmitted */
-#define UTX_TXDATA_SHIFT 0
-#define UTX_CTS_DELTA    0x0100 /* CTS changed */
-#define UTX_CTS_STAT     0x0200 /* CTS State */
-#define UTX_BUSY         0x0400 /* FIFO is busy, sending a character */
-#define UTX_NOCTS        0x0800 /* Ignore CTS */
-#define UTX_SEND_BREAK   0x1000 /* Send a BREAK */
-#define UTX_TX_AVAIL     0x2000 /* Transmit FIFO has a slot available */
-#define UTX_FIFO_HALF    0x4000 /* Transmit FIFO is half empty */
-#define UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */
-
-/* '328-compatible definitions */
-#define UTX_CTS_STATUS  UTX_CTS_STAT
-#define UTX_IGNORE_CTS  UTX_NOCTS
-
-/*
- * UART Miscellaneous Register 
- */
-#define UMISC_ADDR      0xfffff908
-#define UMISC           WORD_REF(UMISC_ADDR)
-
-#define UMISC_TX_POL     0x0004 /* Transmit Polarity */
-#define UMISC_RX_POL     0x0008 /* Receive Polarity */
-#define UMISC_IRDA_LOOP  0x0010 /* IrDA Loopback Enable */
-#define UMISC_IRDA_EN    0x0020 /* Infra-Red Enable */
-#define UMISC_RTS        0x0040 /* Set RTS status */
-#define UMISC_RTSCONT    0x0080 /* Choose RTS control */
-#define UMISC_IR_TEST    0x0400 /* IRDA Test Enable */
-#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
-#define UMISC_LOOP       0x1000 /* Serial Loopback Enable */
-#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
-#define UMISC_CLKSRC     0x4000 /* Clock Source */
-#define UMISC_BAUD_TEST  0x8000 /* Enable Baud Test Mode */
-
-/* 
- * UART Non-integer Prescaler Register
- */
-#define NIPR_ADDR       0xfffff90a
-#define NIPR            WORD_REF(NIPR_ADDR)
-
-#define NIPR_STEP_VALUE_MASK    0x00ff  /* NI prescaler step value */
-#define NIPR_STEP_VALUE_SHIFT   0
-#define NIPR_SELECT_MASK        0x0700  /* Tap Selection */
-#define NIPR_SELECT_SHIFT       8
-#define NIPR_PRE_SEL            0x8000  /* Non-integer prescaler select */
-
-
-/* generalization of uart control registers to support multiple ports: */
-typedef struct {
-  volatile unsigned short int ustcnt;
-  volatile unsigned short int ubaud;
-  union {
-    volatile unsigned short int w;
-    struct {
-      volatile unsigned char status;
-      volatile unsigned char rxdata;
-    } b;
-  } urx;
-  union {
-    volatile unsigned short int w;
-    struct {
-      volatile unsigned char status;
-      volatile unsigned char txdata;
-    } b;
-  } utx;
-  volatile unsigned short int umisc;
-  volatile unsigned short int nipr;
-  volatile unsigned short int hmark;
-  volatile unsigned short int unused;
-} __attribute__((packed)) m68328_uart;
-
-
-
-
-/**********
- *
- * 0xFFFFFAxx -- LCD Controller
- *
- **********/
-
-/*
- * LCD Screen Starting Address Register 
- */
-#define LSSA_ADDR       0xfffffa00
-#define LSSA            LONG_REF(LSSA_ADDR)
-
-#define LSSA_SSA_MASK   0x1ffffffe      /* Bits 0 and 29-31 are reserved */
-
-/*
- * LCD Virtual Page Width Register 
- */
-#define LVPW_ADDR       0xfffffa05
-#define LVPW            BYTE_REF(LVPW_ADDR)
-
-/*
- * LCD Screen Width Register (not compatible with '328 !!!) 
- */
-#define LXMAX_ADDR      0xfffffa08
-#define LXMAX           WORD_REF(LXMAX_ADDR)
-
-#define LXMAX_XM_MASK   0x02f0          /* Bits 0-3 and 10-15 are reserved */
-
-/*
- * LCD Screen Height Register
- */
-#define LYMAX_ADDR      0xfffffa0a
-#define LYMAX           WORD_REF(LYMAX_ADDR)
-
-#define LYMAX_YM_MASK   0x01ff          /* Bits 9-15 are reserved */
-
-/*
- * LCD Cursor X Position Register
- */
-#define LCXP_ADDR       0xfffffa18
-#define LCXP            WORD_REF(LCXP_ADDR)
-
-#define LCXP_CC_MASK    0xc000          /* Cursor Control */
-#define   LCXP_CC_TRAMSPARENT   0x0000
-#define   LCXP_CC_BLACK         0x4000
-#define   LCXP_CC_REVERSED      0x8000
-#define   LCXP_CC_WHITE         0xc000
-#define LCXP_CXP_MASK   0x02ff          /* Cursor X position */
-
-/*
- * LCD Cursor Y Position Register
- */
-#define LCYP_ADDR       0xfffffa1a
-#define LCYP            WORD_REF(LCYP_ADDR)
-
-#define LCYP_CYP_MASK   0x01ff          /* Cursor Y Position */
-
-/*
- * LCD Cursor Width and Heigth Register
- */
-#define LCWCH_ADDR      0xfffffa1c
-#define LCWCH           WORD_REF(LCWCH_ADDR)
-
-#define LCWCH_CH_MASK   0x001f          /* Cursor Height */
-#define LCWCH_CH_SHIFT  0
-#define LCWCH_CW_MASK   0x1f00          /* Cursor Width */
-#define LCWCH_CW_SHIFT  8
-
-/*
- * LCD Blink Control Register
- */
-#define LBLKC_ADDR      0xfffffa1f
-#define LBLKC           BYTE_REF(LBLKC_ADDR)
-
-#define LBLKC_BD_MASK   0x7f    /* Blink Divisor */
-#define LBLKC_BD_SHIFT  0
-#define LBLKC_BKEN      0x80    /* Blink Enabled */
-
-/*
- * LCD Panel Interface Configuration Register 
- */
-#define LPICF_ADDR      0xfffffa20
-#define LPICF           BYTE_REF(LPICF_ADDR)
-
-#define LPICF_GS_MASK    0x03    /* Gray-Scale Mode */
-#define   LPICF_GS_BW      0x00
-#define   LPICF_GS_GRAY_4  0x01
-#define   LPICF_GS_GRAY_16 0x02
-#define LPICF_PBSIZ_MASK 0x0c   /* Panel Bus Width */
-#define   LPICF_PBSIZ_1    0x00
-#define   LPICF_PBSIZ_2    0x04
-#define   LPICF_PBSIZ_4    0x08
-
-/*
- * LCD Polarity Configuration Register 
- */
-#define LPOLCF_ADDR     0xfffffa21
-#define LPOLCF          BYTE_REF(LPOLCF_ADDR)
-
-#define LPOLCF_PIXPOL   0x01    /* Pixel Polarity */
-#define LPOLCF_LPPOL    0x02    /* Line Pulse Polarity */
-#define LPOLCF_FLMPOL   0x04    /* Frame Marker Polarity */
-#define LPOLCF_LCKPOL   0x08    /* LCD Shift Lock Polarity */
-
-/*
- * LACD (LCD Alternate Crystal Direction) Rate Control Register
- */
-#define LACDRC_ADDR     0xfffffa23
-#define LACDRC          BYTE_REF(LACDRC_ADDR)
-
-#define LACDRC_ACDSLT    0x80   /* Signal Source Select */
-#define LACDRC_ACD_MASK  0x0f   /* Alternate Crystal Direction Control */
-#define LACDRC_ACD_SHIFT 0
-
-/*
- * LCD Pixel Clock Divider Register
- */
-#define LPXCD_ADDR      0xfffffa25
-#define LPXCD           BYTE_REF(LPXCD_ADDR)
-
-#define LPXCD_PCD_MASK  0x3f    /* Pixel Clock Divider */
-#define LPXCD_PCD_SHIFT 0
-
-/*
- * LCD Clocking Control Register
- */
-#define LCKCON_ADDR     0xfffffa27
-#define LCKCON          BYTE_REF(LCKCON_ADDR)
-
-#define LCKCON_DWS_MASK  0x0f   /* Display Wait-State */
-#define LCKCON_DWS_SHIFT 0
-#define LCKCON_DWIDTH    0x40   /* Display Memory Width  */
-#define LCKCON_LCDON     0x80   /* Enable LCD Controller */
-
-/* '328-compatible definitions */
-#define LCKCON_DW_MASK  LCKCON_DWS_MASK
-#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
- 
-/*
- * LCD Refresh Rate Adjustment Register 
- */
-#define LRRA_ADDR       0xfffffa29
-#define LRRA            BYTE_REF(LRRA_ADDR)
-
-/*
- * LCD Panning Offset Register
- */
-#define LPOSR_ADDR      0xfffffa2d
-#define LPOSR           BYTE_REF(LPOSR_ADDR)
-
-#define LPOSR_POS_MASK  0x0f    /* Pixel Offset Code */
-#define LPOSR_POS_SHIFT 0
-
-/*
- * LCD Frame Rate Control Modulation Register
- */
-#define LFRCM_ADDR      0xfffffa31
-#define LFRCM           BYTE_REF(LFRCM_ADDR)
-
-#define LFRCM_YMOD_MASK  0x0f   /* Vertical Modulation */
-#define LFRCM_YMOD_SHIFT 0
-#define LFRCM_XMOD_MASK  0xf0   /* Horizontal Modulation */
-#define LFRCM_XMOD_SHIFT 4
-
-/*
- * LCD Gray Palette Mapping Register
- */
-#define LGPMR_ADDR      0xfffffa33
-#define LGPMR           BYTE_REF(LGPMR_ADDR)
-
-#define LGPMR_G1_MASK   0x0f
-#define LGPMR_G1_SHIFT  0
-#define LGPMR_G2_MASK   0xf0
-#define LGPMR_G2_SHIFT  4
-
-/* 
- * PWM Contrast Control Register
- */
-#define PWMR_ADDR       0xfffffa36
-#define PWMR            WORD_REF(PWMR_ADDR)
-
-#define PWMR_PW_MASK    0x00ff  /* Pulse Width */
-#define PWMR_PW_SHIFT   0
-#define PWMR_CCPEN      0x0100  /* Contrast Control Enable */
-#define PWMR_SRC_MASK   0x0600  /* Input Clock Source */
-#define   PWMR_SRC_LINE   0x0000        /* Line Pulse  */
-#define   PWMR_SRC_PIXEL  0x0200        /* Pixel Clock */
-#define   PWMR_SRC_LCD    0x4000        /* LCD clock   */
-
-/**********
- *
- * 0xFFFFFBxx -- Real-Time Clock (RTC)
- *
- **********/
-
-/*
- * RTC Hours Minutes and Seconds Register
- */
-#define RTCTIME_ADDR    0xfffffb00
-#define RTCTIME         LONG_REF(RTCTIME_ADDR)
-
-#define RTCTIME_SECONDS_MASK    0x0000003f      /* Seconds */
-#define RTCTIME_SECONDS_SHIFT   0
-#define RTCTIME_MINUTES_MASK    0x003f0000      /* Minutes */
-#define RTCTIME_MINUTES_SHIFT   16
-#define RTCTIME_HOURS_MASK      0x1f000000      /* Hours */
-#define RTCTIME_HOURS_SHIFT     24
-
-/*
- *  RTC Alarm Register 
- */
-#define RTCALRM_ADDR    0xfffffb04
-#define RTCALRM         LONG_REF(RTCALRM_ADDR)
-
-#define RTCALRM_SECONDS_MASK    0x0000003f      /* Seconds */
-#define RTCALRM_SECONDS_SHIFT   0
-#define RTCALRM_MINUTES_MASK    0x003f0000      /* Minutes */
-#define RTCALRM_MINUTES_SHIFT   16
-#define RTCALRM_HOURS_MASK      0x1f000000      /* Hours */
-#define RTCALRM_HOURS_SHIFT     24
-
-/*
- * Watchdog Timer Register 
- */
-#define WATCHDOG_ADDR   0xfffffb0a
-#define WATCHDOG        WORD_REF(WATCHDOG_ADDR)
-
-#define WATCHDOG_EN     0x0001  /* Watchdog Enabled */
-#define WATCHDOG_ISEL   0x0002  /* Select the watchdog interrupt */
-#define WATCHDOG_INTF   0x0080  /* Watchdog interrupt occcured */
-#define WATCHDOG_CNT_MASK  0x0300       /* Watchdog Counter */
-#define WATCHDOG_CNT_SHIFT 8
-
-/*
- * RTC Control Register
- */
-#define RTCCTL_ADDR     0xfffffb0c
-#define RTCCTL          WORD_REF(RTCCTL_ADDR)
-
-#define RTCCTL_XTL      0x0020  /* Crystal Selection */
-#define RTCCTL_EN       0x0080  /* RTC Enable */
-
-/* '328-compatible definitions */
-#define RTCCTL_384      RTCCTL_XTL
-#define RTCCTL_ENABLE   RTCCTL_EN
-
-/*
- * RTC Interrupt Status Register 
- */
-#define RTCISR_ADDR     0xfffffb0e
-#define RTCISR          WORD_REF(RTCISR_ADDR)
-
-#define RTCISR_SW       0x0001  /* Stopwatch timed out */
-#define RTCISR_MIN      0x0002  /* 1-minute interrupt has occurred */
-#define RTCISR_ALM      0x0004  /* Alarm interrupt has occurred */
-#define RTCISR_DAY      0x0008  /* 24-hour rollover interrupt has occurred */
-#define RTCISR_1HZ      0x0010  /* 1Hz interrupt has occurred */
-#define RTCISR_HR       0x0020  /* 1-hour interrupt has occurred */
-#define RTCISR_SAM0     0x0100  /*   4Hz /   4.6875Hz interrupt has occurred */ 
-#define RTCISR_SAM1     0x0200  /*   8Hz /   9.3750Hz interrupt has occurred */ 
-#define RTCISR_SAM2     0x0400  /*  16Hz /  18.7500Hz interrupt has occurred */ 
-#define RTCISR_SAM3     0x0800  /*  32Hz /  37.5000Hz interrupt has occurred */ 
-#define RTCISR_SAM4     0x1000  /*  64Hz /  75.0000Hz interrupt has occurred */ 
-#define RTCISR_SAM5     0x2000  /* 128Hz / 150.0000Hz interrupt has occurred */ 
-#define RTCISR_SAM6     0x4000  /* 256Hz / 300.0000Hz interrupt has occurred */ 
-#define RTCISR_SAM7     0x8000  /* 512Hz / 600.0000Hz interrupt has occurred */ 
-
-/*
- * RTC Interrupt Enable Register
- */
-#define RTCIENR_ADDR    0xfffffb10
-#define RTCIENR         WORD_REF(RTCIENR_ADDR)
-
-#define RTCIENR_SW      0x0001  /* Stopwatch interrupt enable */
-#define RTCIENR_MIN     0x0002  /* 1-minute interrupt enable */
-#define RTCIENR_ALM     0x0004  /* Alarm interrupt enable */
-#define RTCIENR_DAY     0x0008  /* 24-hour rollover interrupt enable */
-#define RTCIENR_1HZ     0x0010  /* 1Hz interrupt enable */
-#define RTCIENR_HR      0x0020  /* 1-hour interrupt enable */
-#define RTCIENR_SAM0    0x0100  /*   4Hz /   4.6875Hz interrupt enable */ 
-#define RTCIENR_SAM1    0x0200  /*   8Hz /   9.3750Hz interrupt enable */ 
-#define RTCIENR_SAM2    0x0400  /*  16Hz /  18.7500Hz interrupt enable */ 
-#define RTCIENR_SAM3    0x0800  /*  32Hz /  37.5000Hz interrupt enable */ 
-#define RTCIENR_SAM4    0x1000  /*  64Hz /  75.0000Hz interrupt enable */ 
-#define RTCIENR_SAM5    0x2000  /* 128Hz / 150.0000Hz interrupt enable */ 
-#define RTCIENR_SAM6    0x4000  /* 256Hz / 300.0000Hz interrupt enable */ 
-#define RTCIENR_SAM7    0x8000  /* 512Hz / 600.0000Hz interrupt enable */ 
-
-/* 
- * Stopwatch Minutes Register
- */
-#define STPWCH_ADDR     0xfffffb12
-#define STPWCH          WORD_REF(STPWCH_ADDR)
-
-#define STPWCH_CNT_MASK  0x003f /* Stopwatch countdown value */
-#define SPTWCH_CNT_SHIFT 0
-
-/*
- * RTC Day Count Register 
- */
-#define DAYR_ADDR       0xfffffb1a
-#define DAYR            WORD_REF(DAYR_ADDR)
-
-#define DAYR_DAYS_MASK  0x1ff   /* Day Setting */
-#define DAYR_DAYS_SHIFT 0
-
-/*
- * RTC Day Alarm Register 
- */
-#define DAYALARM_ADDR   0xfffffb1c
-#define DAYALARM        WORD_REF(DAYALARM_ADDR)
-
-#define DAYALARM_DAYSAL_MASK    0x01ff  /* Day Setting of the Alarm */
-#define DAYALARM_DAYSAL_SHIFT   0
-
-/**********
- *
- * 0xFFFFFCxx -- DRAM Controller
- *
- **********/
-
-/*
- * DRAM Memory Configuration Register 
- */
-#define DRAMMC_ADDR     0xfffffc00
-#define DRAMMC          WORD_REF(DRAMMC_ADDR)
-
-#define DRAMMC_ROW12_MASK       0xc000  /* Row address bit for MD12 */
-#define   DRAMMC_ROW12_PA10     0x0000
-#define   DRAMMC_ROW12_PA21     0x4000  
-#define   DRAMMC_ROW12_PA23     0x8000
-#define DRAMMC_ROW0_MASK        0x3000  /* Row address bit for MD0 */
-#define   DRAMMC_ROW0_PA11      0x0000
-#define   DRAMMC_ROW0_PA22      0x1000
-#define   DRAMMC_ROW0_PA23      0x2000
-#define DRAMMC_ROW11            0x0800  /* Row address bit for MD11 PA20/PA22 */
-#define DRAMMC_ROW10            0x0400  /* Row address bit for MD10 PA19/PA21 */
-#define DRAMMC_ROW9             0x0200  /* Row address bit for MD9  PA9/PA19  */
-#define DRAMMC_ROW8             0x0100  /* Row address bit for MD8  PA10/PA20 */
-#define DRAMMC_COL10            0x0080  /* Col address bit for MD10 PA11/PA0  */
-#define DRAMMC_COL9             0x0040  /* Col address bit for MD9  PA10/PA0  */
-#define DRAMMC_COL8             0x0020  /* Col address bit for MD8  PA9/PA0   */
-#define DRAMMC_REF_MASK         0x001f  /* Reresh Cycle */
-#define DRAMMC_REF_SHIFT        0
-
-/*
- * DRAM Control Register
- */
-#define DRAMC_ADDR      0xfffffc02
-#define DRAMC           WORD_REF(DRAMC_ADDR)
-
-#define DRAMC_DWE          0x0001       /* DRAM Write Enable */
-#define DRAMC_RST          0x0002       /* Reset Burst Refresh Enable */
-#define DRAMC_LPR          0x0004       /* Low-Power Refresh Enable */
-#define DRAMC_SLW          0x0008       /* Slow RAM */
-#define DRAMC_LSP          0x0010       /* Light Sleep */
-#define DRAMC_MSW          0x0020       /* Slow Multiplexing */
-#define DRAMC_WS_MASK      0x00c0       /* Wait-states */
-#define DRAMC_WS_SHIFT     6
-#define DRAMC_PGSZ_MASK    0x0300       /* Page Size for fast page mode */
-#define DRAMC_PGSZ_SHIFT   8
-#define   DRAMC_PGSZ_256K  0x0000       
-#define   DRAMC_PGSZ_512K  0x0100
-#define   DRAMC_PGSZ_1024K 0x0200
-#define   DRAMC_PGSZ_2048K 0x0300
-#define DRAMC_EDO          0x0400       /* EDO DRAM */
-#define DRAMC_CLK          0x0800       /* Refresh Timer Clock source select */
-#define DRAMC_BC_MASK      0x3000       /* Page Access Clock Cycle (FP mode) */
-#define DRAMC_BC_SHIFT     12
-#define DRAMC_RM           0x4000       /* Refresh Mode */
-#define DRAMC_EN           0x8000       /* DRAM Controller enable */
-
-
-/**********
- *
- * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
- *
- **********/
-
-/*
- * ICE Module Address Compare Register
- */
-#define ICEMACR_ADDR    0xfffffd00
-#define ICEMACR         LONG_REF(ICEMACR_ADDR)
-
-/*
- * ICE Module Address Mask Register
- */
-#define ICEMAMR_ADDR    0xfffffd04
-#define ICEMAMR         LONG_REF(ICEMAMR_ADDR)
-
-/*
- * ICE Module Control Compare Register
- */
-#define ICEMCCR_ADDR    0xfffffd08
-#define ICEMCCR         WORD_REF(ICEMCCR_ADDR)
-
-#define ICEMCCR_PD      0x0001  /* Program/Data Cycle Selection */
-#define ICEMCCR_RW      0x0002  /* Read/Write Cycle Selection */
-
-/*
- * ICE Module Control Mask Register
- */
-#define ICEMCMR_ADDR    0xfffffd0a
-#define ICEMCMR         WORD_REF(ICEMCMR_ADDR)
-
-#define ICEMCMR_PDM     0x0001  /* Program/Data Cycle Mask */
-#define ICEMCMR_RWM     0x0002  /* Read/Write Cycle Mask */
-
-/*
- * ICE Module Control Register 
- */
-#define ICEMCR_ADDR     0xfffffd0c
-#define ICEMCR          WORD_REF(ICEMCR_ADDR)
-
-#define ICEMCR_CEN      0x0001  /* Compare Enable */
-#define ICEMCR_PBEN     0x0002  /* Program Break Enable */
-#define ICEMCR_SB       0x0004  /* Single Breakpoint */
-#define ICEMCR_HMDIS    0x0008  /* HardMap disable */
-#define ICEMCR_BBIEN    0x0010  /* Bus Break Interrupt Enable */
-
-/*
- * ICE Module Status Register 
- */
-#define ICEMSR_ADDR     0xfffffd0e
-#define ICEMSR          WORD_REF(ICEMSR_ADDR)
-
-#define ICEMSR_EMUEN    0x0001  /* Emulation Enable */
-#define ICEMSR_BRKIRQ   0x0002  /* A-Line Vector Fetch Detected */
-#define ICEMSR_BBIRQ    0x0004  /* Bus Break Interrupt Detected */
-#define ICEMSR_EMIRQ    0x0008  /* EMUIRQ Falling Edge Detected */
-
-#endif /* _MC68VZ328_H_ */
diff --git a/arch/m68knommu/include/asm/anchor.h b/arch/m68knommu/include/asm/anchor.h
deleted file mode 100644
index 871c0d5cfc3d..000000000000
--- a/arch/m68knommu/include/asm/anchor.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/****************************************************************************/
-
-/*
- *      anchor.h -- Anchor CO-MEM Lite PCI host bridge part.
- *
- *      (C) Copyright 2000, Moreton Bay (www.moreton.com.au)
- */
-
-/****************************************************************************/
-#ifndef anchor_h
-#define anchor_h
-/****************************************************************************/
-
-/*
- *      Define basic addressing info.
- */
-#if defined(CONFIG_M5407C3)
-#define COMEM_BASE      0xFFFF0000      /* Base of CO-MEM address space */
-#define COMEM_IRQ       25              /* IRQ of anchor part */
-#else
-#define COMEM_BASE      0x80000000      /* Base of CO-MEM address space */
-#define COMEM_IRQ       25              /* IRQ of anchor part */
-#endif
-
-/****************************************************************************/
-
-/*
- *      4-byte registers of CO-MEM, so adjust register addresses for
- *      easy access. Handy macro for word access too.
- */
-#define LREG(a)         ((a) >> 2)
-#define WREG(a)         ((a) >> 1)
-
-
-/*
- *      Define base addresses within CO-MEM Lite register address space.
- */
-#define COMEM_I2O       0x0000          /* I2O registers */
-#define COMEM_OPREGS    0x0400          /* Operation registers */
-#define COMEM_PCIBUS    0x2000          /* Direct access to PCI bus */
-#define COMEM_SHMEM     0x4000          /* Shared memory region */
-
-#define COMEM_SHMEMSIZE 0x4000          /* Size of shared memory */
-
-
-/*
- *      Define CO-MEM Registers.
- */
-#define COMEM_I2OHISR   0x0030          /* I2O host interrupt status */
-#define COMEM_I2OHIMR   0x0034          /* I2O host interrupt mask */
-#define COMEM_I2OLISR   0x0038          /* I2O local interrupt status */
-#define COMEM_I2OLIMR   0x003c          /* I2O local interrupt mask */
-#define COMEM_IBFPFIFO  0x0040          /* I2O inbound free/post FIFO */
-#define COMEM_OBPFFIFO  0x0044          /* I2O outbound post/free FIFO */
-#define COMEM_IBPFFIFO  0x0048          /* I2O inbound post/free FIFO */
-#define COMEM_OBFPFIFO  0x004c          /* I2O outbound free/post FIFO */
-
-#define COMEM_DAHBASE   0x0460          /* Direct access base address */
-
-#define COMEM_NVCMD     0x04a0          /* I2C serial command */
-#define COMEM_NVREAD    0x04a4          /* I2C serial read */
-#define COMEM_NVSTAT    0x04a8          /* I2C status */
-
-#define COMEM_DMALBASE  0x04b0          /* DMA local base address */
-#define COMEM_DMAHBASE  0x04b4          /* DMA host base address */
-#define COMEM_DMASIZE   0x04b8          /* DMA size */
-#define COMEM_DMACTL    0x04bc          /* DMA control */
-
-#define COMEM_HCTL      0x04e0          /* Host control */
-#define COMEM_HINT      0x04e4          /* Host interrupt control/status */
-#define COMEM_HLDATA    0x04e8          /* Host to local data mailbox */
-#define COMEM_LINT      0x04f4          /* Local interrupt contole status */
-#define COMEM_LHDATA    0x04f8          /* Local to host data mailbox */
-
-#define COMEM_LBUSCFG   0x04fc          /* Local bus configuration */
-
-
-/*
- *      Commands and flags for use with Direct Access Register.
- */
-#define COMEM_DA_IACK   0x00000000      /* Interrupt acknowledge (read) */
-#define COMEM_DA_SPCL   0x00000010      /* Special cycle (write) */
-#define COMEM_DA_MEMRD  0x00000004      /* Memory read cycle */
-#define COMEM_DA_MEMWR  0x00000004      /* Memory write cycle */
-#define COMEM_DA_IORD   0x00000002      /* I/O read cycle */
-#define COMEM_DA_IOWR   0x00000002      /* I/O write cycle */
-#define COMEM_DA_CFGRD  0x00000006      /* Configuration read cycle */
-#define COMEM_DA_CFGWR  0x00000006      /* Configuration write cycle */
-
-#define COMEM_DA_ADDR(a)        ((a) & 0xffffe000)
-
-#define COMEM_DA_OFFSET(a)      ((a) & 0x00001fff)
-
-
-/*
- *      The PCI bus will be limited in what slots will actually be used.
- *      Define valid device numbers for different boards.
- */
-#if defined(CONFIG_M5407C3)
-#define COMEM_MINDEV    14              /* Minimum valid DEVICE */
-#define COMEM_MAXDEV    14              /* Maximum valid DEVICE */
-#define COMEM_BRIDGEDEV 15              /* Slot bridge is in */
-#else
-#define COMEM_MINDEV    0               /* Minimum valid DEVICE */
-#define COMEM_MAXDEV    3               /* Maximum valid DEVICE */
-#endif
-
-#define COMEM_MAXPCI    (COMEM_MAXDEV+1)        /* Maximum PCI devices */
-
-
-/****************************************************************************/
-#endif  /* anchor_h */
diff --git a/arch/m68knommu/include/asm/atomic.h b/arch/m68knommu/include/asm/atomic.h
deleted file mode 100644
index 6bb674855a3f..000000000000
--- a/arch/m68knommu/include/asm/atomic.h
+++ /dev/null
@@ -1,155 +0,0 @@
-#ifndef __ARCH_M68KNOMMU_ATOMIC__
-#define __ARCH_M68KNOMMU_ATOMIC__
-
-#include <linux/types.h>
-#include <asm/system.h>
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-
-/*
- * We do not have SMP m68k systems, so we don't have to deal with that.
- */
-
-#define ATOMIC_INIT(i)  { (i) }
-
-#define atomic_read(v)          ((v)->counter)
-#define atomic_set(v, i)        (((v)->counter) = i)
-
-static __inline__ void atomic_add(int i, atomic_t *v)
-{
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "d" (i));
-#else
-        __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "di" (i));
-#endif
-}
-
-static __inline__ void atomic_sub(int i, atomic_t *v)
-{
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "d" (i));
-#else
-        __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "di" (i));
-#endif
-}
-
-static __inline__ int atomic_sub_and_test(int i, atomic_t * v)
-{
-        char c;
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__("subl %2,%1; seq %0"
-                             : "=d" (c), "+m" (*v)
-                             : "d" (i));
-#else
-        __asm__ __volatile__("subl %2,%1; seq %0"
-                             : "=d" (c), "+m" (*v)
-                             : "di" (i));
-#endif
-        return c != 0;
-}
-
-static __inline__ void atomic_inc(volatile atomic_t *v)
-{
-        __asm__ __volatile__("addql #1,%0" : "+m" (*v));
-}
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-
-static __inline__ int atomic_inc_and_test(volatile atomic_t *v)
-{
-        char c;
-        __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
-        return c != 0;
-}
-
-static __inline__ void atomic_dec(volatile atomic_t *v)
-{
-        __asm__ __volatile__("subql #1,%0" : "+m" (*v));
-}
-
-static __inline__ int atomic_dec_and_test(volatile atomic_t *v)
-{
-        char c;
-        __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
-        return c != 0;
-}
-
-static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v)
-{
-        __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask)));
-}
-
-static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v)
-{
-        __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
-}
-
-/* Atomic operations are already serializing */
-#define smp_mb__before_atomic_dec()    barrier()
-#define smp_mb__after_atomic_dec() barrier()
-#define smp_mb__before_atomic_inc()    barrier()
-#define smp_mb__after_atomic_inc() barrier()
-
-static inline int atomic_add_return(int i, atomic_t * v)
-{
-        unsigned long temp, flags;
-
-        local_irq_save(flags);
-        temp = *(long *)v;
-        temp += i;
-        *(long *)v = temp;
-        local_irq_restore(flags);
-
-        return temp;
-}
-
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-
-static inline int atomic_sub_return(int i, atomic_t * v)
-{
-        unsigned long temp, flags;
-
-        local_irq_save(flags);
-        temp = *(long *)v;
-        temp -= i;
-        *(long *)v = temp;
-        local_irq_restore(flags);
-
-        return temp;
-}
-
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int c, old;
-        c = atomic_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-#define atomic_dec_return(v) atomic_sub_return(1,(v))
-#define atomic_inc_return(v) atomic_add_return(1,(v))
-
-#include <asm-generic/atomic.h>
-#endif /* __ARCH_M68KNOMMU_ATOMIC __ */
diff --git a/arch/m68knommu/include/asm/auxvec.h b/arch/m68knommu/include/asm/auxvec.h
deleted file mode 100644
index 844d6d52204b..000000000000
--- a/arch/m68knommu/include/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASMm68k_AUXVEC_H
-#define __ASMm68k_AUXVEC_H
-
-#endif
diff --git a/arch/m68knommu/include/asm/bitops.h b/arch/m68knommu/include/asm/bitops.h
deleted file mode 100644
index 9d3cbe5fad1e..000000000000
--- a/arch/m68knommu/include/asm/bitops.h
+++ /dev/null
@@ -1,337 +0,0 @@
-#ifndef _M68KNOMMU_BITOPS_H
-#define _M68KNOMMU_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-#include <linux/compiler.h>
-#include <asm/byteorder.h>      /* swab32 */
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#if defined (__mcfisaaplus__) || defined (__mcfisac__)
-static inline int ffs(unsigned int val)
-{
-        if (!val)
-                return 0;
-
-        asm volatile(
-                        "bitrev %0\n\t"
-                        "ff1 %0\n\t"
-                        : "=d" (val)
-                        : "0" (val)
-                    );
-        val++;
-        return val;
-}
-
-static inline int __ffs(unsigned int val)
-{
-        asm volatile(
-                        "bitrev %0\n\t"
-                        "ff1 %0\n\t"
-                        : "=d" (val)
-                        : "0" (val)
-                    );
-        return val;
-}
-
-#else
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/__ffs.h>
-#endif
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffz.h>
-
-static __inline__ void set_bit(int nr, volatile unsigned long * addr)
-{
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)"
-             : "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "d" (nr)
-             : "%a0", "cc");
-#else
-        __asm__ __volatile__ ("bset %1,%0"
-             : "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "di" (nr)
-             : "cc");
-#endif
-}
-
-#define __set_bit(nr, addr) set_bit(nr, addr)
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()      barrier()
-#define smp_mb__after_clear_bit()       barrier()
-
-static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
-{
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)"
-             : "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "d" (nr)
-             : "%a0", "cc");
-#else
-        __asm__ __volatile__ ("bclr %1,%0"
-             : "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "di" (nr)
-             : "cc");
-#endif
-}
-
-#define __clear_bit(nr, addr) clear_bit(nr, addr)
-
-static __inline__ void change_bit(int nr, volatile unsigned long * addr)
-{
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)"
-             : "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "d" (nr)
-             : "%a0", "cc");
-#else
-        __asm__ __volatile__ ("bchg %1,%0"
-             : "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "di" (nr)
-             : "cc");
-#endif
-}
-
-#define __change_bit(nr, addr) change_bit(nr, addr)
-
-static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
-{
-        char retval;
-
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "d" (nr)
-             : "%a0");
-#else
-        __asm__ __volatile__ ("bset %2,%1; sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "di" (nr)
-             /* No clobber */);
-#endif
-
-        return retval;
-}
-
-#define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
-
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
-{
-        char retval;
-
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "d" (nr)
-             : "%a0");
-#else
-        __asm__ __volatile__ ("bclr %2,%1; sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "di" (nr)
-             /* No clobber */);
-#endif
-
-        return retval;
-}
-
-#define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
-
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
-{
-        char retval;
-
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "d" (nr)
-             : "%a0");
-#else
-        __asm__ __volatile__ ("bchg %2,%1; sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
-             : "di" (nr)
-             /* No clobber */);
-#endif
-
-        return retval;
-}
-
-#define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr)
-
-/*
- * This routine doesn't need to be atomic.
- */
-static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr)
-{
-        return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
-}
-
-static __inline__ int __test_bit(int nr, const volatile unsigned long * addr)
-{
-        int     * a = (int *) addr;
-        int     mask;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        return ((mask & *a) != 0);
-}
-
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-static __inline__ int ext2_set_bit(int nr, volatile void * addr)
-{
-        char retval;
-
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
-             : "d" (nr)
-             : "%a0");
-#else
-        __asm__ __volatile__ ("bset %2,%1; sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
-             : "di" (nr)
-             /* No clobber */);
-#endif
-
-        return retval;
-}
-
-static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
-{
-        char retval;
-
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
-             : "d" (nr)
-             : "%a0");
-#else
-        __asm__ __volatile__ ("bclr %2,%1; sne %0"
-             : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
-             : "di" (nr)
-             /* No clobber */);
-#endif
-
-        return retval;
-}
-
-#define ext2_set_bit_atomic(lock, nr, addr)             \
-        ({                                              \
-                int ret;                                \
-                spin_lock(lock);                        \
-                ret = ext2_set_bit((nr), (addr));       \
-                spin_unlock(lock);                      \
-                ret;                                    \
-        })
-
-#define ext2_clear_bit_atomic(lock, nr, addr)           \
-        ({                                              \
-                int ret;                                \
-                spin_lock(lock);                        \
-                ret = ext2_clear_bit((nr), (addr));     \
-                spin_unlock(lock);                      \
-                ret;                                    \
-        })
-
-static __inline__ int ext2_test_bit(int nr, const volatile void * addr)
-{
-        char retval;
-
-#ifdef CONFIG_COLDFIRE
-        __asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0"
-             : "=d" (retval)
-             : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr)
-             : "%a0");
-#else
-        __asm__ __volatile__ ("btst %2,%1; sne %0"
-             : "=d" (retval)
-             : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr)
-             /* No clobber */);
-#endif
-
-        return retval;
-}
-
-#define ext2_find_first_zero_bit(addr, size) \
-        ext2_find_next_zero_bit((addr), (size), 0)
-
-static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
-{
-        unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
-        unsigned long result = offset & ~31UL;
-        unsigned long tmp;
-
-        if (offset >= size)
-                return size;
-        size -= result;
-        offset &= 31UL;
-        if(offset) {
-                /* We hold the little endian value in tmp, but then the
-                 * shift is illegal. So we could keep a big endian value
-                 * in tmp, like this:
-                 *
-                 * tmp = __swab32(*(p++));
-                 * tmp |= ~0UL >> (32-offset);
-                 *
-                 * but this would decrease performance, so we change the
-                 * shift:
-                 */
-                tmp = *(p++);
-                tmp |= __swab32(~0UL >> (32-offset));
-                if(size < 32)
-                        goto found_first;
-                if(~tmp)
-                        goto found_middle;
-                size -= 32;
-                result += 32;
-        }
-        while(size & ~31UL) {
-                if(~(tmp = *(p++)))
-                        goto found_middle;
-                result += 32;
-                size -= 32;
-        }
-        if(!size)
-                return result;
-        tmp = *p;
-
-found_first:
-        /* tmp is little endian, so we would have to swab the shift,
-         * see above. But then we have to swab tmp below for ffz, so
-         * we might as well do this here.
-         */
-        return result + ffz(__swab32(tmp) | (~0UL << size));
-found_middle:
-        return result + ffz(__swab32(tmp));
-}
-
-#define ext2_find_next_bit(addr, size, off) \
-        generic_find_next_le_bit((unsigned long *)(addr), (size), (off))
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#endif /* _M68KNOMMU_BITOPS_H */
diff --git a/arch/m68knommu/include/asm/bootinfo.h b/arch/m68knommu/include/asm/bootinfo.h
deleted file mode 100644
index c12e526f5189..000000000000
--- a/arch/m68knommu/include/asm/bootinfo.h
+++ /dev/null
@@ -1,2 +0,0 @@
-
-/* Nothing for m68knommu */
diff --git a/arch/m68knommu/include/asm/bootstd.h b/arch/m68knommu/include/asm/bootstd.h
deleted file mode 100644
index bdc1a4ac4fe9..000000000000
--- a/arch/m68knommu/include/asm/bootstd.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* bootstd.h:  Bootloader system call interface
- *
- * (c) 1999, Rt-Control, Inc.
- */
-
-#ifndef __BOOTSTD_H__
-#define __BOOTSTD_H__
-
-#define NR_BSC 21            /* last used bootloader system call */
-
-#define __BN_reset        0  /* reset and start the bootloader */
-#define __BN_test         1  /* tests the system call interface */
-#define __BN_exec         2  /* executes a bootloader image */
-#define __BN_exit         3  /* terminates a bootloader image */
-#define __BN_program      4  /* program FLASH from a chain */
-#define __BN_erase        5  /* erase sector(s) of FLASH */
-#define __BN_open         6
-#define __BN_write        7
-#define __BN_read         8
-#define __BN_close        9
-#define __BN_mmap         10 /* map a file descriptor into memory */
-#define __BN_munmap       11 /* remove a file to memory mapping */
-#define __BN_gethwaddr    12 /* get the hardware address of my interfaces */
-#define __BN_getserialnum 13 /* get the serial number of this board */
-#define __BN_getbenv      14 /* get a bootloader envvar */
-#define __BN_setbenv      15 /* get a bootloader envvar */
-#define __BN_setpmask     16 /* set the protection mask */
-#define __BN_readenv      17 /* read environment variables */
-#define __BN_flash_chattr_range         18
-#define __BN_flash_erase_range          19
-#define __BN_flash_write_range          20
-
-/* Calling conventions compatible to (uC)linux/68k
- * We use simmilar macros to call into the bootloader as for uClinux
- */
-
-#define __bsc_return(type, res) \
-do { \
-   if ((unsigned long)(res) >= (unsigned long)(-64)) { \
-      /* let errno be a function, preserve res in %d0 */ \
-      int __err = -(res); \
-      errno = __err; \
-      res = -1; \
-   } \
-   return (type)(res); \
-} while (0)
-
-#define _bsc0(type,name) \
-type name(void) \
-{ \
-   register long __res __asm__ ("%d0") = __BN_##name; \
-   __asm__ __volatile__ ("trap #2" \
-                         : "=g" (__res) \
-                         : "0" (__res) \
-                         ); \
-   __bsc_return(type,__res); \
-}
-
-#define _bsc1(type,name,atype,a) \
-type name(atype a) \
-{ \
-   register long __res __asm__ ("%d0") = __BN_##name; \
-   register long __a __asm__ ("%d1") = (long)a; \
-   __asm__ __volatile__ ("trap #2" \
-                         : "=g" (__res) \
-                         : "0" (__res), "d" (__a) \
-                         ); \
-   __bsc_return(type,__res); \
-}
-
-#define _bsc2(type,name,atype,a,btype,b) \
-type name(atype a, btype b) \
-{ \
-   register long __res __asm__ ("%d0") = __BN_##name; \
-   register long __a __asm__ ("%d1") = (long)a; \
-   register long __b __asm__ ("%d2") = (long)b; \
-   __asm__ __volatile__ ("trap #2" \
-                         : "=g" (__res) \
-                         : "0" (__res), "d" (__a), "d" (__b) \
-                         ); \
-   __bsc_return(type,__res); \
-}
-
-#define _bsc3(type,name,atype,a,btype,b,ctype,c) \
-type name(atype a, btype b, ctype c) \
-{ \
-   register long __res __asm__ ("%d0") = __BN_##name; \
-   register long __a __asm__ ("%d1") = (long)a; \
-   register long __b __asm__ ("%d2") = (long)b; \
-   register long __c __asm__ ("%d3") = (long)c; \
-   __asm__ __volatile__ ("trap #2" \
-                         : "=g" (__res) \
-                         : "0" (__res), "d" (__a), "d" (__b), \
-                           "d" (__c) \
-                         ); \
-   __bsc_return(type,__res); \
-}
-
-#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
-type name(atype a, btype b, ctype c, dtype d) \
-{ \
-   register long __res __asm__ ("%d0") = __BN_##name; \
-   register long __a __asm__ ("%d1") = (long)a; \
-   register long __b __asm__ ("%d2") = (long)b; \
-   register long __c __asm__ ("%d3") = (long)c; \
-   register long __d __asm__ ("%d4") = (long)d; \
-   __asm__ __volatile__ ("trap #2" \
-                         : "=g" (__res) \
-                         : "0" (__res), "d" (__a), "d" (__b), \
-                           "d" (__c), "d" (__d) \
-                         ); \
-   __bsc_return(type,__res); \
-}
-
-#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
-type name(atype a, btype b, ctype c, dtype d, etype e) \
-{ \
-   register long __res __asm__ ("%d0") = __BN_##name; \
-   register long __a __asm__ ("%d1") = (long)a; \
-   register long __b __asm__ ("%d2") = (long)b; \
-   register long __c __asm__ ("%d3") = (long)c; \
-   register long __d __asm__ ("%d4") = (long)d; \
-   register long __e __asm__ ("%d5") = (long)e; \
-   __asm__ __volatile__ ("trap #2" \
-                         : "=g" (__res) \
-                         : "0" (__res), "d" (__a), "d" (__b), \
-                           "d" (__c), "d" (__d), "d" (__e) \
-                         ); \
-   __bsc_return(type,__res); \
-}
-
-#endif /* __BOOTSTD_H__ */
diff --git a/arch/m68knommu/include/asm/bug.h b/arch/m68knommu/include/asm/bug.h
deleted file mode 100644
index 70e7dc0af21a..000000000000
--- a/arch/m68knommu/include/asm/bug.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _M68KNOMMU_BUG_H
-#define _M68KNOMMU_BUG_H
-#include <asm-generic/bug.h>
-#endif
diff --git a/arch/m68knommu/include/asm/bugs.h b/arch/m68knommu/include/asm/bugs.h
deleted file mode 100644
index 5f382dac3a60..000000000000
--- a/arch/m68knommu/include/asm/bugs.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  include/asm-m68k/bugs.h
- *
- *  Copyright (C) 1994  Linus Torvalds
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *      void check_bugs(void);
- */
-
-static void check_bugs(void)
-{
-}
diff --git a/arch/m68knommu/include/asm/byteorder.h b/arch/m68knommu/include/asm/byteorder.h
deleted file mode 100644
index a6f0b8f7f622..000000000000
--- a/arch/m68knommu/include/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _M68KNOMMU_BYTEORDER_H
-#define _M68KNOMMU_BYTEORDER_H
-
-#include <asm/swab.h>
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _M68KNOMMU_BYTEORDER_H */
diff --git a/arch/m68knommu/include/asm/cache.h b/arch/m68knommu/include/asm/cache.h
deleted file mode 100644
index 24e9eace5f8c..000000000000
--- a/arch/m68knommu/include/asm/cache.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __ARCH_M68KNOMMU_CACHE_H
-#define __ARCH_M68KNOMMU_CACHE_H
-
-/* bytes per L1 cache line */
-#define        L1_CACHE_BYTES  16       /* this need to be at least 1 */
-
-/* m68k-elf-gcc  2.95.2 doesn't like these */
-
-#define __cacheline_aligned
-#define ____cacheline_aligned
-
-#endif
diff --git a/arch/m68knommu/include/asm/cachectl.h b/arch/m68knommu/include/asm/cachectl.h
deleted file mode 100644
index bcf5a6a9dd52..000000000000
--- a/arch/m68knommu/include/asm/cachectl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/cachectl.h>
diff --git a/arch/m68knommu/include/asm/cacheflush.h b/arch/m68knommu/include/asm/cacheflush.h
deleted file mode 100644
index 87e5dc0413b4..000000000000
--- a/arch/m68knommu/include/asm/cacheflush.h
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef _M68KNOMMU_CACHEFLUSH_H
-#define _M68KNOMMU_CACHEFLUSH_H
-
-/*
- * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
- */
-#include <linux/mm.h>
-
-#define flush_cache_all()                       __flush_cache_all()
-#define flush_cache_mm(mm)                      do { } while (0)
-#define flush_cache_dup_mm(mm)                  do { } while (0)
-#define flush_cache_range(vma, start, end)      __flush_cache_all()
-#define flush_cache_page(vma, vmaddr)           do { } while (0)
-#define flush_dcache_range(start,len)           __flush_cache_all()
-#define flush_dcache_page(page)                 do { } while (0)
-#define flush_dcache_mmap_lock(mapping)         do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
-#define flush_icache_range(start,len)           __flush_cache_all()
-#define flush_icache_page(vma,pg)               do { } while (0)
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-#define flush_cache_vmap(start, end)            do { } while (0)
-#define flush_cache_vunmap(start, end)          do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-        memcpy(dst, src, len)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-        memcpy(dst, src, len)
-
-static inline void __flush_cache_all(void)
-{
-#ifdef CONFIG_M5407
-        /*
-         *      Use cpushl to push and invalidate all cache lines.
-         *      Gas doesn't seem to know how to generate the ColdFire
-         *      cpushl instruction... Oh well, bit stuff it for now.
-         */
-        __asm__ __volatile__ (
-                "nop\n\t"
-                "clrl   %%d0\n\t"
-                "1:\n\t"
-                "movel  %%d0,%%a0\n\t"
-                "2:\n\t"
-                ".word  0xf468\n\t"
-                "addl   #0x10,%%a0\n\t"
-                "cmpl   #0x00000800,%%a0\n\t"
-                "blt    2b\n\t"
-                "addql  #1,%%d0\n\t"
-                "cmpil  #4,%%d0\n\t"
-                "bne    1b\n\t"
-                "movel  #0xb6088500,%%d0\n\t"
-                "movec  %%d0,%%CACR\n\t"
-                : : : "d0", "a0" );
-#endif /* CONFIG_M5407 */
-#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
-        __asm__ __volatile__ (
-                "movel  #0x81000200, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
-                "nop\n\t"
-                : : : "d0" );
-#endif /* CONFIG_M527x || CONFIG_M528x */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
-        __asm__ __volatile__ (
-                "movel  #0x81000100, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
-                "nop\n\t"
-                : : : "d0" );
-#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
-#ifdef CONFIG_M5249
-        __asm__ __volatile__ (
-                "movel  #0xa1000200, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
-                "nop\n\t"
-                : : : "d0" );
-#endif /* CONFIG_M5249 */
-#ifdef CONFIG_M532x
-        __asm__ __volatile__ (
-                "movel  #0x81000200, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
-                "nop\n\t"
-                : : : "d0" );
-#endif /* CONFIG_M532x */
-}
-
-#endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68knommu/include/asm/checksum.h b/arch/m68knommu/include/asm/checksum.h
deleted file mode 100644
index 81883482ffb1..000000000000
--- a/arch/m68knommu/include/asm/checksum.h
+++ /dev/null
@@ -1,132 +0,0 @@
-#ifndef _M68K_CHECKSUM_H
-#define _M68K_CHECKSUM_H
-
-#include <linux/in6.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy_nocheck(const void *src, void *dst,
-        int len, __wsum sum);
-
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-extern __wsum csum_partial_copy_from_user(const void __user *src,
-        void *dst, int len, __wsum sum, int *csum_err);
-
-__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-
-/*
- *      Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
-        unsigned int tmp = (__force u32)sum;
-#ifdef CONFIG_COLDFIRE
-        tmp = (tmp & 0xffff) + (tmp >> 16);
-        tmp = (tmp & 0xffff) + (tmp >> 16);
-        return (__force __sum16)~tmp;
-#else
-        __asm__("swap %1\n\t"
-                "addw %1, %0\n\t"
-                "clrw %1\n\t"
-                "addxw %1, %0"
-                : "=&d" (sum), "=&d" (tmp)
-                : "0" (sum), "1" (sum));
-        return (__force __sum16)~sum;
-#endif
-}
-
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        __asm__ ("addl  %1,%0\n\t"
-                 "addxl %4,%0\n\t"
-                 "addxl %5,%0\n\t"
-                 "clrl %1\n\t"
-                 "addxl %1,%0"
-                 : "=&d" (sum), "=&d" (saddr)
-                 : "0" (daddr), "1" (saddr), "d" (len + proto),
-                   "d"(sum));
-        return sum;
-}
-
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#define _HAVE_ARCH_IPV6_CSUM
-static __inline__ __sum16
-csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
-                __u32 len, unsigned short proto, __wsum sum)
-{
-        register unsigned long tmp;
-        __asm__("addl %2@,%0\n\t"
-                "movel %2@(4),%1\n\t"
-                "addxl %1,%0\n\t"
-                "movel %2@(8),%1\n\t"
-                "addxl %1,%0\n\t"
-                "movel %2@(12),%1\n\t"
-                "addxl %1,%0\n\t"
-                "movel %3@,%1\n\t"
-                "addxl %1,%0\n\t"
-                "movel %3@(4),%1\n\t"
-                "addxl %1,%0\n\t"
-                "movel %3@(8),%1\n\t"
-                "addxl %1,%0\n\t"
-                "movel %3@(12),%1\n\t"
-                "addxl %1,%0\n\t"
-                "addxl %4,%0\n\t"
-                "clrl %1\n\t"
-                "addxl %1,%0"
-                : "=&d" (sum), "=&d" (tmp)
-                : "a" (saddr), "a" (daddr), "d" (len + proto),
-                  "0" (sum));
-
-        return csum_fold(sum);
-}
-
-#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68knommu/include/asm/coldfire.h b/arch/m68knommu/include/asm/coldfire.h
deleted file mode 100644
index 83a9fa4e618a..000000000000
--- a/arch/m68knommu/include/asm/coldfire.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/****************************************************************************/
-
-/*
- *      coldfire.h -- Motorola ColdFire CPU sepecific defines
- *
- *      (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo (www.lineo.com)
- */
-
-/****************************************************************************/
-#ifndef coldfire_h
-#define coldfire_h
-/****************************************************************************/
-
-
-/*
- *      Define master clock frequency. This is essentially done at config
- *      time now. No point enumerating dozens of possible clock options
- *      here. Also the peripheral clock (bus clock) divide ratio is set
- *      at config time too.
- */
-#ifdef CONFIG_CLOCK_SET
-#define MCF_CLK         CONFIG_CLOCK_FREQ
-#define MCF_BUSCLK      (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
-#else
-#error "Don't know what your ColdFire CPU clock frequency is??"
-#endif
-
-/*
- *      Define the processor support peripherals base address.
- *      This is generally setup by the boards start up code.
- */
-#define MCF_MBAR        0x10000000
-#define MCF_MBAR2       0x80000000
-#if defined(CONFIG_M520x)
-#define MCF_IPSBAR      0xFC000000
-#else
-#define MCF_IPSBAR      0x40000000
-#endif
-
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x)
-#undef MCF_MBAR
-#define MCF_MBAR        MCF_IPSBAR
-#elif defined(CONFIG_M532x)
-#undef MCF_MBAR
-#define MCF_MBAR        0x00000000
-#endif
-
-/****************************************************************************/
-#endif  /* coldfire_h */
diff --git a/arch/m68knommu/include/asm/commproc.h b/arch/m68knommu/include/asm/commproc.h
deleted file mode 100644
index edf5eb6c08d2..000000000000
--- a/arch/m68knommu/include/asm/commproc.h
+++ /dev/null
@@ -1,703 +0,0 @@
-
-/*
- * 68360 Communication Processor Module.
- * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
- * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
- *
- * This file contains structures and information for the communication
- * processor channels.  Some CPM control and status is available
- * through the 68360 internal memory map.  See include/asm/360_immap.h for details.
- * This file is not a complete map of all of the 360 QUICC's capabilities
- *
- * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
- * bytes of the DP RAM and relocates the I2C parameter area to the
- * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
- * or other use.
- */
-#ifndef __CPM_360__
-#define __CPM_360__
-
-
-/* CPM Command register masks: */
-#define CPM_CR_RST      ((ushort)0x8000)
-#define CPM_CR_OPCODE   ((ushort)0x0f00)
-#define CPM_CR_CHAN     ((ushort)0x00f0)
-#define CPM_CR_FLG      ((ushort)0x0001)
-
-/* CPM Command set (opcodes): */
-#define CPM_CR_INIT_TRX         ((ushort)0x0000)
-#define CPM_CR_INIT_RX          ((ushort)0x0001)
-#define CPM_CR_INIT_TX          ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
-#define CPM_CR_STOP_TX          ((ushort)0x0004)
-#define CPM_CR_GRSTOP_TX        ((ushort)0x0005)
-#define CPM_CR_RESTART_TX       ((ushort)0x0006)
-#define CPM_CR_CLOSE_RXBD       ((ushort)0x0007)
-#define CPM_CR_SET_GADDR        ((ushort)0x0008)
-#define CPM_CR_GCI_TIMEOUT      ((ushort)0x0009)
-#define CPM_CR_GCI_ABORT        ((ushort)0x000a)
-#define CPM_CR_RESET_BCS        ((ushort)0x000a)
-
-/* CPM Channel numbers. */
-#define CPM_CR_CH_SCC1  ((ushort)0x0000)
-#define CPM_CR_CH_SCC2  ((ushort)0x0004)
-#define CPM_CR_CH_SPI   ((ushort)0x0005)        /* SPI / Timers */
-#define CPM_CR_CH_TMR   ((ushort)0x0005)
-#define CPM_CR_CH_SCC3  ((ushort)0x0008)
-#define CPM_CR_CH_SMC1  ((ushort)0x0009)        /* SMC1 / IDMA1 */
-#define CPM_CR_CH_IDMA1 ((ushort)0x0009)
-#define CPM_CR_CH_SCC4  ((ushort)0x000c)
-#define CPM_CR_CH_SMC2  ((ushort)0x000d)        /* SMC2 / IDMA2 */
-#define CPM_CR_CH_IDMA2 ((ushort)0x000d)
-
-
-#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
-
-#if 1 /* mleslie: I dinna think we have any such restrictions on
-       * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
-
-/* The dual ported RAM is multi-functional.  Some areas can be (and are
- * being) used for microcode.  There is an area that can only be used
- * as data ram for buffer descriptors, which is all we use right now.
- * Currently the first 512 and last 256 bytes are used for microcode.
- */
-/* mleslie: The uCquicc board is using no extra microcode in DPRAM */
-#define CPM_DATAONLY_BASE       ((uint)0x0000)
-#define CPM_DATAONLY_SIZE       ((uint)0x0800)
-#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
-
-#endif
-
-
-/* Export the base address of the communication processor registers
- * and dual port ram. */
-/* extern       cpm360_t        *cpmp; */               /* Pointer to comm processor */
-extern QUICC *pquicc;
-uint         m360_cpm_dpalloc(uint size);
-/* void         *m360_cpm_hostalloc(uint size); */
-void          m360_cpm_setbrg(uint brg, uint rate);
-
-#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h  */
-/* Buffer descriptors used by many of the CPM protocols. */
-typedef struct cpm_buf_desc {
-        ushort  cbd_sc;         /* Status and Control */
-        ushort  cbd_datlen;     /* Data length in buffer */
-        uint    cbd_bufaddr;    /* Buffer address in host memory */
-} cbd_t;
-#endif
-
-
-/* rx bd status/control bits */
-#define BD_SC_EMPTY     ((ushort)0x8000)        /* Recieve is empty */
-#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor in table */
-#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
-#define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame OR control char */
-
-#define BD_SC_FIRST     ((ushort)0x0400)        /* 1st buffer in an HDLC frame */
-#define BD_SC_ADDR      ((ushort)0x0400)        /* 1st byte is a multidrop address */
-
-#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
-#define BD_SC_ID        ((ushort)0x0100)        /* Received too many idles */
-
-#define BD_SC_AM        ((ushort)0x0080)        /* Multidrop address match */
-#define BD_SC_DE        ((ushort)0x0080)        /* DPLL Error (HDLC) */
-
-#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
-#define BD_SC_LG        ((ushort)0x0020)        /* Frame length violation (HDLC) */
-
-#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
-#define BD_SC_NO        ((ushort)0x0010)        /* Nonoctet aligned frame (HDLC) */
-
-#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
-#define BD_SC_AB        ((ushort)0x0008)        /* Received abort Sequence (HDLC) */
-
-#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
-#define BD_SC_CD        ((ushort)0x0001)        /* Carrier Detect lost */
-
-/* tx bd status/control bits (as differ from rx bd) */
-#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
-#define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
-#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
-#define BD_SC_UN        ((ushort)0x0002)        /* Underrun */
-
-
-
-
-/* Parameter RAM offsets. */
-
-
-
-/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
- * In 2.0, we use a more structured C struct map of DPRAM, and so 
- * instead, we need only a parameter ram `slot'  */
-
-#define PRSLOT_SCC1     0
-#define PRSLOT_SCC2     1
-#define PRSLOT_SCC3     2
-#define PRSLOT_SMC1     2
-#define PRSLOT_SCC4     3
-#define PRSLOT_SMC2     3
-
-
-/* #define PROFF_SCC1   ((uint)0x0000) */
-/* #define PROFF_SCC2   ((uint)0x0100) */
-/* #define PROFF_SCC3   ((uint)0x0200) */
-/* #define PROFF_SMC1   ((uint)0x0280) */
-/* #define PROFF_SCC4   ((uint)0x0300) */
-/* #define PROFF_SMC2   ((uint)0x0380) */
-
-
-/* Define enough so I can at least use the serial port as a UART.
- * The MBX uses SMC1 as the host serial port.
- */
-typedef struct smc_uart {
-        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
-        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
-        u_char  smc_rfcr;       /* Rx function code */
-        u_char  smc_tfcr;       /* Tx function code */
-        ushort  smc_mrblr;      /* Max receive buffer length */
-        uint    smc_rstate;     /* Internal */
-        uint    smc_idp;        /* Internal */
-        ushort  smc_rbptr;      /* Internal */
-        ushort  smc_ibc;        /* Internal */
-        uint    smc_rxtmp;      /* Internal */
-        uint    smc_tstate;     /* Internal */
-        uint    smc_tdp;        /* Internal */
-        ushort  smc_tbptr;      /* Internal */
-        ushort  smc_tbc;        /* Internal */
-        uint    smc_txtmp;      /* Internal */
-        ushort  smc_maxidl;     /* Maximum idle characters */
-        ushort  smc_tmpidl;     /* Temporary idle counter */
-        ushort  smc_brklen;     /* Last received break length */
-        ushort  smc_brkec;      /* rcv'd break condition counter */
-        ushort  smc_brkcr;      /* xmt break count register */
-        ushort  smc_rmask;      /* Temporary bit mask */
-} smc_uart_t;
-
-/* Function code bits.
-*/
-#define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
-
-/* SMC uart mode register.
-*/
-#define SMCMR_REN       ((ushort)0x0001)
-#define SMCMR_TEN       ((ushort)0x0002)
-#define SMCMR_DM        ((ushort)0x000c)
-#define SMCMR_SM_GCI    ((ushort)0x0000)
-#define SMCMR_SM_UART   ((ushort)0x0020)
-#define SMCMR_SM_TRANS  ((ushort)0x0030)
-#define SMCMR_SM_MASK   ((ushort)0x0030)
-#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
-#define SMCMR_REVD      SMCMR_PM_EVEN
-#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
-#define SMCMR_BS        SMCMR_PEN
-#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
-#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
-#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC2 as Centronics parallel printer.  It is half duplex, in that
- * it can only receive or transmit.  The parameter ram values for
- * each direction are either unique or properly overlap, so we can
- * include them in one structure.
- */
-typedef struct smc_centronics {
-        ushort  scent_rbase;
-        ushort  scent_tbase;
-        u_char  scent_cfcr;
-        u_char  scent_smask;
-        ushort  scent_mrblr;
-        uint    scent_rstate;
-        uint    scent_r_ptr;
-        ushort  scent_rbptr;
-        ushort  scent_r_cnt;
-        uint    scent_rtemp;
-        uint    scent_tstate;
-        uint    scent_t_ptr;
-        ushort  scent_tbptr;
-        ushort  scent_t_cnt;
-        uint    scent_ttemp;
-        ushort  scent_max_sl;
-        ushort  scent_sl_cnt;
-        ushort  scent_character1;
-        ushort  scent_character2;
-        ushort  scent_character3;
-        ushort  scent_character4;
-        ushort  scent_character5;
-        ushort  scent_character6;
-        ushort  scent_character7;
-        ushort  scent_character8;
-        ushort  scent_rccm;
-        ushort  scent_rccr;
-} smc_cent_t;
-
-/* Centronics Status Mask Register.
-*/
-#define SMC_CENT_F      ((u_char)0x08)
-#define SMC_CENT_PE     ((u_char)0x04)
-#define SMC_CENT_S      ((u_char)0x02)
-
-/* SMC Event and Mask register.
-*/
-#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
-#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
-#define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
-#define SMCM_BSY        ((unsigned char)0x04)
-#define SMCM_TX         ((unsigned char)0x02)
-#define SMCM_RX         ((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST             ((uint)0x00020000)
-#define CPM_BRG_EN              ((uint)0x00010000)
-#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
-#define CPM_BRG_ATB             ((uint)0x00002000)
-#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
-#define CPM_BRG_DIV16           ((uint)0x00000001)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP           ((uint)0x00040000)
-#define SCC_GSMRH_GDE           ((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
-#define SCC_GSMRH_REVD          ((uint)0x00002000)
-#define SCC_GSMRH_TRX           ((uint)0x00001000)
-#define SCC_GSMRH_TTX           ((uint)0x00000800)
-#define SCC_GSMRH_CDP           ((uint)0x00000400)
-#define SCC_GSMRH_CTSP          ((uint)0x00000200)
-#define SCC_GSMRH_CDS           ((uint)0x00000100)
-#define SCC_GSMRH_CTSS          ((uint)0x00000080)
-#define SCC_GSMRH_TFL           ((uint)0x00000040)
-#define SCC_GSMRH_RFW           ((uint)0x00000020)
-#define SCC_GSMRH_TXSY          ((uint)0x00000010)
-#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
-#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
-#define SCC_GSMRH_RTSM          ((uint)0x00000002)
-#define SCC_GSMRH_RSYN          ((uint)0x00000001)
-
-#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
-#define SCC_GSMRL_TCI           ((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
-#define SCC_GSMRL_RINV          ((uint)0x02000000)
-#define SCC_GSMRL_TINV          ((uint)0x01000000)
-#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
-#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
-#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
-#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
-#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
-#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
-#define SCC_GSMRL_TEND          ((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
-#define SCC_GSMRL_ENR           ((uint)0x00000020)
-#define SCC_GSMRL_ENT           ((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
-
-#define SCC_TODR_TOD            ((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define SCCM_TXE        ((unsigned char)0x10)
-#define SCCM_BSY        ((unsigned char)0x04)
-#define SCCM_TX         ((unsigned char)0x02)
-#define SCCM_RX         ((unsigned char)0x01)
-
-typedef struct scc_param {
-        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
-        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
-        u_char  scc_rfcr;       /* Rx function code */
-        u_char  scc_tfcr;       /* Tx function code */
-        ushort  scc_mrblr;      /* Max receive buffer length */
-        uint    scc_rstate;     /* Internal */
-        uint    scc_idp;        /* Internal */
-        ushort  scc_rbptr;      /* Internal */
-        ushort  scc_ibc;        /* Internal */
-        uint    scc_rxtmp;      /* Internal */
-        uint    scc_tstate;     /* Internal */
-        uint    scc_tdp;        /* Internal */
-        ushort  scc_tbptr;      /* Internal */
-        ushort  scc_tbc;        /* Internal */
-        uint    scc_txtmp;      /* Internal */
-        uint    scc_rcrc;       /* Internal */
-        uint    scc_tcrc;       /* Internal */
-} sccp_t;
-
-
-/* Function code bits.
- */
-#define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
-#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-        sccp_t  sen_genscc;
-        uint    sen_cpres;      /* Preset CRC */
-        uint    sen_cmask;      /* Constant mask for CRC */
-        uint    sen_crcec;      /* CRC Error counter */
-        uint    sen_alec;       /* alignment error counter */
-        uint    sen_disfc;      /* discard frame counter */
-        ushort  sen_pads;       /* Tx short frame pad character */
-        ushort  sen_retlim;     /* Retry limit threshold */
-        ushort  sen_retcnt;     /* Retry limit counter */
-        ushort  sen_maxflr;     /* maximum frame length register */
-        ushort  sen_minflr;     /* minimum frame length register */
-        ushort  sen_maxd1;      /* maximum DMA1 length */
-        ushort  sen_maxd2;      /* maximum DMA2 length */
-        ushort  sen_maxd;       /* Rx max DMA */
-        ushort  sen_dmacnt;     /* Rx DMA counter */
-        ushort  sen_maxb;       /* Max BD byte count */
-        ushort  sen_gaddr1;     /* Group address filter */
-        ushort  sen_gaddr2;
-        ushort  sen_gaddr3;
-        ushort  sen_gaddr4;
-        uint    sen_tbuf0data0; /* Save area 0 - current frame */
-        uint    sen_tbuf0data1; /* Save area 1 - current frame */
-        uint    sen_tbuf0rba;   /* Internal */
-        uint    sen_tbuf0crc;   /* Internal */
-        ushort  sen_tbuf0bcnt;  /* Internal */
-        ushort  sen_paddrh;     /* physical address (MSB) */
-        ushort  sen_paddrm;
-        ushort  sen_paddrl;     /* physical address (LSB) */
-        ushort  sen_pper;       /* persistence */
-        ushort  sen_rfbdptr;    /* Rx first BD pointer */
-        ushort  sen_tfbdptr;    /* Tx first BD pointer */
-        ushort  sen_tlbdptr;    /* Tx last BD pointer */
-        uint    sen_tbuf1data0; /* Save area 0 - current frame */
-        uint    sen_tbuf1data1; /* Save area 1 - current frame */
-        uint    sen_tbuf1rba;   /* Internal */
-        uint    sen_tbuf1crc;   /* Internal */
-        ushort  sen_tbuf1bcnt;  /* Internal */
-        ushort  sen_txlen;      /* Tx Frame length counter */
-        ushort  sen_iaddr1;     /* Individual address filter */
-        ushort  sen_iaddr2;
-        ushort  sen_iaddr3;
-        ushort  sen_iaddr4;
-        ushort  sen_boffcnt;    /* Backoff counter */
-
-        /* NOTE: Some versions of the manual have the following items
-         * incorrectly documented.  Below is the proper order.
-         */
-        ushort  sen_taddrh;     /* temp address (MSB) */
-        ushort  sen_taddrm;
-        ushort  sen_taddrl;     /* temp address (LSB) */
-} scc_enet_t;
-
-
-
-#if defined (CONFIG_UCQUICC)
-/* uCquicc has the following signals connected to Ethernet:
- *  68360    - lxt905
- * PA0/RXD1  - rxd
- * PA1/TXD1  - txd
- * PA8/CLK1  - tclk
- * PA9/CLK2  - rclk
- * PC0/!RTS1 - t_en
- * PC1/!CTS1 - col
- * PC5/!CD1  - cd
- */
-#define PA_ENET_RXD     PA_RXD1
-#define PA_ENET_TXD     PA_TXD1
-#define PA_ENET_TCLK    PA_CLK1
-#define PA_ENET_RCLK    PA_CLK2
-#define PC_ENET_TENA    PC_RTS1
-#define PC_ENET_CLSN    PC_CTS1
-#define PC_ENET_RENA    PC_CD1
-
-/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
- * SCC1.
- */
-#define SICR_ENET_MASK  ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000002c)
-
-#endif /* config_ucquicc */
-
-
-#ifdef MBX
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
- * to the MBX860 board.  Any two of the four available clocks could be
- * used, and the MPC860 cookbook manual has an example using different
- * clock pins.
- */
-#define PA_ENET_RXD     ((ushort)0x0001)
-#define PA_ENET_TXD     ((ushort)0x0002)
-#define PA_ENET_TCLK    ((ushort)0x0200)
-#define PA_ENET_RCLK    ((ushort)0x0800)
-#define PC_ENET_TENA    ((ushort)0x0001)
-#define PC_ENET_CLSN    ((ushort)0x0010)
-#define PC_ENET_RENA    ((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK  ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000003d)
-#endif
-
-#ifdef CONFIG_RPXLITE
-/* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
- * this may be unique to the RPX-Lite configuration.
- * Note TENA is on Port B.
- */
-#define PA_ENET_RXD     ((ushort)0x0004)
-#define PA_ENET_TXD     ((ushort)0x0008)
-#define PA_ENET_TCLK    ((ushort)0x0200)
-#define PA_ENET_RCLK    ((ushort)0x0800)
-#define PB_ENET_TENA    ((uint)0x00002000)
-#define PC_ENET_CLSN    ((ushort)0x0040)
-#define PC_ENET_RENA    ((ushort)0x0080)
-
-#define SICR_ENET_MASK  ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003d00)
-#endif
-
-#ifdef CONFIG_BSEIP
-/* This ENET stuff is for the MPC823 with ethernet on SCC2.
- * This is unique to the BSE ip-Engine board.
- */
-#define PA_ENET_RXD     ((ushort)0x0004)
-#define PA_ENET_TXD     ((ushort)0x0008)
-#define PA_ENET_TCLK    ((ushort)0x0100)
-#define PA_ENET_RCLK    ((ushort)0x0200)
-#define PB_ENET_TENA    ((uint)0x00002000)
-#define PC_ENET_CLSN    ((ushort)0x0040)
-#define PC_ENET_RENA    ((ushort)0x0080)
-
-/* BSE uses port B and C bits for PHY control also.
-*/
-#define PB_BSE_POWERUP  ((uint)0x00000004)
-#define PB_BSE_FDXDIS   ((uint)0x00008000)
-#define PC_BSE_LOOPBACK ((ushort)0x0800)
-
-#define SICR_ENET_MASK  ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002c00)
-#endif
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
-#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
-#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
-#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
-#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
-#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
-
-/* SCC Mode Register (PMSR) as used by Ethernet.
-*/
-#define SCC_PMSR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
-#define SCC_PMSR_FC     ((ushort)0x4000)        /* Force collision */
-#define SCC_PMSR_RSH    ((ushort)0x2000)        /* Receive short frames */
-#define SCC_PMSR_IAM    ((ushort)0x1000)        /* Check individual hash */
-#define SCC_PMSR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
-#define SCC_PMSR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
-#define SCC_PMSR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
-#define SCC_PMSR_SBT    ((ushort)0x0080)        /* Special backoff timer */
-#define SCC_PMSR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
-#define SCC_PMSR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
-#define SCC_PMSR_LCW    ((ushort)0x0010)        /* Late collision window */
-#define SCC_PMSR_NIB22  ((ushort)0x000a)        /* Start frame search */
-#define SCC_PMSR_FDE    ((ushort)0x0001)        /* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
-*/
-#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
-#define BD_ENET_RX_WRAP         ((ushort)0x2000)
-#define BD_ENET_RX_INTR         ((ushort)0x1000)
-#define BD_ENET_RX_LAST         ((ushort)0x0800)
-#define BD_ENET_RX_FIRST        ((ushort)0x0400)
-#define BD_ENET_RX_MISS         ((ushort)0x0100)
-#define BD_ENET_RX_LG           ((ushort)0x0020)
-#define BD_ENET_RX_NO           ((ushort)0x0010)
-#define BD_ENET_RX_SH           ((ushort)0x0008)
-#define BD_ENET_RX_CR           ((ushort)0x0004)
-#define BD_ENET_RX_OV           ((ushort)0x0002)
-#define BD_ENET_RX_CL           ((ushort)0x0001)
-#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
-*/
-#define BD_ENET_TX_READY        ((ushort)0x8000)
-#define BD_ENET_TX_PAD          ((ushort)0x4000)
-#define BD_ENET_TX_WRAP         ((ushort)0x2000)
-#define BD_ENET_TX_INTR         ((ushort)0x1000)
-#define BD_ENET_TX_LAST         ((ushort)0x0800)
-#define BD_ENET_TX_TC           ((ushort)0x0400)
-#define BD_ENET_TX_DEF          ((ushort)0x0200)
-#define BD_ENET_TX_HB           ((ushort)0x0100)
-#define BD_ENET_TX_LC           ((ushort)0x0080)
-#define BD_ENET_TX_RL           ((ushort)0x0040)
-#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
-#define BD_ENET_TX_UN           ((ushort)0x0002)
-#define BD_ENET_TX_CSL          ((ushort)0x0001)
-#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-        sccp_t  scc_genscc;
-        uint    scc_res1;       /* Reserved */
-        uint    scc_res2;       /* Reserved */
-        ushort  scc_maxidl;     /* Maximum idle chars */
-        ushort  scc_idlc;       /* temp idle counter */
-        ushort  scc_brkcr;      /* Break count register */
-        ushort  scc_parec;      /* receive parity error counter */
-        ushort  scc_frmec;      /* receive framing error counter */
-        ushort  scc_nosec;      /* receive noise counter */
-        ushort  scc_brkec;      /* receive break condition counter */
-        ushort  scc_brkln;      /* last received break length */
-        ushort  scc_uaddr1;     /* UART address character 1 */
-        ushort  scc_uaddr2;     /* UART address character 2 */
-        ushort  scc_rtemp;      /* Temp storage */
-        ushort  scc_toseq;      /* Transmit out of sequence char */
-        ushort  scc_char1;      /* control character 1 */
-        ushort  scc_char2;      /* control character 2 */
-        ushort  scc_char3;      /* control character 3 */
-        ushort  scc_char4;      /* control character 4 */
-        ushort  scc_char5;      /* control character 5 */
-        ushort  scc_char6;      /* control character 6 */
-        ushort  scc_char7;      /* control character 7 */
-        ushort  scc_char8;      /* control character 8 */
-        ushort  scc_rccm;       /* receive control character mask */
-        ushort  scc_rccr;       /* receive control character register */
-        ushort  scc_rlbc;       /* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR           ((ushort)0x1000)
-#define UART_SCCM_GLT           ((ushort)0x0800)
-#define UART_SCCM_AB            ((ushort)0x0200)
-#define UART_SCCM_IDL           ((ushort)0x0100)
-#define UART_SCCM_GRA           ((ushort)0x0080)
-#define UART_SCCM_BRKE          ((ushort)0x0040)
-#define UART_SCCM_BRKS          ((ushort)0x0020)
-#define UART_SCCM_CCR           ((ushort)0x0008)
-#define UART_SCCM_BSY           ((ushort)0x0004)
-#define UART_SCCM_TX            ((ushort)0x0002)
-#define UART_SCCM_RX            ((ushort)0x0001)
-
-/* The SCC PMSR when used as a UART.
-*/
-#define SCU_PMSR_FLC            ((ushort)0x8000)
-#define SCU_PMSR_SL             ((ushort)0x4000)
-#define SCU_PMSR_CL             ((ushort)0x3000)
-#define SCU_PMSR_UM             ((ushort)0x0c00)
-#define SCU_PMSR_FRZ            ((ushort)0x0200)
-#define SCU_PMSR_RZS            ((ushort)0x0100)
-#define SCU_PMSR_SYN            ((ushort)0x0080)
-#define SCU_PMSR_DRT            ((ushort)0x0040)
-#define SCU_PMSR_PEN            ((ushort)0x0010)
-#define SCU_PMSR_RPM            ((ushort)0x000c)
-#define SCU_PMSR_REVP           ((ushort)0x0008)
-#define SCU_PMSR_TPM            ((ushort)0x0003)
-#define SCU_PMSR_TEVP           ((ushort)0x0003)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-        sccp_t  st_genscc;
-        uint    st_cpres;       /* Preset CRC */
-        uint    st_cmask;       /* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST          ((ushort)0x0800)
-
-
-
-/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
- * channels or devices.  All of these are presented to the PPC core
- * as a single interrupt.  The CPM interrupt handler dispatches its
- * own handlers, in a similar fashion to the PPC core handler.  We
- * use the table as defined in the manuals (i.e. no special high
- * priority and SCC1 == SCCa, etc...).
- */
-/* #define CPMVEC_NR            32 */
-/* #define      CPMVEC_PIO_PC15         ((ushort)0x1f) */
-/* #define      CPMVEC_SCC1             ((ushort)0x1e) */
-/* #define      CPMVEC_SCC2             ((ushort)0x1d) */
-/* #define      CPMVEC_SCC3             ((ushort)0x1c) */
-/* #define      CPMVEC_SCC4             ((ushort)0x1b) */
-/* #define      CPMVEC_PIO_PC14         ((ushort)0x1a) */
-/* #define      CPMVEC_TIMER1           ((ushort)0x19) */
-/* #define      CPMVEC_PIO_PC13         ((ushort)0x18) */
-/* #define      CPMVEC_PIO_PC12         ((ushort)0x17) */
-/* #define      CPMVEC_SDMA_CB_ERR      ((ushort)0x16) */
-/* #define CPMVEC_IDMA1         ((ushort)0x15) */
-/* #define CPMVEC_IDMA2         ((ushort)0x14) */
-/* #define CPMVEC_TIMER2                ((ushort)0x12) */
-/* #define CPMVEC_RISCTIMER     ((ushort)0x11) */
-/* #define CPMVEC_I2C           ((ushort)0x10) */
-/* #define      CPMVEC_PIO_PC11         ((ushort)0x0f) */
-/* #define      CPMVEC_PIO_PC10         ((ushort)0x0e) */
-/* #define CPMVEC_TIMER3                ((ushort)0x0c) */
-/* #define      CPMVEC_PIO_PC9          ((ushort)0x0b) */
-/* #define      CPMVEC_PIO_PC8          ((ushort)0x0a) */
-/* #define      CPMVEC_PIO_PC7          ((ushort)0x09) */
-/* #define CPMVEC_TIMER4                ((ushort)0x07) */
-/* #define      CPMVEC_PIO_PC6          ((ushort)0x06) */
-/* #define      CPMVEC_SPI              ((ushort)0x05) */
-/* #define      CPMVEC_SMC1             ((ushort)0x04) */
-/* #define      CPMVEC_SMC2             ((ushort)0x03) */
-/* #define      CPMVEC_PIO_PC5          ((ushort)0x02) */
-/* #define      CPMVEC_PIO_PC4          ((ushort)0x01) */
-/* #define      CPMVEC_ERROR            ((ushort)0x00) */
-
-extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
-
-/* CPM interrupt configuration vector.
-*/
-#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
-#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
-#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
-#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
-#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
-#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
-#define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
-#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
-#endif /* __CPM_360__ */
diff --git a/arch/m68knommu/include/asm/cputime.h b/arch/m68knommu/include/asm/cputime.h
deleted file mode 100644
index a0c4a660878d..000000000000
--- a/arch/m68knommu/include/asm/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __M68KNOMMU_CPUTIME_H
-#define __M68KNOMMU_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __M68KNOMMU_CPUTIME_H */
diff --git a/arch/m68knommu/include/asm/current.h b/arch/m68knommu/include/asm/current.h
deleted file mode 100644
index 53ee0f9f7cef..000000000000
--- a/arch/m68knommu/include/asm/current.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _M68KNOMMU_CURRENT_H
-#define _M68KNOMMU_CURRENT_H
-/*
- *      current.h
- *      (C) Copyright 2000, Lineo, David McCullough <davidm@uclinux.org>
- *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
- *
- *      rather than dedicate a register (as the m68k source does), we
- *      just keep a global,  we should probably just change it all to be
- *      current and lose _current_task.
- */
-
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct *get_current(void)
-{
-        return(current_thread_info()->task);
-}
-
-#define current get_current()
-
-#endif /* _M68KNOMMU_CURRENT_H */
diff --git a/arch/m68knommu/include/asm/dbg.h b/arch/m68knommu/include/asm/dbg.h
deleted file mode 100644
index 27af3270f671..000000000000
--- a/arch/m68knommu/include/asm/dbg.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#define DEBUG 1
-#ifdef CONFIG_COLDFIRE
-#define BREAK asm volatile ("halt")
-#else
-#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0
-#endif
diff --git a/arch/m68knommu/include/asm/delay.h b/arch/m68knommu/include/asm/delay.h
deleted file mode 100644
index 55cbd6294ab6..000000000000
--- a/arch/m68knommu/include/asm/delay.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef _M68KNOMMU_DELAY_H
-#define _M68KNOMMU_DELAY_H
-
-/*
- * Copyright (C) 1994 Hamish Macdonald
- * Copyright (C) 2004 Greg Ungerer <gerg@snapgear.com>
- */
-
-#include <asm/param.h>
-
-static inline void __delay(unsigned long loops)
-{
-#if defined(CONFIG_COLDFIRE)
-        /* The coldfire runs this loop at significantly different speeds
-         * depending upon long word alignment or not.  We'll pad it to
-         * long word alignment which is the faster version.
-         * The 0x4a8e is of course a 'tstl %fp' instruction.  This is better
-         * than using a NOP (0x4e71) instruction because it executes in one
-         * cycle not three and doesn't allow for an arbitary delay waiting
-         * for bus cycles to finish.  Also fp/a6 isn't likely to cause a
-         * stall waiting for the register to become valid if such is added
-         * to the coldfire at some stage.
-         */
-        __asm__ __volatile__ (  ".balignw 4, 0x4a8e\n\t"
-                                "1: subql #1, %0\n\t"
-                                "jcc 1b"
-                : "=d" (loops) : "0" (loops));
-#else
-        __asm__ __volatile__ (  "1: subql #1, %0\n\t"
-                                "jcc 1b"
-                : "=d" (loops) : "0" (loops));
-#endif
-}
-
-/*
- *      Ideally we use a 32*32->64 multiply to calculate the number of
- *      loop iterations, but the older standard 68k and ColdFire do not
- *      have this instruction. So for them we have a clsoe approximation
- *      loop using 32*32->32 multiplies only. This calculation based on
- *      the ARM version of delay.
- *
- *      We want to implement:
- *
- *      loops = (usecs * 0x10c6 * HZ * loops_per_jiffy) / 2^32
- */
-
-#define HZSCALE         (268435456 / (1000000/HZ))
-
-extern unsigned long loops_per_jiffy;
-
-static inline void _udelay(unsigned long usecs)
-{
-#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \
-    defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \
-    defined(CONFIG_COLDFIRE)
-        __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6);
-#else
-        unsigned long tmp;
-
-        usecs *= 4295;          /* 2**32 / 1000000 */
-        __asm__ ("mulul %2,%0:%1"
-                : "=d" (usecs), "=d" (tmp)
-                : "d" (usecs), "1" (loops_per_jiffy*HZ));
-        __delay(usecs);
-#endif
-}
-
-/*
- *      Moved the udelay() function into library code, no longer inlined.
- *      I had to change the algorithm because we are overflowing now on
- *      the faster ColdFire parts. The code is a little bigger, so it makes
- *      sense to library it.
- */
-extern void udelay(unsigned long usecs);
-
-#endif /* defined(_M68KNOMMU_DELAY_H) */
diff --git a/arch/m68knommu/include/asm/device.h b/arch/m68knommu/include/asm/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/arch/m68knommu/include/asm/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/arch/m68knommu/include/asm/div64.h b/arch/m68knommu/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/m68knommu/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/m68knommu/include/asm/dma-mapping.h b/arch/m68knommu/include/asm/dma-mapping.h
deleted file mode 100644
index 6aeab18e58bd..000000000000
--- a/arch/m68knommu/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _M68KNOMMU_DMA_MAPPING_H
-#define _M68KNOMMU_DMA_MAPPING_H
-
-#ifdef CONFIG_PCI
-#include <asm-generic/dma-mapping.h>
-#else
-#include <asm-generic/dma-mapping-broken.h>
-#endif
-
-#endif  /* _M68KNOMMU_DMA_MAPPING_H */
diff --git a/arch/m68knommu/include/asm/dma.h b/arch/m68knommu/include/asm/dma.h
deleted file mode 100644
index 939a02056217..000000000000
--- a/arch/m68knommu/include/asm/dma.h
+++ /dev/null
@@ -1,494 +0,0 @@
-#ifndef _M68K_DMA_H
-#define _M68K_DMA_H 1
- 
-//#define       DMA_DEBUG       1
-
-
-#ifdef CONFIG_COLDFIRE
-/*
- * ColdFire DMA Model:
- *   ColdFire DMA supports two forms of DMA: Single and Dual address. Single
- * address mode emits a source address, and expects that the device will either
- * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
- * the device will place data on the correct byte(s) of the data bus, as the
- * memory transactions are always 32 bits. This implies that only 32 bit
- * devices will find single mode transfers useful. Dual address DMA mode
- * performs two cycles: source read and destination write. ColdFire will
- * align the data so that the device will always get the correct bytes, thus
- * is useful for 8 and 16 bit devices. This is the mode that is supported
- * below.
- *
- * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000 
- *               Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
- *
- * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
- *               Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
- *
- * APR/18/2002 : added proper support for MCF5272 DMA controller.
- *               Arthur Shipkowski (art@videon-central.com)
- */
-
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfdma.h>
-
-/*
- * Set number of channels of DMA on ColdFire for different implementations.
- */
-#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
-        defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-#define MAX_M68K_DMA_CHANNELS 4
-#elif defined(CONFIG_M5272)
-#define MAX_M68K_DMA_CHANNELS 1
-#elif defined(CONFIG_M532x)
-#define MAX_M68K_DMA_CHANNELS 0
-#else
-#define MAX_M68K_DMA_CHANNELS 2
-#endif
-
-extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
-extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
-
-#if !defined(CONFIG_M5272)
-#define DMA_MODE_WRITE_BIT  0x01  /* Memory/IO to IO/Memory select */
-#define DMA_MODE_WORD_BIT   0x02  /* 8 or 16 bit transfers */
-#define DMA_MODE_LONG_BIT   0x04  /* or 32 bit transfers */
-#define DMA_MODE_SINGLE_BIT 0x08  /* single-address-mode */
-
-/* I/O to memory, 8 bits, mode */
-#define DMA_MODE_READ               0
-/* memory to I/O, 8 bits, mode */
-#define DMA_MODE_WRITE              1
-/* I/O to memory, 16 bits, mode */
-#define DMA_MODE_READ_WORD          2
-/* memory to I/O, 16 bits, mode */
-#define DMA_MODE_WRITE_WORD         3
-/* I/O to memory, 32 bits, mode */
-#define DMA_MODE_READ_LONG          4
-/* memory to I/O, 32 bits, mode */
-#define DMA_MODE_WRITE_LONG         5
-/* I/O to memory, 8 bits, single-address-mode */     
-#define DMA_MODE_READ_SINGLE        8
-/* memory to I/O, 8 bits, single-address-mode */
-#define DMA_MODE_WRITE_SINGLE       9
-/* I/O to memory, 16 bits, single-address-mode */
-#define DMA_MODE_READ_WORD_SINGLE  10
-/* memory to I/O, 16 bits, single-address-mode */
-#define DMA_MODE_WRITE_WORD_SINGLE 11
-/* I/O to memory, 32 bits, single-address-mode */
-#define DMA_MODE_READ_LONG_SINGLE  12
-/* memory to I/O, 32 bits, single-address-mode */
-#define DMA_MODE_WRITE_LONG_SINGLE 13
-
-#else /* CONFIG_M5272 is defined */
-
-/* Source static-address mode */
-#define DMA_MODE_SRC_SA_BIT 0x01  
-/* Two bits to select between all four modes */
-#define DMA_MODE_SSIZE_MASK 0x06 
-/* Offset to shift bits in */
-#define DMA_MODE_SSIZE_OFF  0x01  
-/* Destination static-address mode */
-#define DMA_MODE_DES_SA_BIT 0x10  
-/* Two bits to select between all four modes */
-#define DMA_MODE_DSIZE_MASK 0x60  
-/* Offset to shift bits in */
-#define DMA_MODE_DSIZE_OFF  0x05
-/* Size modifiers */
-#define DMA_MODE_SIZE_LONG  0x00
-#define DMA_MODE_SIZE_BYTE  0x01
-#define DMA_MODE_SIZE_WORD  0x02
-#define DMA_MODE_SIZE_LINE  0x03
-
-/* 
- * Aliases to help speed quick ports; these may be suboptimal, however. They
- * do not include the SINGLE mode modifiers since the MCF5272 does not have a
- * mode where the device is in control of its addressing.
- */
-
-/* I/O to memory, 8 bits, mode */
-#define DMA_MODE_READ                 ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
-/* memory to I/O, 8 bits, mode */
-#define DMA_MODE_WRITE              ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
-/* I/O to memory, 16 bits, mode */
-#define DMA_MODE_READ_WORD              ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
-/* memory to I/O, 16 bits, mode */
-#define DMA_MODE_WRITE_WORD         ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
-/* I/O to memory, 32 bits, mode */
-#define DMA_MODE_READ_LONG              ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
-/* memory to I/O, 32 bits, mode */
-#define DMA_MODE_WRITE_LONG         ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
-
-#endif /* !defined(CONFIG_M5272) */
-
-#if !defined(CONFIG_M5272)
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-  volatile unsigned short *dmawp;
-
-#ifdef DMA_DEBUG
-  printk("enable_dma(dmanr=%d)\n", dmanr);
-#endif
-
-  dmawp = (unsigned short *) dma_base_addr[dmanr];
-  dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-  volatile unsigned short *dmawp;
-  volatile unsigned char  *dmapb;
-
-#ifdef DMA_DEBUG
-  printk("disable_dma(dmanr=%d)\n", dmanr);
-#endif
-
-  dmawp = (unsigned short *) dma_base_addr[dmanr];
-  dmapb = (unsigned char *) dma_base_addr[dmanr];
-
-  /* Turn off external requests, and stop any DMA in progress */
-  dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
-  dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
-}
-
-/*
- * Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while interrupts are disabled! ---
- *
- * This is a NOP for ColdFire. Provide a stub for compatibility.
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-
-  volatile unsigned char  *dmabp;
-  volatile unsigned short *dmawp;
-
-#ifdef DMA_DEBUG
-  printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
-#endif
-
-  dmabp = (unsigned char *) dma_base_addr[dmanr];
-  dmawp = (unsigned short *) dma_base_addr[dmanr];
-
-  // Clear config errors
-  dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE; 
-
-  // Set command register
-  dmawp[MCFDMA_DCR] =
-    MCFDMA_DCR_INT |         // Enable completion irq
-    MCFDMA_DCR_CS |          // Force one xfer per request
-    MCFDMA_DCR_AA |          // Enable auto alignment
-    // single-address-mode
-    ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
-    // sets s_rw (-> r/w) high if Memory to I/0
-    ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
-    // Memory to I/O or I/O to Memory
-    ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
-    // 32 bit, 16 bit or 8 bit transfers
-    ((mode & DMA_MODE_WORD_BIT)  ? MCFDMA_DCR_SSIZE_WORD : 
-     ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
-                                   MCFDMA_DCR_SSIZE_BYTE)) |
-    ((mode & DMA_MODE_WORD_BIT)  ? MCFDMA_DCR_DSIZE_WORD :
-     ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
-                                   MCFDMA_DCR_DSIZE_BYTE));
-
-#ifdef DEBUG_DMA
-  printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
-         dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
-         (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
-#endif
-}
-
-/* Set transfer address for specific DMA channel */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-  volatile unsigned short *dmawp;
-  volatile unsigned int   *dmalp;
-
-#ifdef DMA_DEBUG
-  printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
-#endif
-
-  dmawp = (unsigned short *) dma_base_addr[dmanr];
-  dmalp = (unsigned int *) dma_base_addr[dmanr];
-
-  // Determine which address registers are used for memory/device accesses
-  if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
-    // Source incrementing, must be memory
-    dmalp[MCFDMA_SAR] = a;
-    // Set dest address, must be device
-    dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
-  } else {
-    // Destination incrementing, must be memory
-    dmalp[MCFDMA_DAR] = a;
-    // Set source address, must be device
-    dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
-  }
-
-#ifdef DEBUG_DMA
-  printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
-        __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
-        (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
-        (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
-#endif
-}
-
-/*
- * Specific for Coldfire - sets device address.
- * Should be called after the mode set call, and before set DMA address.
- */
-static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
-{
-#ifdef DMA_DEBUG
-  printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
-#endif
-
-  dma_device_address[dmanr] = a;
-}
-
-/*
- * NOTE 2: "count" represents _bytes_.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-  volatile unsigned short *dmawp;
-
-#ifdef DMA_DEBUG
-  printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
-#endif
-
-  dmawp = (unsigned short *) dma_base_addr[dmanr];
-  dmawp[MCFDMA_BCR] = (unsigned short)count;
-}
-
-/*
- * Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-  volatile unsigned short *dmawp;
-  unsigned short count;
-
-#ifdef DMA_DEBUG
-  printk("get_dma_residue(dmanr=%d)\n", dmanr);
-#endif
-
-  dmawp = (unsigned short *) dma_base_addr[dmanr];
-  count = dmawp[MCFDMA_BCR];
-  return((int) count);
-}
-#else /* CONFIG_M5272 is defined */
-
-/*
- * The MCF5272 DMA controller is very different than the controller defined above
- * in terms of register mapping.  For instance, with the exception of the 16-bit 
- * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
- *
- * The big difference, however, is the lack of device-requested DMA.  All modes
- * are dual address transfer, and there is no 'device' setup or direction bit.
- * You can DMA between a device and memory, between memory and memory, or even between
- * two devices directly, with any combination of incrementing and non-incrementing
- * addresses you choose.  This puts a crimp in distinguishing between the 'device 
- * address' set up by set_dma_device_addr.
- *
- * Therefore, there are two options.  One is to use set_dma_addr and set_dma_device_addr,
- * which will act exactly as above in -- it will look to see if the source is set to
- * autoincrement, and if so it will make the source use the set_dma_addr value and the
- * destination the set_dma_device_addr value.  Otherwise the source will be set to the
- * set_dma_device_addr value and the destination will get the set_dma_addr value.
- *
- * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
- * and make it explicit.  Depending on what you're doing, one of these two should work
- * for you, but don't mix them in the same transfer setup.
- */
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-  volatile unsigned int  *dmalp;
-
-#ifdef DMA_DEBUG
-  printk("enable_dma(dmanr=%d)\n", dmanr);
-#endif
-
-  dmalp = (unsigned int *) dma_base_addr[dmanr];
-  dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-  volatile unsigned int   *dmalp;
-
-#ifdef DMA_DEBUG
-  printk("disable_dma(dmanr=%d)\n", dmanr);
-#endif
-
-  dmalp = (unsigned int *) dma_base_addr[dmanr];
-
-  /* Turn off external requests, and stop any DMA in progress */
-  dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
-  dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
-}
-
-/*
- * Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while interrupts are disabled! ---
- *
- * This is a NOP for ColdFire. Provide a stub for compatibility.
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-
-  volatile unsigned int   *dmalp;
-  volatile unsigned short *dmawp;
-
-#ifdef DMA_DEBUG
-  printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
-#endif
-  dmalp = (unsigned int *) dma_base_addr[dmanr];
-  dmawp = (unsigned short *) dma_base_addr[dmanr];
-
-  // Clear config errors
-  dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; 
-
-  // Set command register
-  dmalp[MCFDMA_DMR] =
-    MCFDMA_DMR_RQM_DUAL |         // Mandatory Request Mode setting
-    MCFDMA_DMR_DSTT_SD  |         // Set up addressing types; set to supervisor-data.
-    MCFDMA_DMR_SRCT_SD  |         // Set up addressing types; set to supervisor-data. 
-    // source static-address-mode
-    ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
-    // dest static-address-mode
-    ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
-    // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272
-    (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
-    (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
-    
-  dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN;   /* Enable completion interrupts */
-  
-#ifdef DEBUG_DMA
-  printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
-         dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
-         (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
-#endif
-}
-
-/* Set transfer address for specific DMA channel */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-  volatile unsigned int   *dmalp;
-
-#ifdef DMA_DEBUG
-  printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
-#endif
-
-  dmalp = (unsigned int *) dma_base_addr[dmanr];
-
-  // Determine which address registers are used for memory/device accesses
-  if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
-    // Source incrementing, must be memory
-    dmalp[MCFDMA_DSAR] = a;
-    // Set dest address, must be device
-    dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
-  } else {
-    // Destination incrementing, must be memory
-    dmalp[MCFDMA_DDAR] = a;
-    // Set source address, must be device
-    dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
-  }
-
-#ifdef DEBUG_DMA
-  printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
-        __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
-        (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
-        (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
-#endif
-}
-
-/*
- * Specific for Coldfire - sets device address.
- * Should be called after the mode set call, and before set DMA address.
- */
-static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
-{
-#ifdef DMA_DEBUG
-  printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
-#endif
-
-  dma_device_address[dmanr] = a;
-}
-
-/*
- * NOTE 2: "count" represents _bytes_.
- *
- * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-  volatile unsigned int *dmalp;
-  
-#ifdef DMA_DEBUG
-  printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
-#endif
-
-  dmalp = (unsigned int *) dma_base_addr[dmanr];
-  dmalp[MCFDMA_DBCR] = count;
-}
-
-/*
- * Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-  volatile unsigned int *dmalp;
-  unsigned int count;
-
-#ifdef DMA_DEBUG
-  printk("get_dma_residue(dmanr=%d)\n", dmanr);
-#endif
-
-  dmalp = (unsigned int *) dma_base_addr[dmanr];
-  count = dmalp[MCFDMA_DBCR];
-  return(count);
-}
-
-#endif /* !defined(CONFIG_M5272) */
-#endif /* CONFIG_COLDFIRE */
- 
-#define MAX_DMA_CHANNELS 8
-
-/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
-   occurrence should be flagged as an error.  */
-/* under 2.4 it is actually needed by the new bootmem allocator */
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char *device_id);      /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
- 
-#endif /* _M68K_DMA_H */
diff --git a/arch/m68knommu/include/asm/elf.h b/arch/m68knommu/include/asm/elf.h
deleted file mode 100644
index b8046837f384..000000000000
--- a/arch/m68knommu/include/asm/elf.h
+++ /dev/null
@@ -1,110 +0,0 @@
-#ifndef __ASMm68k_ELF_H
-#define __ASMm68k_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/*
- * 68k ELF relocation types
- */
-#define R_68K_NONE  0
-#define R_68K_32    1
-#define R_68K_16    2
-#define R_68K_8     3
-#define R_68K_PC32  4
-#define R_68K_PC16  5
-#define R_68K_PC8   6
-#define R_68K_GOT32 7
-#define R_68K_GOT16 8
-#define R_68K_GOT8  9
-#define R_68K_GOT32O    10
-#define R_68K_GOT16O    11
-#define R_68K_GOT8O 12
-#define R_68K_PLT32 13
-#define R_68K_PLT16 14
-#define R_68K_PLT8  15
-#define R_68K_PLT32O    16
-#define R_68K_PLT16O    17
-#define R_68K_PLT8O 18
-#define R_68K_COPY  19
-#define R_68K_GLOB_DAT  20
-#define R_68K_JMP_SLOT  21
-#define R_68K_RELATIVE  22
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_m68kfp_struct elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_68K)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2MSB
-#define ELF_ARCH        EM_68K
-
-/* For SVR4/m68k the function pointer to be registered with `atexit' is
-   passed in %a1.  Although my copy of the ABI has no such statement, it
-   is actually used on ASV.  */
-#define ELF_PLAT_INIT(_r, load_addr)    _r->a1 = 0
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)                                \
-        /* Bleech. */                                                   \
-        pr_reg[0] = regs->d1;                                           \
-        pr_reg[1] = regs->d2;                                           \
-        pr_reg[2] = regs->d3;                                           \
-        pr_reg[3] = regs->d4;                                           \
-        pr_reg[4] = regs->d5;                                           \
-        pr_reg[7] = regs->a0;                                           \
-        pr_reg[8] = regs->a1;                                           \
-        pr_reg[14] = regs->d0;                                          \
-        pr_reg[15] = rdusp();                                           \
-        pr_reg[16] = 0 /* regs->orig_d0 */;                             \
-        pr_reg[17] = regs->sr;                                          \
-        pr_reg[18] = regs->pc;                                          \
-        /* pr_reg[19] = (regs->format << 12) | regs->vector; */         \
-        {                                                               \
-          struct switch_stack *sw = ((struct switch_stack *)regs) - 1;  \
-          pr_reg[5] = sw->d6;                                           \
-          pr_reg[6] = sw->d7;                                           \
-          pr_reg[10] = sw->a3;                                          \
-          pr_reg[11] = sw->a4;                                          \
-          pr_reg[12] = sw->a5;                                          \
-          pr_reg[13] = sw->a6;                                          \
-        }
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  */
-
-#define ELF_HWCAP       (0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.  */
-
-#define ELF_PLATFORM  (NULL)
-
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
-
-#endif
diff --git a/arch/m68knommu/include/asm/elia.h b/arch/m68knommu/include/asm/elia.h
deleted file mode 100644
index e037d4e2de33..000000000000
--- a/arch/m68knommu/include/asm/elia.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/****************************************************************************/
-
-/*
- *      elia.h -- Lineo (formerly Moreton Bay) eLIA platform support.
- *
- *      (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au)
- *      (C) Copyright 1999-2000, Lineo (www.lineo.com)
- */
-
-/****************************************************************************/
-#ifndef elia_h
-#define elia_h
-/****************************************************************************/
-
-#include <asm/coldfire.h>
-
-#ifdef CONFIG_eLIA
-
-/*
- *      The serial port DTR and DCD lines are also on the Parallel I/O
- *      as well, so define those too.
- */
-
-#define eLIA_DCD1               0x0001
-#define eLIA_DCD0               0x0002
-#define eLIA_DTR1               0x0004
-#define eLIA_DTR0               0x0008
-
-#define eLIA_PCIRESET           0x0020
-
-/*
- *      Kernel macros to set and unset the LEDs.
- */
-#ifndef __ASSEMBLY__
-extern unsigned short   ppdata;
-#endif /* __ASSEMBLY__ */
-
-#endif  /* CONFIG_eLIA */
-
-/****************************************************************************/
-#endif  /* elia_h */
diff --git a/arch/m68knommu/include/asm/emergency-restart.h b/arch/m68knommu/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/arch/m68knommu/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/m68knommu/include/asm/entry.h b/arch/m68knommu/include/asm/entry.h
deleted file mode 100644
index c2553d26273d..000000000000
--- a/arch/m68knommu/include/asm/entry.h
+++ /dev/null
@@ -1,182 +0,0 @@
-#ifndef __M68KNOMMU_ENTRY_H
-#define __M68KNOMMU_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-/*
- * Stack layout in 'ret_from_exception':
- *
- * This allows access to the syscall arguments in registers d1-d5
- *
- *       0(sp) - d1
- *       4(sp) - d2
- *       8(sp) - d3
- *       C(sp) - d4
- *      10(sp) - d5
- *      14(sp) - a0
- *      18(sp) - a1
- *      1C(sp) - a2
- *      20(sp) - d0
- *      24(sp) - orig_d0
- *      28(sp) - stack adjustment
- *      2C(sp) - [ sr              ] [ format & vector ]
- *      2E(sp) - [ pc-hiword       ] [ sr              ]
- *      30(sp) - [ pc-loword       ] [ pc-hiword       ]
- *      32(sp) - [ format & vector ] [ pc-loword       ]
- *                ^^^^^^^^^^^^^^^^^   ^^^^^^^^^^^^^^^^^
- *                      M68K              COLDFIRE
- */
-
-#define ALLOWINT 0xf8ff
-
-#ifdef __ASSEMBLY__
-
-/* process bits for task_struct.flags */
-PF_TRACESYS_OFF = 3
-PF_TRACESYS_BIT = 5
-PF_PTRACED_OFF = 3
-PF_PTRACED_BIT = 4
-PF_DTRACE_OFF = 1
-PF_DTRACE_BIT = 5
-
-LENOSYS = 38
-
-#define SWITCH_STACK_SIZE (6*4+4)       /* Includes return address */
-
-/*
- * This defines the normal kernel pt-regs layout.
- *
- * regs are a2-a6 and d6-d7 preserved by C code
- * the kernel doesn't mess with usp unless it needs to
- */
-
-#ifdef CONFIG_COLDFIRE
-/*
- * This is made a little more tricky on the ColdFire. There is no
- * separate kernel and user stack pointers. Need to artificially
- * construct a usp in software... When doing this we need to disable
- * interrupts, otherwise bad things could happen.
- */
-.macro SAVE_ALL
-        move    #0x2700,%sr             /* disable intrs */
-        btst    #5,%sp@(2)              /* from user? */
-        bnes    6f                      /* no, skip */
-        movel   %sp,sw_usp              /* save user sp */
-        addql   #8,sw_usp               /* remove exception */
-        movel   sw_ksp,%sp              /* kernel sp */
-        subql   #8,%sp                  /* room for exception */
-        clrl    %sp@-                   /* stkadj */
-        movel   %d0,%sp@-               /* orig d0 */
-        movel   %d0,%sp@-               /* d0 */
-        lea     %sp@(-32),%sp           /* space for 8 regs */
-        moveml  %d1-%d5/%a0-%a2,%sp@
-        movel   sw_usp,%a0              /* get usp */
-        movel   %a0@-,%sp@(PT_PC)       /* copy exception program counter */
-        movel   %a0@-,%sp@(PT_FORMATVEC)/* copy exception format/vector/sr */
-        bra     7f
-        6:
-        clrl    %sp@-                   /* stkadj */
-        movel   %d0,%sp@-               /* orig d0 */
-        movel   %d0,%sp@-               /* d0 */
-        lea     %sp@(-32),%sp           /* space for 8 regs */
-        moveml  %d1-%d5/%a0-%a2,%sp@
-        7:
-.endm
-
-.macro RESTORE_ALL
-        btst    #5,%sp@(PT_SR)          /* going user? */
-        bnes    8f                      /* no, skip */
-        move    #0x2700,%sr             /* disable intrs */
-        movel   sw_usp,%a0              /* get usp */
-        movel   %sp@(PT_PC),%a0@-       /* copy exception program counter */
-        movel   %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */
-        moveml  %sp@,%d1-%d5/%a0-%a2
-        lea     %sp@(32),%sp            /* space for 8 regs */
-        movel   %sp@+,%d0
-        addql   #4,%sp                  /* orig d0 */
-        addl    %sp@+,%sp               /* stkadj */
-        addql   #8,%sp                  /* remove exception */
-        movel   %sp,sw_ksp              /* save ksp */
-        subql   #8,sw_usp               /* set exception */
-        movel   sw_usp,%sp              /* restore usp */
-        rte
-        8:
-        moveml  %sp@,%d1-%d5/%a0-%a2
-        lea     %sp@(32),%sp            /* space for 8 regs */
-        movel   %sp@+,%d0
-        addql   #4,%sp                  /* orig d0 */
-        addl    %sp@+,%sp               /* stkadj */
-        rte
-.endm
-
-/*
- * Quick exception save, use current stack only.
- */
-.macro SAVE_LOCAL
-        move    #0x2700,%sr             /* disable intrs */
-        clrl    %sp@-                   /* stkadj */
-        movel   %d0,%sp@-               /* orig d0 */
-        movel   %d0,%sp@-               /* d0 */
-        lea     %sp@(-32),%sp           /* space for 8 regs */
-        moveml  %d1-%d5/%a0-%a2,%sp@
-.endm
-
-.macro RESTORE_LOCAL
-        moveml  %sp@,%d1-%d5/%a0-%a2
-        lea     %sp@(32),%sp            /* space for 8 regs */
-        movel   %sp@+,%d0
-        addql   #4,%sp                  /* orig d0 */
-        addl    %sp@+,%sp               /* stkadj */
-        rte
-.endm
-
-.macro SAVE_SWITCH_STACK
-        lea     %sp@(-24),%sp           /* 6 regs */
-        moveml  %a3-%a6/%d6-%d7,%sp@
-.endm
-
-.macro RESTORE_SWITCH_STACK
-        moveml  %sp@,%a3-%a6/%d6-%d7
-        lea     %sp@(24),%sp            /* 6 regs */
-.endm
-
-/*
- * Software copy of the user and kernel stack pointers... Ugh...
- * Need these to get around ColdFire not having separate kernel
- * and user stack pointers.
- */
-.globl sw_usp
-.globl sw_ksp
-
-#else /* !CONFIG_COLDFIRE */
-
-/*
- * Standard 68k interrupt entry and exit macros.
- */
-.macro SAVE_ALL
-        clrl    %sp@-                   /* stkadj */
-        movel   %d0,%sp@-               /* orig d0 */
-        movel   %d0,%sp@-               /* d0 */
-        moveml  %d1-%d5/%a0-%a2,%sp@-
-.endm
-
-.macro RESTORE_ALL
-        moveml  %sp@+,%a0-%a2/%d1-%d5
-        movel   %sp@+,%d0
-        addql   #4,%sp                  /* orig d0 */
-        addl    %sp@+,%sp               /* stkadj */
-        rte
-.endm
-
-.macro SAVE_SWITCH_STACK
-        moveml  %a3-%a6/%d6-%d7,%sp@-
-.endm
-
-.macro RESTORE_SWITCH_STACK
-        moveml  %sp@+,%a3-%a6/%d6-%d7
-.endm
-
-#endif /* !CONFIG_COLDFIRE */
-#endif /* __ASSEMBLY__ */
-#endif /* __M68KNOMMU_ENTRY_H */
diff --git a/arch/m68knommu/include/asm/errno.h b/arch/m68knommu/include/asm/errno.h
deleted file mode 100644
index 7e8c22b9a5e6..000000000000
--- a/arch/m68knommu/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/errno.h>
diff --git a/arch/m68knommu/include/asm/fb.h b/arch/m68knommu/include/asm/fb.h
deleted file mode 100644
index c7df38030992..000000000000
--- a/arch/m68knommu/include/asm/fb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/fb.h>
-
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-        return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/arch/m68knommu/include/asm/fcntl.h b/arch/m68knommu/include/asm/fcntl.h
deleted file mode 100644
index f6a552cda4cd..000000000000
--- a/arch/m68knommu/include/asm/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/fcntl.h>
diff --git a/arch/m68knommu/include/asm/flat.h b/arch/m68knommu/include/asm/flat.h
deleted file mode 100644
index 814b5174a8e0..000000000000
--- a/arch/m68knommu/include/asm/flat.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * include/asm-m68knommu/flat.h -- uClinux flat-format executables
- */
-
-#ifndef __M68KNOMMU_FLAT_H__
-#define __M68KNOMMU_FLAT_H__
-
-#define flat_stack_align(sp)                    /* nothing needed */
-#define flat_argvp_envp_on_stack()              1
-#define flat_old_ram_flag(flags)                (flags)
-#define flat_reloc_valid(reloc, size)           ((reloc) <= (size))
-#define flat_get_addr_from_rp(rp, relval, flags, p)     get_unaligned(rp)
-#define flat_put_addr_at_rp(rp, val, relval)    put_unaligned(val,rp)
-#define flat_get_relocate_addr(rel)             (rel)
-#define flat_set_persistent(relval, p)          0
-
-#endif /* __M68KNOMMU_FLAT_H__ */
diff --git a/arch/m68knommu/include/asm/fpu.h b/arch/m68knommu/include/asm/fpu.h
deleted file mode 100644
index b16b2e4fca2a..000000000000
--- a/arch/m68knommu/include/asm/fpu.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __M68KNOMMU_FPU_H
-#define __M68KNOMMU_FPU_H
-
-
-/*
- * MAX floating point unit state size (FSAVE/FRESTORE)
- */
-#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
-#define FPSTATESIZE (216/sizeof(unsigned char))
-#elif defined(CONFIG_M68040)
-#define FPSTATESIZE (96/sizeof(unsigned char))
-#elif defined(CONFIG_M68KFPU_EMU)
-#define FPSTATESIZE (28/sizeof(unsigned char))
-#elif defined(CONFIG_M68060)
-#define FPSTATESIZE (12/sizeof(unsigned char))
-#else
-/* Assume no FP unit present then... */
-#define FPSTATESIZE (2) /* dummy size */
-#endif
-
-#endif /* __M68K_FPU_H */
diff --git a/arch/m68knommu/include/asm/futex.h b/arch/m68knommu/include/asm/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/arch/m68knommu/include/asm/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/arch/m68knommu/include/asm/hardirq.h b/arch/m68knommu/include/asm/hardirq.h
deleted file mode 100644
index bfad28149a49..000000000000
--- a/arch/m68knommu/include/asm/hardirq.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __M68K_HARDIRQ_H
-#define __M68K_HARDIRQ_H
-
-#include <linux/cache.h>
-#include <linux/threads.h>
-#include <asm/irq.h>
-
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-#define HARDIRQ_BITS    8
-
-/*
- * The hardirq mask has to be large enough to have
- * space for potentially all IRQ sources in the system
- * nesting on a single CPU:
- */
-#if (1 << HARDIRQ_BITS) < NR_IRQS
-# error HARDIRQ_BITS is too low!
-#endif
-
-void ack_bad_irq(unsigned int irq);
-
-#endif /* __M68K_HARDIRQ_H */
diff --git a/arch/m68knommu/include/asm/hw_irq.h b/arch/m68knommu/include/asm/hw_irq.h
deleted file mode 100644
index f3ec9e5ae049..000000000000
--- a/arch/m68knommu/include/asm/hw_irq.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __M68KNOMMU_HW_IRQ_H__
-#define __M68KNOMMU_HW_IRQ_H__
-
-#endif /* __M68KNOMMU_HW_IRQ_H__ */
diff --git a/arch/m68knommu/include/asm/hwtest.h b/arch/m68knommu/include/asm/hwtest.h
deleted file mode 100644
index 700626a1b1bf..000000000000
--- a/arch/m68knommu/include/asm/hwtest.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/hwtest.h>
diff --git a/arch/m68knommu/include/asm/io.h b/arch/m68knommu/include/asm/io.h
deleted file mode 100644
index 6adef1ee2082..000000000000
--- a/arch/m68knommu/include/asm/io.h
+++ /dev/null
@@ -1,194 +0,0 @@
-#ifndef _M68KNOMMU_IO_H
-#define _M68KNOMMU_IO_H
-
-#ifdef __KERNEL__
-
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the m68k architecture, we just read/write the
- * memory location directly.
- */
-/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
- * two accesses to memory, which may be undesireable for some devices.
- */
-
-/*
- * swap functions are sometimes needed to interface little-endian hardware
- */
-static inline unsigned short _swapw(volatile unsigned short v)
-{
-    return ((v << 8) | (v >> 8));
-}
-
-static inline unsigned int _swapl(volatile unsigned long v)
-{
-    return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
-}
-
-#define readb(addr) \
-    ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
-#define readw(addr) \
-    ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
-#define readl(addr) \
-    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-static inline void io_outsb(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned char *ap = (volatile unsigned char *) addr;
-        unsigned char *bp = (unsigned char *) buf;
-        while (len--)
-                *ap = *bp++;
-}
-
-static inline void io_outsw(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned short *ap = (volatile unsigned short *) addr;
-        unsigned short *bp = (unsigned short *) buf;
-        while (len--)
-                *ap = _swapw(*bp++);
-}
-
-static inline void io_outsl(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned int *ap = (volatile unsigned int *) addr;
-        unsigned int *bp = (unsigned int *) buf;
-        while (len--)
-                *ap = _swapl(*bp++);
-}
-
-static inline void io_insb(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned char *ap = (volatile unsigned char *) addr;
-        unsigned char *bp = (unsigned char *) buf;
-        while (len--)
-                *bp++ = *ap;
-}
-
-static inline void io_insw(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned short *ap = (volatile unsigned short *) addr;
-        unsigned short *bp = (unsigned short *) buf;
-        while (len--)
-                *bp++ = _swapw(*ap);
-}
-
-static inline void io_insl(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned int *ap = (volatile unsigned int *) addr;
-        unsigned int *bp = (unsigned int *) buf;
-        while (len--)
-                *bp++ = _swapl(*ap);
-}
-
-#define mmiowb()
-
-/*
- *      make the short names macros so specific devices
- *      can override them as required
- */
-
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
-
-#define inb(addr)    readb(addr)
-#define inw(addr)    readw(addr)
-#define inl(addr)    readl(addr)
-#define outb(x,addr) ((void) writeb(x,addr))
-#define outw(x,addr) ((void) writew(x,addr))
-#define outl(x,addr) ((void) writel(x,addr))
-
-#define inb_p(addr)    inb(addr)
-#define inw_p(addr)    inw(addr)
-#define inl_p(addr)    inl(addr)
-#define outb_p(x,addr) outb(x,addr)
-#define outw_p(x,addr) outw(x,addr)
-#define outl_p(x,addr) outl(x,addr)
-
-#define outsb(a,b,l) io_outsb(a,b,l)
-#define outsw(a,b,l) io_outsw(a,b,l)
-#define outsl(a,b,l) io_outsl(a,b,l)
-
-#define insb(a,b,l) io_insb(a,b,l)
-#define insw(a,b,l) io_insw(a,b,l)
-#define insl(a,b,l) io_insl(a,b,l)
-
-#define IO_SPACE_LIMIT 0xffff
-
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_FULL_CACHING              0
-#define IOMAP_NOCACHE_SER               1
-#define IOMAP_NOCACHE_NONSER            2
-#define IOMAP_WRITETHROUGH              3
-
-extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
-extern void __iounmap(void *addr, unsigned long size);
-
-static inline void *ioremap(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
-}
-static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
-}
-
-extern void iounmap(void *addr);
-
-/* Pages to physical address... */
-#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
-#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
-
-/*
- * Macros used for converting between virtual and physical mappings.
- */
-#define phys_to_virt(vaddr)     ((void *) (vaddr))
-#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif /* __KERNEL__ */
-
-#endif /* _M68KNOMMU_IO_H */
diff --git a/arch/m68knommu/include/asm/ioctl.h b/arch/m68knommu/include/asm/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/arch/m68knommu/include/asm/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/arch/m68knommu/include/asm/ioctls.h b/arch/m68knommu/include/asm/ioctls.h
deleted file mode 100644
index 0b1eb4d85059..000000000000
--- a/arch/m68knommu/include/asm/ioctls.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/ioctls.h>
diff --git a/arch/m68knommu/include/asm/ipcbuf.h b/arch/m68knommu/include/asm/ipcbuf.h
deleted file mode 100644
index e4a7be6dd706..000000000000
--- a/arch/m68knommu/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/ipcbuf.h>
diff --git a/arch/m68knommu/include/asm/irq.h b/arch/m68knommu/include/asm/irq.h
deleted file mode 100644
index 9373c31ac87d..000000000000
--- a/arch/m68knommu/include/asm/irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef _M68KNOMMU_IRQ_H_
-#define _M68KNOMMU_IRQ_H_
-
-#ifdef CONFIG_COLDFIRE
-/*
- * On the ColdFire we keep track of all vectors. That way drivers
- * can register whatever vector number they wish, and we can deal
- * with it.
- */
-#define SYS_IRQS        256
-#define NR_IRQS         SYS_IRQS
-
-#else
-
-/*
- * # of m68k interrupts
- */
-#define SYS_IRQS        8
-#define NR_IRQS         (24 + SYS_IRQS)
-
-#endif /* CONFIG_COLDFIRE */
-
-
-#define irq_canonicalize(irq)   (irq)
-
-#endif /* _M68KNOMMU_IRQ_H_ */
diff --git a/arch/m68knommu/include/asm/irq_regs.h b/arch/m68knommu/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/m68knommu/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/m68knommu/include/asm/kdebug.h b/arch/m68knommu/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/m68knommu/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/m68knommu/include/asm/kmap_types.h b/arch/m68knommu/include/asm/kmap_types.h
deleted file mode 100644
index bfb6707575d1..000000000000
--- a/arch/m68knommu/include/asm/kmap_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __ASM_M68K_KMAP_TYPES_H
-#define __ASM_M68K_KMAP_TYPES_H
-
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
-
-#endif
diff --git a/arch/m68knommu/include/asm/linkage.h b/arch/m68knommu/include/asm/linkage.h
deleted file mode 100644
index c288a19ff489..000000000000
--- a/arch/m68knommu/include/asm/linkage.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/linkage.h>
diff --git a/arch/m68knommu/include/asm/local.h b/arch/m68knommu/include/asm/local.h
deleted file mode 100644
index 84a39c1b86f8..000000000000
--- a/arch/m68knommu/include/asm/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __M68KNOMMU_LOCAL_H
-#define __M68KNOMMU_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif /* __M68KNOMMU_LOCAL_H */
diff --git a/arch/m68knommu/include/asm/m5206sim.h b/arch/m68knommu/include/asm/m5206sim.h
deleted file mode 100644
index 7e3594dea88b..000000000000
--- a/arch/m68knommu/include/asm/m5206sim.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m5206sim.h -- ColdFire 5206 System Integration Module support.
- *
- *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com) 
- */
-
-/****************************************************************************/
-#ifndef m5206sim_h
-#define m5206sim_h
-/****************************************************************************/
-
-
-/*
- *      Define the 5206 SIM register set addresses.
- */
-#define MCFSIM_SIMR             0x03            /* SIM Config reg (r/w) */
-#define MCFSIM_ICR1             0x14            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x15            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x16            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x17            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x18            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x19            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x1a            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x1b            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x1c            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x1d            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x1e            /* Intr Ctrl reg 11 (r/w) */
-#define MCFSIM_ICR12            0x1f            /* Intr Ctrl reg 12 (r/w) */
-#define MCFSIM_ICR13            0x20            /* Intr Ctrl reg 13 (r/w) */
-#ifdef CONFIG_M5206e
-#define MCFSIM_ICR14            0x21            /* Intr Ctrl reg 14 (r/w) */
-#define MCFSIM_ICR15            0x22            /* Intr Ctrl reg 15 (r/w) */
-#endif
-
-#define MCFSIM_IMR              0x36            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_IPR              0x3a            /* Interrupt Pend reg (r/w) */
-
-#define MCFSIM_RSR              0x40            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x41            /* System Protection reg (r/w)*/
-
-#define MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */
-
-#define MCFSIM_DCRR             0x46            /* DRAM Refresh reg (r/w) */
-#define MCFSIM_DCTR             0x4a            /* DRAM Timing reg (r/w) */
-#define MCFSIM_DAR0             0x4c            /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DMR0             0x50            /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCR0             0x57            /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DAR1             0x58            /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DMR1             0x5c            /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCR1             0x63            /* DRAM 1 Control reg (r/w) */
-
-#define MCFSIM_CSAR0            0x64            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x68            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x6e            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x70            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x74            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x7a            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x7c            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x80            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0x86            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0x88            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0x8c            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0x92            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0x94            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0x98            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0x9e            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xa0            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xa4            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xaa            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xac            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xb0            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xb6            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xb8            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xbc            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xc2            /* CS 7 Control reg (r/w) */
-#define MCFSIM_DMCR             0xc6            /* Default control */
-
-#ifdef CONFIG_M5206e
-#define MCFSIM_PAR              0xca            /* Pin Assignment reg (r/w) */
-#else
-#define MCFSIM_PAR              0xcb            /* Pin Assignment reg (r/w) */
-#endif
-
-#define MCFSIM_PADDR            0x1c5           /* Parallel Direction (r/w) */
-#define MCFSIM_PADAT            0x1c9           /* Parallel Port Value (r/w) */
-
-/*
- *      Some symbol defines for the Parallel Port Pin Assignment Register
- */
-#ifdef CONFIG_M5206e
-#define MCFSIM_PAR_DREQ0        0x100           /* Set to select DREQ0 input */
-                                                /* Clear to select T0 input */
-#define MCFSIM_PAR_DREQ1        0x200           /* Select DREQ1 input */
-                                                /* Clear to select T0 output */
-#endif
-
-/*
- *      Some symbol defines for the Interrupt Control Register
- */
-#define MCFSIM_SWDICR           MCFSIM_ICR8     /* Watchdog timer ICR */
-#define MCFSIM_TIMER1ICR        MCFSIM_ICR9     /* Timer 1 ICR */
-#define MCFSIM_TIMER2ICR        MCFSIM_ICR10    /* Timer 2 ICR */
-#define MCFSIM_UART1ICR         MCFSIM_ICR12    /* UART 1 ICR */
-#define MCFSIM_UART2ICR         MCFSIM_ICR13    /* UART 2 ICR */
-#ifdef CONFIG_M5206e
-#define MCFSIM_DMA1ICR          MCFSIM_ICR14    /* DMA 1 ICR */
-#define MCFSIM_DMA2ICR          MCFSIM_ICR15    /* DMA 2 ICR */
-#endif
-
-#if defined(CONFIG_M5206e)
-#define MCFSIM_IMR_MASKALL      0xfffe          /* All SIM intr sources */
-#endif
-
-/*
- *      Macro to get and set IMR register. It is 16 bits on the 5206.
- */
-#define mcf_getimr()            \
-        *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
-
-#define mcf_setimr(imr)         \
-        *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
-
-#define mcf_getipr()            \
-        *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
-
-/****************************************************************************/
-#endif  /* m5206sim_h */
diff --git a/arch/m68knommu/include/asm/m520xsim.h b/arch/m68knommu/include/asm/m520xsim.h
deleted file mode 100644
index 49d016e6391a..000000000000
--- a/arch/m68knommu/include/asm/m520xsim.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/****************************************************************************/
-
-/*
- *  m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
- *
- *  (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
- */
-
-/****************************************************************************/
-#ifndef m520xsim_h
-#define m520xsim_h
-/****************************************************************************/
-
-
-/*
- *  Define the 5282 SIM register set addresses.
- */
-#define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
-#define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
-#define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
-#define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
-#define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
-#define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
-#define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
-#define MCFINTC_ICR0        0x40        /* Base ICR register */
-
-#define MCFINT_VECBASE      64
-#define MCFINT_UART0        26          /* Interrupt number for UART0 */
-#define MCFINT_UART1        27          /* Interrupt number for UART1 */
-#define MCFINT_UART2        28          /* Interrupt number for UART2 */
-#define MCFINT_QSPI         31          /* Interrupt number for QSPI */
-#define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */
-
-/*
- *  SDRAM configuration registers.
- */
-#define MCFSIM_SDMR         0x000a8000  /* SDRAM Mode/Extended Mode Register */
-#define MCFSIM_SDCR         0x000a8004  /* SDRAM Control Register */
-#define MCFSIM_SDCFG1       0x000a8008  /* SDRAM Configuration Register 1 */
-#define MCFSIM_SDCFG2       0x000a800c  /* SDRAM Configuration Register 2 */
-#define MCFSIM_SDCS0        0x000a8110  /* SDRAM Chip Select 0 Configuration */
-#define MCFSIM_SDCS1        0x000a8114  /* SDRAM Chip Select 1 Configuration */
-
-
-#define MCF_GPIO_PAR_UART                   (0xA4036)
-#define MCF_GPIO_PAR_FECI2C                 (0xA4033)
-#define MCF_GPIO_PAR_FEC                    (0xA4038)
-
-#define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
-#define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
-
-#define MCF_GPIO_PAR_UART_PAR_URXD1         (0x0040)
-#define MCF_GPIO_PAR_UART_PAR_UTXD1         (0x0080)
-
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
-
-#define ICR_INTRCONF            0x05
-#define MCFPIT_IMR              MCFINTC_IMRL
-#define MCFPIT_IMR_IBIT         (1 << MCFINT_PIT1)
-
-/****************************************************************************/
-#endif  /* m520xsim_h */
diff --git a/arch/m68knommu/include/asm/m523xsim.h b/arch/m68knommu/include/asm/m523xsim.h
deleted file mode 100644
index bf397313e93f..000000000000
--- a/arch/m68knommu/include/asm/m523xsim.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m523xsim.h -- ColdFire 523x System Integration Module support.
- *
- *      (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
- */
-
-/****************************************************************************/
-#ifndef m523xsim_h
-#define m523xsim_h
-/****************************************************************************/
-
-
-/*
- *      Define the 523x SIM register set addresses.
- */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 0 */
-#define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
-#define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
-#define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
-#define MCFINTC_IMRL            0x0c            /* Interrupt mask 1-31 */
-#define MCFINTC_INTFRCH         0x10            /* Interrupt force 32-63 */
-#define MCFINTC_INTFRCL         0x14            /* Interrupt force 1-31 */
-#define MCFINTC_IRLR            0x18            /* */
-#define MCFINTC_IACKL           0x19            /* */
-#define MCFINTC_ICR0            0x40            /* Base ICR register */
-
-#define MCFINT_VECBASE          64              /* Vector base number */
-#define MCFINT_UART0            13              /* Interrupt number for UART0 */
-#define MCFINT_PIT1             36              /* Interrupt number for PIT1 */
-#define MCFINT_QSPI             18              /* Interrupt number for QSPI */
-
-/*
- *      SDRAM configuration registers.
- */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
-
-/****************************************************************************/
-#endif  /* m523xsim_h */
diff --git a/arch/m68knommu/include/asm/m5249sim.h b/arch/m68knommu/include/asm/m5249sim.h
deleted file mode 100644
index 366eb8602d2f..000000000000
--- a/arch/m68knommu/include/asm/m5249sim.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m5249sim.h -- ColdFire 5249 System Integration Module support.
- *
- *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
- */
-
-/****************************************************************************/
-#ifndef m5249sim_h
-#define m5249sim_h
-/****************************************************************************/
-
-/*
- *      Define the 5249 SIM register set addresses.
- */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
-
-
-/*
- *      Some symbol defines for the above...
- */
-#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
-#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
-#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
-#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
-#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
-#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
-#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
-#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
-#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
-
-/*
- *      General purpose IO registers (in MBAR2).
- */
-#define MCFSIM2_GPIOREAD        0x0             /* GPIO read values */
-#define MCFSIM2_GPIOWRITE       0x4             /* GPIO write values */
-#define MCFSIM2_GPIOENABLE      0x8             /* GPIO enabled */
-#define MCFSIM2_GPIOFUNC        0xc             /* GPIO function */
-#define MCFSIM2_GPIO1READ       0xb0            /* GPIO1 read values */
-#define MCFSIM2_GPIO1WRITE      0xb4            /* GPIO1 write values */
-#define MCFSIM2_GPIO1ENABLE     0xb8            /* GPIO1 enabled */
-#define MCFSIM2_GPIO1FUNC       0xbc            /* GPIO1 function */
-
-#define MCFSIM2_GPIOINTSTAT     0xc0            /* GPIO interrupt status */
-#define MCFSIM2_GPIOINTCLEAR    0xc0            /* GPIO interrupt clear */
-#define MCFSIM2_GPIOINTENABLE   0xc4            /* GPIO interrupt enable */
-
-#define MCFSIM2_INTLEVEL1       0x140           /* Interrupt level reg 1 */
-#define MCFSIM2_INTLEVEL2       0x144           /* Interrupt level reg 2 */
-#define MCFSIM2_INTLEVEL3       0x148           /* Interrupt level reg 3 */
-#define MCFSIM2_INTLEVEL4       0x14c           /* Interrupt level reg 4 */
-#define MCFSIM2_INTLEVEL5       0x150           /* Interrupt level reg 5 */
-#define MCFSIM2_INTLEVEL6       0x154           /* Interrupt level reg 6 */
-#define MCFSIM2_INTLEVEL7       0x158           /* Interrupt level reg 7 */
-#define MCFSIM2_INTLEVEL8       0x15c           /* Interrupt level reg 8 */
-
-#define MCFSIM2_DMAROUTE        0x188           /* DMA routing */
-
-#define MCFSIM2_IDECONFIG1      0x18c           /* IDEconfig1 */
-#define MCFSIM2_IDECONFIG2      0x190           /* IDEconfig2 */
-
-
-/*
- *      Macro to set IMR register. It is 32 bits on the 5249.
- */
-#define MCFSIM_IMR_MASKALL      0x7fffe         /* All SIM intr sources */
-
-#define mcf_getimr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
-
-#define mcf_setimr(imr)         \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
-
-#define mcf_getipr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
-
-/****************************************************************************/
-
-#ifdef __ASSEMBLER__
-
-/*
- *      The M5249C3 board needs a little help getting all its SIM devices
- *      initialized at kernel start time. dBUG doesn't set much up, so
- *      we need to do it manually.
- */
-.macro m5249c3_setup
-        /*
-         *      Set MBAR1 and MBAR2, just incase they are not set.
-         */
-        movel   #0x10000001,%a0
-        movec   %a0,%MBAR                       /* map MBAR region */
-        subql   #1,%a0                          /* get MBAR address in a0 */
-
-        movel   #0x80000001,%a1
-        movec   %a1,#3086                       /* map MBAR2 region */
-        subql   #1,%a1                          /* get MBAR2 address in a1 */
-
-        /*
-         *      Move secondary interrupts to base at 128.
-         */
-        moveb   #0x80,%d0
-        moveb   %d0,0x16b(%a1)                  /* interrupt base register */
-
-        /*
-         *      Work around broken CSMR0/DRAM vector problem.
-         */
-        movel   #0x001F0021,%d0                 /* disable C/I bit */
-        movel   %d0,0x84(%a0)                   /* set CSMR0 */
-
-        /*
-         *      Disable the PLL firstly. (Who knows what state it is
-         *      in here!).
-         */
-        movel   0x180(%a1),%d0                  /* get current PLL value */
-        andl    #0xfffffffe,%d0                 /* PLL bypass first */
-        movel   %d0,0x180(%a1)                  /* set PLL register */
-        nop
-
-#if CONFIG_CLOCK_FREQ == 140000000
-        /*
-         *      Set initial clock frequency. This assumes M5249C3 board
-         *      is fitted with 11.2896MHz crystal. It will program the
-         *      PLL for 140MHz. Lets go fast :-)
-         */
-        movel   #0x125a40f0,%d0                 /* set for 140MHz */
-        movel   %d0,0x180(%a1)                  /* set PLL register */
-        orl     #0x1,%d0
-        movel   %d0,0x180(%a1)                  /* set PLL register */
-#endif
-
-        /*
-         *      Setup CS1 for ethernet controller.
-         *      (Setup as per M5249C3 doco).
-         */
-        movel  #0xe0000000,%d0                  /* CS1 mapped at 0xe0000000 */
-        movel  %d0,0x8c(%a0)
-        movel  #0x001f0021,%d0                  /* CS1 size of 1Mb */
-        movel  %d0,0x90(%a0)
-        movew  #0x0080,%d0                      /* CS1 = 16bit port, AA */
-        movew  %d0,0x96(%a0)
-
-        /*
-         *      Setup CS2 for IDE interface.
-         */
-        movel   #0x50000000,%d0                 /* CS2 mapped at 0x50000000 */
-        movel   %d0,0x98(%a0)
-        movel   #0x001f0001,%d0                 /* CS2 size of 1MB */
-        movel   %d0,0x9c(%a0)
-        movew   #0x0080,%d0                     /* CS2 = 16bit, TA */
-        movew   %d0,0xa2(%a0)
-
-        movel   #0x00107000,%d0                 /* IDEconfig1 */
-        movel   %d0,0x18c(%a1)
-        movel   #0x000c0400,%d0                 /* IDEconfig2 */
-        movel   %d0,0x190(%a1)
-
-        movel   #0x00080000,%d0                 /* GPIO19, IDE reset bit */
-        orl     %d0,0xc(%a1)                    /* function GPIO19 */
-        orl     %d0,0x8(%a1)                    /* enable GPIO19 as output */
-        orl     %d0,0x4(%a1)                    /* de-assert IDE reset */
-.endm
-
-#define PLATFORM_SETUP  m5249c3_setup
-
-#endif /* __ASSEMBLER__ */
-
-/****************************************************************************/
-#endif  /* m5249sim_h */
diff --git a/arch/m68knommu/include/asm/m5272sim.h b/arch/m68knommu/include/asm/m5272sim.h
deleted file mode 100644
index 6217edc21139..000000000000
--- a/arch/m68knommu/include/asm/m5272sim.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m5272sim.h -- ColdFire 5272 System Integration Module support.
- *
- *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com) 
- */
-
-/****************************************************************************/
-#ifndef m5272sim_h
-#define m5272sim_h
-/****************************************************************************/
-
-
-/*
- *      Define the 5272 SIM register set addresses.
- */
-#define MCFSIM_SCR              0x04            /* SIM Config reg (r/w) */
-#define MCFSIM_SPR              0x06            /* System Protection reg (r/w)*/
-#define MCFSIM_PMR              0x08            /* Power Management reg (r/w) */
-#define MCFSIM_APMR             0x0e            /* Active Low Power reg (r/w) */
-#define MCFSIM_DIR              0x10            /* Device Identity reg (r/w) */
-
-#define MCFSIM_ICR1             0x20            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x24            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x28            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x2c            /* Intr Ctrl reg 4 (r/w) */
-
-#define MCFSIM_ISR              0x30            /* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR             0x34            /* Interrupt Transition (r/w) */
-#define MCFSIM_PIWR             0x38            /* Interrupt Wakeup reg (r/w) */
-#define MCFSIM_PIVR             0x3f            /* Interrupt Vector reg (r/w( */
-
-#define MCFSIM_WRRR             0x280           /* Watchdog reference (r/w) */
-#define MCFSIM_WIRR             0x284           /* Watchdog interrupt (r/w) */
-#define MCFSIM_WCR              0x288           /* Watchdog counter (r/w) */
-#define MCFSIM_WER              0x28c           /* Watchdog event (r/w) */
-
-#define MCFSIM_CSBR0            0x40            /* CS0 Base Address (r/w) */
-#define MCFSIM_CSOR0            0x44            /* CS0 Option (r/w) */
-#define MCFSIM_CSBR1            0x48            /* CS1 Base Address (r/w) */
-#define MCFSIM_CSOR1            0x4c            /* CS1 Option (r/w) */
-#define MCFSIM_CSBR2            0x50            /* CS2 Base Address (r/w) */
-#define MCFSIM_CSOR2            0x54            /* CS2 Option (r/w) */
-#define MCFSIM_CSBR3            0x58            /* CS3 Base Address (r/w) */
-#define MCFSIM_CSOR3            0x5c            /* CS3 Option (r/w) */
-#define MCFSIM_CSBR4            0x60            /* CS4 Base Address (r/w) */
-#define MCFSIM_CSOR4            0x64            /* CS4 Option (r/w) */
-#define MCFSIM_CSBR5            0x68            /* CS5 Base Address (r/w) */
-#define MCFSIM_CSOR5            0x6c            /* CS5 Option (r/w) */
-#define MCFSIM_CSBR6            0x70            /* CS6 Base Address (r/w) */
-#define MCFSIM_CSOR6            0x74            /* CS6 Option (r/w) */
-#define MCFSIM_CSBR7            0x78            /* CS7 Base Address (r/w) */
-#define MCFSIM_CSOR7            0x7c            /* CS7 Option (r/w) */
-
-#define MCFSIM_SDCR             0x180           /* SDRAM Configuration (r/w) */
-#define MCFSIM_SDTR             0x184           /* SDRAM Timing (r/w) */
-#define MCFSIM_DCAR0            0x4c            /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DCMR0            0x50            /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCCR0            0x57            /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DCAR1            0x58            /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DCMR1            0x5c            /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCCR1            0x63            /* DRAM 1 Control reg (r/w) */
-
-#define MCFSIM_PACNT            0x80            /* Port A Control (r/w) */
-#define MCFSIM_PADDR            0x84            /* Port A Direction (r/w) */
-#define MCFSIM_PADAT            0x86            /* Port A Data (r/w) */
-#define MCFSIM_PBCNT            0x88            /* Port B Control (r/w) */
-#define MCFSIM_PBDDR            0x8c            /* Port B Direction (r/w) */
-#define MCFSIM_PBDAT            0x8e            /* Port B Data (r/w) */
-#define MCFSIM_PCDDR            0x94            /* Port C Direction (r/w) */
-#define MCFSIM_PCDAT            0x96            /* Port C Data (r/w) */
-#define MCFSIM_PDCNT            0x98            /* Port D Control (r/w) */
-
-
-/****************************************************************************/
-#endif  /* m5272sim_h */
diff --git a/arch/m68knommu/include/asm/m527xsim.h b/arch/m68knommu/include/asm/m527xsim.h
deleted file mode 100644
index 1f63ab3fb3e6..000000000000
--- a/arch/m68knommu/include/asm/m527xsim.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
- *
- *      (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
- */
-
-/****************************************************************************/
-#ifndef m527xsim_h
-#define m527xsim_h
-/****************************************************************************/
-
-
-/*
- *      Define the 5270/5271 SIM register set addresses.
- */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 1 */
-#define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
-#define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
-#define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
-#define MCFINTC_IMRL            0x0c            /* Interrupt mask 1-31 */
-#define MCFINTC_INTFRCH         0x10            /* Interrupt force 32-63 */
-#define MCFINTC_INTFRCL         0x14            /* Interrupt force 1-31 */
-#define MCFINTC_IRLR            0x18            /* */
-#define MCFINTC_IACKL           0x19            /* */
-#define MCFINTC_ICR0            0x40            /* Base ICR register */
-
-#define MCFINT_VECBASE          64              /* Vector base number */
-#define MCFINT_UART0            13              /* Interrupt number for UART0 */
-#define MCFINT_UART1            14              /* Interrupt number for UART1 */
-#define MCFINT_UART2            15              /* Interrupt number for UART2 */
-#define MCFINT_PIT1             36              /* Interrupt number for PIT1 */
-
-/*
- *      SDRAM configuration registers.
- */
-#ifdef CONFIG_M5271
-#define MCFSIM_DCR              0x40            /* SDRAM control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
-#endif
-#ifdef CONFIG_M5275
-#define MCFSIM_DMR              0x40            /* SDRAM mode */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
-#define MCFSIM_DCFG1            0x48            /* SDRAM configuration 1 */
-#define MCFSIM_DCFG2            0x4c            /* SDRAM configuration 2 */
-#define MCFSIM_DBAR0            0x50            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x54            /* SDRAM address mask 0 */
-#define MCFSIM_DBAR1            0x58            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x5c            /* SDRAM address mask 1 */
-#endif
-
-/*
- *      GPIO pins setups to enable the UARTs.
- */
-#ifdef CONFIG_M5271
-#define MCF_GPIO_PAR_UART       0x100048        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x0ff0
-#define UART2_ENABLE_MASK       0x3000
-#endif
-#ifdef CONFIG_M5275
-#define MCF_GPIO_PAR_UART       0x10007c        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x00f0
-#define UART2_ENABLE_MASK       0x3f00 
-#endif
-
-/****************************************************************************/
-#endif  /* m527xsim_h */
diff --git a/arch/m68knommu/include/asm/m528xsim.h b/arch/m68knommu/include/asm/m528xsim.h
deleted file mode 100644
index 28bf783a5d6d..000000000000
--- a/arch/m68knommu/include/asm/m528xsim.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
- *
- *      (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
- */
-
-/****************************************************************************/
-#ifndef m528xsim_h
-#define m528xsim_h
-/****************************************************************************/
-
-
-/*
- *      Define the 5280/5282 SIM register set addresses.
- */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 0 */
-#define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
-#define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
-#define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
-#define MCFINTC_IMRL            0x0c            /* Interrupt mask 1-31 */
-#define MCFINTC_INTFRCH         0x10            /* Interrupt force 32-63 */
-#define MCFINTC_INTFRCL         0x14            /* Interrupt force 1-31 */
-#define MCFINTC_IRLR            0x18            /* */
-#define MCFINTC_IACKL           0x19            /* */
-#define MCFINTC_ICR0            0x40            /* Base ICR register */
-
-#define MCFINT_VECBASE          64              /* Vector base number */
-#define MCFINT_UART0            13              /* Interrupt number for UART0 */
-#define MCFINT_PIT1             55              /* Interrupt number for PIT1 */
-
-/*
- *      SDRAM configuration registers.
- */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
-
-/*
- *      Derek Cheung - 6 Feb 2005
- *              add I2C and QSPI register definition using Freescale's MCF5282
- */
-/* set Port AS pin for I2C or UART */
-#define MCF5282_GPIO_PASPAR     (volatile u16 *) (MCF_IPSBAR + 0x00100056)
-
-/* Port UA Pin Assignment Register (8 Bit) */
-#define MCF5282_GPIO_PUAPAR     0x10005C
-
-/* Interrupt Mask Register Register Low */ 
-#define MCF5282_INTC0_IMRL      (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
-/* Interrupt Control Register 7 */
-#define MCF5282_INTC0_ICR17     (volatile u8 *) (MCF_IPSBAR + 0x0C51)
-
-
-
-/*********************************************************************
-*
-* Inter-IC (I2C) Module
-*
-*********************************************************************/
-/* Read/Write access macros for general use */
-#define MCF5282_I2C_I2ADR       (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address 
-#define MCF5282_I2C_I2FDR       (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
-#define MCF5282_I2C_I2CR        (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
-#define MCF5282_I2C_I2SR        (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
-#define MCF5282_I2C_I2DR        (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF5282_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF5282_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF5282_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF5282_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF5282_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF5282_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF5282_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF5282_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF5282_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF5282_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF5282_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF5282_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF5282_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF5282_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF5282_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-
-
-/*********************************************************************
-*
-* Queued Serial Peripheral Interface (QSPI) Module
-*
-*********************************************************************/
-/* Derek - 21 Feb 2005 */
-/* change to the format used in I2C */
-/* Read/Write access macros for general use */
-#define MCF5282_QSPI_QMR        MCF_IPSBAR + 0x0340
-#define MCF5282_QSPI_QDLYR      MCF_IPSBAR + 0x0344
-#define MCF5282_QSPI_QWR        MCF_IPSBAR + 0x0348
-#define MCF5282_QSPI_QIR        MCF_IPSBAR + 0x034C
-#define MCF5282_QSPI_QAR        MCF_IPSBAR + 0x0350
-#define MCF5282_QSPI_QDR        MCF_IPSBAR + 0x0354
-#define MCF5282_QSPI_QCR        MCF_IPSBAR + 0x0354
-
-/* Bit level definitions and macros */
-#define MCF5282_QSPI_QMR_MSTR                           (0x8000)
-#define MCF5282_QSPI_QMR_DOHIE                          (0x4000)
-#define MCF5282_QSPI_QMR_BITS_16                        (0x0000)
-#define MCF5282_QSPI_QMR_BITS_8                         (0x2000)
-#define MCF5282_QSPI_QMR_BITS_9                         (0x2400)
-#define MCF5282_QSPI_QMR_BITS_10                        (0x2800)
-#define MCF5282_QSPI_QMR_BITS_11                        (0x2C00)
-#define MCF5282_QSPI_QMR_BITS_12                        (0x3000)
-#define MCF5282_QSPI_QMR_BITS_13                        (0x3400)
-#define MCF5282_QSPI_QMR_BITS_14                        (0x3800)
-#define MCF5282_QSPI_QMR_BITS_15                        (0x3C00)
-#define MCF5282_QSPI_QMR_CPOL                           (0x0200)
-#define MCF5282_QSPI_QMR_CPHA                           (0x0100)
-#define MCF5282_QSPI_QMR_BAUD(x)                        (((x)&0x00FF))
-
-#define MCF5282_QSPI_QDLYR_SPE                          (0x80)
-#define MCF5282_QSPI_QDLYR_QCD(x)                       (((x)&0x007F)<<8)
-#define MCF5282_QSPI_QDLYR_DTL(x)                       (((x)&0x00FF))
-
-#define MCF5282_QSPI_QWR_HALT                           (0x8000)
-#define MCF5282_QSPI_QWR_WREN                           (0x4000)
-#define MCF5282_QSPI_QWR_WRTO                           (0x2000)
-#define MCF5282_QSPI_QWR_CSIV                           (0x1000)
-#define MCF5282_QSPI_QWR_ENDQP(x)                       (((x)&0x000F)<<8)
-#define MCF5282_QSPI_QWR_CPTQP(x)                       (((x)&0x000F)<<4)
-#define MCF5282_QSPI_QWR_NEWQP(x)                       (((x)&0x000F))
-
-#define MCF5282_QSPI_QIR_WCEFB                          (0x8000)
-#define MCF5282_QSPI_QIR_ABRTB                          (0x4000)
-#define MCF5282_QSPI_QIR_ABRTL                          (0x1000)
-#define MCF5282_QSPI_QIR_WCEFE                          (0x0800)
-#define MCF5282_QSPI_QIR_ABRTE                          (0x0400)
-#define MCF5282_QSPI_QIR_SPIFE                          (0x0100)
-#define MCF5282_QSPI_QIR_WCEF                           (0x0008)
-#define MCF5282_QSPI_QIR_ABRT                           (0x0004)
-#define MCF5282_QSPI_QIR_SPIF                           (0x0001)
-
-#define MCF5282_QSPI_QAR_ADDR(x)                        (((x)&0x003F))
-
-#define MCF5282_QSPI_QDR_COMMAND(x)                     (((x)&0xFF00))
-#define MCF5282_QSPI_QCR_DATA(x)                        (((x)&0x00FF)<<8)
-#define MCF5282_QSPI_QCR_CONT                           (0x8000)
-#define MCF5282_QSPI_QCR_BITSE                          (0x4000)
-#define MCF5282_QSPI_QCR_DT                             (0x2000)
-#define MCF5282_QSPI_QCR_DSCK                           (0x1000)
-#define MCF5282_QSPI_QCR_CS                             (((x)&0x000F)<<8)
-
-/****************************************************************************/
-#endif  /* m528xsim_h */
diff --git a/arch/m68knommu/include/asm/m5307sim.h b/arch/m68knommu/include/asm/m5307sim.h
deleted file mode 100644
index 5886728409c0..000000000000
--- a/arch/m68knommu/include/asm/m5307sim.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m5307sim.h -- ColdFire 5307 System Integration Module support.
- *
- *      (C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
- *      (C) Copyright 1999,  Lineo (www.lineo.com)
- *
- *      Modified by David W. Miller for the MCF5307 Eval Board.
- */
-
-/****************************************************************************/
-#ifndef m5307sim_h
-#define m5307sim_h
-/****************************************************************************/
-
-/*
- *      Define the 5307 SIM register set addresses.
- */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Controll Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-
-#ifdef CONFIG_OLDMASK
-#define MCFSIM_CSBAR            0x98            /* CS Base Address reg (r/w) */
-#define MCFSIM_CSBAMR           0x9c            /* CS Base Mask reg (r/w) */
-#define MCFSIM_CSMR2            0x9e            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSMR3            0xaa            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSMR4            0xb6            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSMR5            0xc2            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSMR6            0xce            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSMR7            0xda            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
-#else
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
-#endif /* CONFIG_OLDMASK */
-
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
-
-#define MCFSIM_PADDR            0x244           /* Parallel Direction (r/w) */
-#define MCFSIM_PADAT            0x248           /* Parallel Data (r/w) */
-
-
-/* Definition offset address for CS2-7  -- old mask 5307 */
-
-#define MCF5307_CS2             (0x400000)
-#define MCF5307_CS3             (0x600000)
-#define MCF5307_CS4             (0x800000)
-#define MCF5307_CS5             (0xA00000)
-#define MCF5307_CS6             (0xC00000)
-#define MCF5307_CS7             (0xE00000)
-
-
-/*
- *      Some symbol defines for the above...
- */
-#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
-#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
-#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
-#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
-#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
-#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
-#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
-#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
-#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
-
-#if defined(CONFIG_M5307)
-#define MCFSIM_IMR_MASKALL      0x3fffe         /* All SIM intr sources */
-#endif
-
-/*
- *      Macro to set IMR register. It is 32 bits on the 5307.
- */
-#define mcf_getimr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
-
-#define mcf_setimr(imr)         \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
-
-#define mcf_getipr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
-
-
-/*
- *      Some symbol defines for the Parallel Port Pin Assignment Register
- */
-#define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
-                                                /* Clear to select par I/O */
-#define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
-                                                /* Clear to select par I/O */
-
-/*
- *       Defines for the IRQPAR Register
- */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
-
-
-/*
- *      Define the Cache register flags.
- */
-#define CACR_EC                 (1<<31)
-#define CACR_ESB                (1<<29)
-#define CACR_DPI                (1<<28)
-#define CACR_HLCK               (1<<27)
-#define CACR_CINVA              (1<<24)
-#define CACR_DNFB               (1<<10)
-#define CACR_DCM_WTHRU          (0<<8)
-#define CACR_DCM_WBACK          (1<<8)
-#define CACR_DCM_OFF_PRE        (2<<8)
-#define CACR_DCM_OFF_IMP        (3<<8)
-#define CACR_DW                 (1<<5)
-
-#define ACR_BASE_POS            24
-#define ACR_MASK_POS            16
-#define ACR_ENABLE              (1<<15)
-#define ACR_USER                (0<<13)
-#define ACR_SUPER               (1<<13)
-#define ACR_ANY                 (2<<13)
-#define ACR_CM_WTHRU            (0<<5)
-#define ACR_CM_WBACK            (1<<5)
-#define ACR_CM_OFF_PRE          (2<<5)
-#define ACR_CM_OFF_IMP          (3<<5)
-#define ACR_WPROTECT            (1<<2)
-
-/****************************************************************************/
-#endif  /* m5307sim_h */
diff --git a/arch/m68knommu/include/asm/m532xsim.h b/arch/m68knommu/include/asm/m532xsim.h
deleted file mode 100644
index 1835fd20a82c..000000000000
--- a/arch/m68knommu/include/asm/m532xsim.h
+++ /dev/null
@@ -1,2238 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m532xsim.h -- ColdFire 5329 registers
- */
-
-/****************************************************************************/
-#ifndef m532xsim_h
-#define m532xsim_h
-/****************************************************************************/
-
-#define MCF_REG32(x) (*(volatile unsigned long  *)(x))
-#define MCF_REG16(x) (*(volatile unsigned short *)(x))
-#define MCF_REG08(x) (*(volatile unsigned char  *)(x))
-
-#define MCFINT_VECBASE      64
-#define MCFINT_UART0        26          /* Interrupt number for UART0 */
-#define MCFINT_UART1        27          /* Interrupt number for UART1 */
-
-#define MCF_WTM_WCR     MCF_REG16(0xFC098000)
-
-/*
- *      Define the 532x SIM register set addresses.
- */
-#define MCFSIM_IPRL             0xFC048004
-#define MCFSIM_IPRH             0xFC048000
-#define MCFSIM_IPR              MCFSIM_IPRL
-#define MCFSIM_IMRL             0xFC04800C
-#define MCFSIM_IMRH             0xFC048008
-#define MCFSIM_IMR              MCFSIM_IMRL
-#define MCFSIM_ICR0             0xFC048040      
-#define MCFSIM_ICR1             0xFC048041      
-#define MCFSIM_ICR2             0xFC048042      
-#define MCFSIM_ICR3             0xFC048043      
-#define MCFSIM_ICR4             0xFC048044      
-#define MCFSIM_ICR5             0xFC048045      
-#define MCFSIM_ICR6             0xFC048046      
-#define MCFSIM_ICR7             0xFC048047      
-#define MCFSIM_ICR8             0xFC048048      
-#define MCFSIM_ICR9             0xFC048049      
-#define MCFSIM_ICR10            0xFC04804A
-#define MCFSIM_ICR11            0xFC04804B
-
-/*
- *      Some symbol defines for the above...
- */
-#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
-#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
-#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
-#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
-#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
-#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
-#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
-#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
-#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
-
-
-#define MCFSIM_IMR_MASKALL      0xFFFFFFFF      /* All SIM intr sources */
-
-#define MCFSIM_IMR_SIMR0        0xFC04801C
-#define MCFSIM_IMR_SIMR1        0xFC04C01C
-#define MCFSIM_IMR_CIMR0        0xFC04801D
-#define MCFSIM_IMR_CIMR1        0xFC04C01D
-
-#define MCFSIM_ICR_TIMER1       (0xFC048040+32)
-#define MCFSIM_ICR_TIMER2       (0xFC048040+33)
-
-
-/*
- *      Macro to set IMR register. It is 32 bits on the 5307.
- */
-#define mcf_getimr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
-
-#define mcf_setimr(imr)         \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
-
-#define mcf_getipr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
-
-#define mcf_getiprl()           \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL))
-
-#define mcf_getiprh()           \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH))
-
-
-#define mcf_enable_irq0(irq)            \
-        *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq);
-
-#define mcf_enable_irq1(irq)            \
-        *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq);
-
-#define mcf_disable_irq0(irq)           \
-        *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq);
-
-#define mcf_disable_irq1(irq)           \
-        *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq);
-
-/*
- *      Define the Cache register flags.
- */
-#define CACR_EC                 (1<<31)
-#define CACR_ESB                (1<<29)
-#define CACR_DPI                (1<<28)
-#define CACR_HLCK               (1<<27)
-#define CACR_CINVA              (1<<24)
-#define CACR_DNFB               (1<<10)
-#define CACR_DCM_WTHRU          (0<<8)
-#define CACR_DCM_WBACK          (1<<8)
-#define CACR_DCM_OFF_PRE        (2<<8)
-#define CACR_DCM_OFF_IMP        (3<<8)
-#define CACR_DW                 (1<<5)
-
-#define ACR_BASE_POS            24
-#define ACR_MASK_POS            16
-#define ACR_ENABLE              (1<<15)
-#define ACR_USER                (0<<13)
-#define ACR_SUPER               (1<<13)
-#define ACR_ANY                 (2<<13)
-#define ACR_CM_WTHRU            (0<<5)
-#define ACR_CM_WBACK            (1<<5)
-#define ACR_CM_OFF_PRE          (2<<5)
-#define ACR_CM_OFF_IMP          (3<<5)
-#define ACR_WPROTECT            (1<<2)
-
-/*********************************************************************
- *
- * Inter-IC (I2C) Module
- *
- *********************************************************************/
-
-/* Read/Write access macros for general use */
-#define MCF532x_I2C_I2ADR       (volatile u8 *) (0xFC058000) // Address 
-#define MCF532x_I2C_I2FDR       (volatile u8 *) (0xFC058004) // Freq Divider
-#define MCF532x_I2C_I2CR        (volatile u8 *) (0xFC058008) // Control
-#define MCF532x_I2C_I2SR        (volatile u8 *) (0xFC05800C) // Status
-#define MCF532x_I2C_I2DR        (volatile u8 *) (0xFC058010) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF532x_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF532x_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF532x_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF532x_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF532x_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF532x_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF532x_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF532x_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF532x_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF532x_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF532x_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF532x_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF532x_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF532x_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF532x_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-#define MCF532x_PAR_FECI2C      (volatile u8 *) (0xFC0A4053)
-
-
-/*
- *      The M5329EVB board needs a help getting its devices initialized 
- *      at kernel start time if dBUG doesn't set it up (for example 
- *      it is not used), so we need to do it manually.
- */
-#ifdef __ASSEMBLER__
-.macro m5329EVB_setup
-        movel   #0xFC098000, %a7
-        movel   #0x0, (%a7)
-#define CORE_SRAM       0x80000000      
-#define CORE_SRAM_SIZE  0x8000
-        movel   #CORE_SRAM, %d0
-        addl    #0x221, %d0
-        movec   %d0,%RAMBAR1
-        movel   #CORE_SRAM, %sp
-        addl    #CORE_SRAM_SIZE, %sp
-        jsr     sysinit
-.endm
-#define PLATFORM_SETUP  m5329EVB_setup
-
-#endif /* __ASSEMBLER__ */
-
-/*********************************************************************
- *
- * Chip Configuration Module (CCM)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_CCM_CCR               MCF_REG16(0xFC0A0004)
-#define MCF_CCM_RCON              MCF_REG16(0xFC0A0008)
-#define MCF_CCM_CIR               MCF_REG16(0xFC0A000A)
-#define MCF_CCM_MISCCR            MCF_REG16(0xFC0A0010)
-#define MCF_CCM_CDR               MCF_REG16(0xFC0A0012)
-#define MCF_CCM_UHCSR             MCF_REG16(0xFC0A0014)
-#define MCF_CCM_UOCSR             MCF_REG16(0xFC0A0016)
-
-/* Bit definitions and macros for MCF_CCM_CCR */
-#define MCF_CCM_CCR_RESERVED      (0x0001)
-#define MCF_CCM_CCR_PLL_MODE      (0x0003)
-#define MCF_CCM_CCR_OSC_MODE      (0x0005)
-#define MCF_CCM_CCR_BOOTPS(x)     (((x)&0x0003)<<3|0x0001)
-#define MCF_CCM_CCR_LOAD          (0x0021)
-#define MCF_CCM_CCR_LIMP          (0x0041)
-#define MCF_CCM_CCR_CSC(x)        (((x)&0x0003)<<8|0x0001)
-
-/* Bit definitions and macros for MCF_CCM_RCON */
-#define MCF_CCM_RCON_RESERVED     (0x0001)
-#define MCF_CCM_RCON_PLL_MODE     (0x0003)
-#define MCF_CCM_RCON_OSC_MODE     (0x0005)
-#define MCF_CCM_RCON_BOOTPS(x)    (((x)&0x0003)<<3|0x0001)
-#define MCF_CCM_RCON_LOAD         (0x0021)
-#define MCF_CCM_RCON_LIMP         (0x0041)
-#define MCF_CCM_RCON_CSC(x)       (((x)&0x0003)<<8|0x0001)
-
-/* Bit definitions and macros for MCF_CCM_CIR */
-#define MCF_CCM_CIR_PRN(x)        (((x)&0x003F)<<0)
-#define MCF_CCM_CIR_PIN(x)        (((x)&0x03FF)<<6)
-
-/* Bit definitions and macros for MCF_CCM_MISCCR */
-#define MCF_CCM_MISCCR_USBSRC     (0x0001)
-#define MCF_CCM_MISCCR_USBDIV     (0x0002)
-#define MCF_CCM_MISCCR_SSI_SRC    (0x0010)
-#define MCF_CCM_MISCCR_TIM_DMA   (0x0020)
-#define MCF_CCM_MISCCR_SSI_PUS    (0x0040)
-#define MCF_CCM_MISCCR_SSI_PUE    (0x0080)
-#define MCF_CCM_MISCCR_LCD_CHEN   (0x0100)
-#define MCF_CCM_MISCCR_LIMP       (0x1000)
-#define MCF_CCM_MISCCR_PLL_LOCK   (0x2000)
-
-/* Bit definitions and macros for MCF_CCM_CDR */
-#define MCF_CCM_CDR_SSIDIV(x)     (((x)&0x000F)<<0)
-#define MCF_CCM_CDR_LPDIV(x)      (((x)&0x000F)<<8)
-
-/* Bit definitions and macros for MCF_CCM_UHCSR */
-#define MCF_CCM_UHCSR_XPDE        (0x0001)
-#define MCF_CCM_UHCSR_UHMIE       (0x0002)
-#define MCF_CCM_UHCSR_WKUP        (0x0004)
-#define MCF_CCM_UHCSR_PORTIND(x)  (((x)&0x0003)<<14)
-
-/* Bit definitions and macros for MCF_CCM_UOCSR */
-#define MCF_CCM_UOCSR_XPDE        (0x0001)
-#define MCF_CCM_UOCSR_UOMIE       (0x0002)
-#define MCF_CCM_UOCSR_WKUP        (0x0004)
-#define MCF_CCM_UOCSR_PWRFLT      (0x0008)
-#define MCF_CCM_UOCSR_SEND        (0x0010)
-#define MCF_CCM_UOCSR_VVLD        (0x0020)
-#define MCF_CCM_UOCSR_BVLD        (0x0040)
-#define MCF_CCM_UOCSR_AVLD        (0x0080)
-#define MCF_CCM_UOCSR_DPPU        (0x0100)
-#define MCF_CCM_UOCSR_DCR_VBUS    (0x0200)
-#define MCF_CCM_UOCSR_CRG_VBUS    (0x0400)
-#define MCF_CCM_UOCSR_DRV_VBUS    (0x0800)
-#define MCF_CCM_UOCSR_DMPD        (0x1000)
-#define MCF_CCM_UOCSR_DPPD        (0x2000)
-#define MCF_CCM_UOCSR_PORTIND(x)  (((x)&0x0003)<<14)
-
-/*********************************************************************
- *
- * DMA Timers (DTIM)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_DTIM0_DTMR           MCF_REG16(0xFC070000)
-#define MCF_DTIM0_DTXMR          MCF_REG08(0xFC070002)
-#define MCF_DTIM0_DTER           MCF_REG08(0xFC070003)
-#define MCF_DTIM0_DTRR           MCF_REG32(0xFC070004)
-#define MCF_DTIM0_DTCR           MCF_REG32(0xFC070008)
-#define MCF_DTIM0_DTCN           MCF_REG32(0xFC07000C)
-#define MCF_DTIM1_DTMR           MCF_REG16(0xFC074000)
-#define MCF_DTIM1_DTXMR          MCF_REG08(0xFC074002)
-#define MCF_DTIM1_DTER           MCF_REG08(0xFC074003)
-#define MCF_DTIM1_DTRR           MCF_REG32(0xFC074004)
-#define MCF_DTIM1_DTCR           MCF_REG32(0xFC074008)
-#define MCF_DTIM1_DTCN           MCF_REG32(0xFC07400C)
-#define MCF_DTIM2_DTMR           MCF_REG16(0xFC078000)
-#define MCF_DTIM2_DTXMR          MCF_REG08(0xFC078002)
-#define MCF_DTIM2_DTER           MCF_REG08(0xFC078003)
-#define MCF_DTIM2_DTRR           MCF_REG32(0xFC078004)
-#define MCF_DTIM2_DTCR           MCF_REG32(0xFC078008)
-#define MCF_DTIM2_DTCN           MCF_REG32(0xFC07800C)
-#define MCF_DTIM3_DTMR           MCF_REG16(0xFC07C000)
-#define MCF_DTIM3_DTXMR          MCF_REG08(0xFC07C002)
-#define MCF_DTIM3_DTER           MCF_REG08(0xFC07C003)
-#define MCF_DTIM3_DTRR           MCF_REG32(0xFC07C004)
-#define MCF_DTIM3_DTCR           MCF_REG32(0xFC07C008)
-#define MCF_DTIM3_DTCN           MCF_REG32(0xFC07C00C)
-#define MCF_DTIM_DTMR(x)         MCF_REG16(0xFC070000+((x)*0x4000))
-#define MCF_DTIM_DTXMR(x)        MCF_REG08(0xFC070002+((x)*0x4000))
-#define MCF_DTIM_DTER(x)         MCF_REG08(0xFC070003+((x)*0x4000))
-#define MCF_DTIM_DTRR(x)         MCF_REG32(0xFC070004+((x)*0x4000))
-#define MCF_DTIM_DTCR(x)         MCF_REG32(0xFC070008+((x)*0x4000))
-#define MCF_DTIM_DTCN(x)         MCF_REG32(0xFC07000C+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_DTIM_DTMR */
-#define MCF_DTIM_DTMR_RST        (0x0001)
-#define MCF_DTIM_DTMR_CLK(x)     (((x)&0x0003)<<1)
-#define MCF_DTIM_DTMR_FRR        (0x0008)
-#define MCF_DTIM_DTMR_ORRI       (0x0010)
-#define MCF_DTIM_DTMR_OM         (0x0020)
-#define MCF_DTIM_DTMR_CE(x)      (((x)&0x0003)<<6)
-#define MCF_DTIM_DTMR_PS(x)      (((x)&0x00FF)<<8)
-#define MCF_DTIM_DTMR_CE_ANY     (0x00C0)
-#define MCF_DTIM_DTMR_CE_FALL    (0x0080)
-#define MCF_DTIM_DTMR_CE_RISE    (0x0040)
-#define MCF_DTIM_DTMR_CE_NONE    (0x0000)
-#define MCF_DTIM_DTMR_CLK_DTIN   (0x0006)
-#define MCF_DTIM_DTMR_CLK_DIV16  (0x0004)
-#define MCF_DTIM_DTMR_CLK_DIV1   (0x0002)
-#define MCF_DTIM_DTMR_CLK_STOP   (0x0000)
-
-/* Bit definitions and macros for MCF_DTIM_DTXMR */
-#define MCF_DTIM_DTXMR_MODE16    (0x01)
-#define MCF_DTIM_DTXMR_DMAEN     (0x80)
-
-/* Bit definitions and macros for MCF_DTIM_DTER */
-#define MCF_DTIM_DTER_CAP        (0x01)
-#define MCF_DTIM_DTER_REF        (0x02)
-
-/* Bit definitions and macros for MCF_DTIM_DTRR */
-#define MCF_DTIM_DTRR_REF(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCR */
-#define MCF_DTIM_DTCR_CAP(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCN */
-#define MCF_DTIM_DTCN_CNT(x)     (((x)&0xFFFFFFFF)<<0)
-
-/*********************************************************************
- *
- * FlexBus Chip Selects (FBCS)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_FBCS0_CSAR          MCF_REG32(0xFC008000)
-#define MCF_FBCS0_CSMR          MCF_REG32(0xFC008004)
-#define MCF_FBCS0_CSCR          MCF_REG32(0xFC008008)
-#define MCF_FBCS1_CSAR          MCF_REG32(0xFC00800C)
-#define MCF_FBCS1_CSMR          MCF_REG32(0xFC008010)
-#define MCF_FBCS1_CSCR          MCF_REG32(0xFC008014)
-#define MCF_FBCS2_CSAR          MCF_REG32(0xFC008018)
-#define MCF_FBCS2_CSMR          MCF_REG32(0xFC00801C)
-#define MCF_FBCS2_CSCR          MCF_REG32(0xFC008020)
-#define MCF_FBCS3_CSAR          MCF_REG32(0xFC008024)
-#define MCF_FBCS3_CSMR          MCF_REG32(0xFC008028)
-#define MCF_FBCS3_CSCR          MCF_REG32(0xFC00802C)
-#define MCF_FBCS4_CSAR          MCF_REG32(0xFC008030)
-#define MCF_FBCS4_CSMR          MCF_REG32(0xFC008034)
-#define MCF_FBCS4_CSCR          MCF_REG32(0xFC008038)
-#define MCF_FBCS5_CSAR          MCF_REG32(0xFC00803C)
-#define MCF_FBCS5_CSMR          MCF_REG32(0xFC008040)
-#define MCF_FBCS5_CSCR          MCF_REG32(0xFC008044)
-#define MCF_FBCS_CSAR(x)        MCF_REG32(0xFC008000+((x)*0x00C))
-#define MCF_FBCS_CSMR(x)        MCF_REG32(0xFC008004+((x)*0x00C))
-#define MCF_FBCS_CSCR(x)        MCF_REG32(0xFC008008+((x)*0x00C))
-
-/* Bit definitions and macros for MCF_FBCS_CSAR */
-#define MCF_FBCS_CSAR_BA(x)     ((x)&0xFFFF0000)
-
-/* Bit definitions and macros for MCF_FBCS_CSMR */
-#define MCF_FBCS_CSMR_V         (0x00000001)
-#define MCF_FBCS_CSMR_WP        (0x00000100)
-#define MCF_FBCS_CSMR_BAM(x)    (((x)&0x0000FFFF)<<16)
-#define MCF_FBCS_CSMR_BAM_4G    (0xFFFF0000)
-#define MCF_FBCS_CSMR_BAM_2G    (0x7FFF0000)
-#define MCF_FBCS_CSMR_BAM_1G    (0x3FFF0000)
-#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
-#define MCF_FBCS_CSMR_BAM_512M  (0x1FFF0000)
-#define MCF_FBCS_CSMR_BAM_256M  (0x0FFF0000)
-#define MCF_FBCS_CSMR_BAM_128M  (0x07FF0000)
-#define MCF_FBCS_CSMR_BAM_64M   (0x03FF0000)
-#define MCF_FBCS_CSMR_BAM_32M   (0x01FF0000)
-#define MCF_FBCS_CSMR_BAM_16M   (0x00FF0000)
-#define MCF_FBCS_CSMR_BAM_8M    (0x007F0000)
-#define MCF_FBCS_CSMR_BAM_4M    (0x003F0000)
-#define MCF_FBCS_CSMR_BAM_2M    (0x001F0000)
-#define MCF_FBCS_CSMR_BAM_1M    (0x000F0000)
-#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
-#define MCF_FBCS_CSMR_BAM_512K  (0x00070000)
-#define MCF_FBCS_CSMR_BAM_256K  (0x00030000)
-#define MCF_FBCS_CSMR_BAM_128K  (0x00010000)
-#define MCF_FBCS_CSMR_BAM_64K   (0x00000000)
-
-/* Bit definitions and macros for MCF_FBCS_CSCR */
-#define MCF_FBCS_CSCR_BSTW      (0x00000008)
-#define MCF_FBCS_CSCR_BSTR      (0x00000010)
-#define MCF_FBCS_CSCR_BEM       (0x00000020)
-#define MCF_FBCS_CSCR_PS(x)     (((x)&0x00000003)<<6)
-#define MCF_FBCS_CSCR_AA        (0x00000100)
-#define MCF_FBCS_CSCR_SBM       (0x00000200)
-#define MCF_FBCS_CSCR_WS(x)     (((x)&0x0000003F)<<10)
-#define MCF_FBCS_CSCR_WRAH(x)   (((x)&0x00000003)<<16)
-#define MCF_FBCS_CSCR_RDAH(x)   (((x)&0x00000003)<<18)
-#define MCF_FBCS_CSCR_ASET(x)   (((x)&0x00000003)<<20)
-#define MCF_FBCS_CSCR_SWSEN     (0x00800000)
-#define MCF_FBCS_CSCR_SWS(x)    (((x)&0x0000003F)<<26)
-#define MCF_FBCS_CSCR_PS_8      (0x0040)
-#define MCF_FBCS_CSCR_PS_16     (0x0080)
-#define MCF_FBCS_CSCR_PS_32     (0x0000)
-
-/*********************************************************************
- *
- * General Purpose I/O (GPIO)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_GPIO_PODR_FECH              MCF_REG08(0xFC0A4000)
-#define MCF_GPIO_PODR_FECL              MCF_REG08(0xFC0A4001)
-#define MCF_GPIO_PODR_SSI               MCF_REG08(0xFC0A4002)
-#define MCF_GPIO_PODR_BUSCTL            MCF_REG08(0xFC0A4003)
-#define MCF_GPIO_PODR_BE                MCF_REG08(0xFC0A4004)
-#define MCF_GPIO_PODR_CS                MCF_REG08(0xFC0A4005)
-#define MCF_GPIO_PODR_PWM               MCF_REG08(0xFC0A4006)
-#define MCF_GPIO_PODR_FECI2C            MCF_REG08(0xFC0A4007)
-#define MCF_GPIO_PODR_UART              MCF_REG08(0xFC0A4009)
-#define MCF_GPIO_PODR_QSPI              MCF_REG08(0xFC0A400A)
-#define MCF_GPIO_PODR_TIMER             MCF_REG08(0xFC0A400B)
-#define MCF_GPIO_PODR_LCDDATAH          MCF_REG08(0xFC0A400D)
-#define MCF_GPIO_PODR_LCDDATAM          MCF_REG08(0xFC0A400E)
-#define MCF_GPIO_PODR_LCDDATAL          MCF_REG08(0xFC0A400F)
-#define MCF_GPIO_PODR_LCDCTLH           MCF_REG08(0xFC0A4010)
-#define MCF_GPIO_PODR_LCDCTLL           MCF_REG08(0xFC0A4011)
-#define MCF_GPIO_PDDR_FECH              MCF_REG08(0xFC0A4014)
-#define MCF_GPIO_PDDR_FECL              MCF_REG08(0xFC0A4015)
-#define MCF_GPIO_PDDR_SSI               MCF_REG08(0xFC0A4016)
-#define MCF_GPIO_PDDR_BUSCTL            MCF_REG08(0xFC0A4017)
-#define MCF_GPIO_PDDR_BE                MCF_REG08(0xFC0A4018)
-#define MCF_GPIO_PDDR_CS                MCF_REG08(0xFC0A4019)
-#define MCF_GPIO_PDDR_PWM               MCF_REG08(0xFC0A401A)
-#define MCF_GPIO_PDDR_FECI2C            MCF_REG08(0xFC0A401B)
-#define MCF_GPIO_PDDR_UART              MCF_REG08(0xFC0A401C)
-#define MCF_GPIO_PDDR_QSPI              MCF_REG08(0xFC0A401E)
-#define MCF_GPIO_PDDR_TIMER             MCF_REG08(0xFC0A401F)
-#define MCF_GPIO_PDDR_LCDDATAH          MCF_REG08(0xFC0A4021)
-#define MCF_GPIO_PDDR_LCDDATAM          MCF_REG08(0xFC0A4022)
-#define MCF_GPIO_PDDR_LCDDATAL          MCF_REG08(0xFC0A4023)
-#define MCF_GPIO_PDDR_LCDCTLH           MCF_REG08(0xFC0A4024)
-#define MCF_GPIO_PDDR_LCDCTLL           MCF_REG08(0xFC0A4025)
-#define MCF_GPIO_PPDSDR_FECH            MCF_REG08(0xFC0A4028)
-#define MCF_GPIO_PPDSDR_FECL            MCF_REG08(0xFC0A4029)
-#define MCF_GPIO_PPDSDR_SSI             MCF_REG08(0xFC0A402A)
-#define MCF_GPIO_PPDSDR_BUSCTL          MCF_REG08(0xFC0A402B)
-#define MCF_GPIO_PPDSDR_BE              MCF_REG08(0xFC0A402C)
-#define MCF_GPIO_PPDSDR_CS              MCF_REG08(0xFC0A402D)
-#define MCF_GPIO_PPDSDR_PWM             MCF_REG08(0xFC0A402E)
-#define MCF_GPIO_PPDSDR_FECI2C          MCF_REG08(0xFC0A402F)
-#define MCF_GPIO_PPDSDR_UART            MCF_REG08(0xFC0A4031)
-#define MCF_GPIO_PPDSDR_QSPI            MCF_REG08(0xFC0A4032)
-#define MCF_GPIO_PPDSDR_TIMER           MCF_REG08(0xFC0A4033)
-#define MCF_GPIO_PPDSDR_LCDDATAH        MCF_REG08(0xFC0A4035)
-#define MCF_GPIO_PPDSDR_LCDDATAM        MCF_REG08(0xFC0A4036)
-#define MCF_GPIO_PPDSDR_LCDDATAL        MCF_REG08(0xFC0A4037)
-#define MCF_GPIO_PPDSDR_LCDCTLH         MCF_REG08(0xFC0A4038)
-#define MCF_GPIO_PPDSDR_LCDCTLL         MCF_REG08(0xFC0A4039)
-#define MCF_GPIO_PCLRR_FECH             MCF_REG08(0xFC0A403C)
-#define MCF_GPIO_PCLRR_FECL             MCF_REG08(0xFC0A403D)
-#define MCF_GPIO_PCLRR_SSI              MCF_REG08(0xFC0A403E)
-#define MCF_GPIO_PCLRR_BUSCTL           MCF_REG08(0xFC0A403F)
-#define MCF_GPIO_PCLRR_BE               MCF_REG08(0xFC0A4040)
-#define MCF_GPIO_PCLRR_CS               MCF_REG08(0xFC0A4041)
-#define MCF_GPIO_PCLRR_PWM              MCF_REG08(0xFC0A4042)
-#define MCF_GPIO_PCLRR_FECI2C           MCF_REG08(0xFC0A4043)
-#define MCF_GPIO_PCLRR_UART             MCF_REG08(0xFC0A4045)
-#define MCF_GPIO_PCLRR_QSPI             MCF_REG08(0xFC0A4046)
-#define MCF_GPIO_PCLRR_TIMER            MCF_REG08(0xFC0A4047)
-#define MCF_GPIO_PCLRR_LCDDATAH         MCF_REG08(0xFC0A4049)
-#define MCF_GPIO_PCLRR_LCDDATAM         MCF_REG08(0xFC0A404A)
-#define MCF_GPIO_PCLRR_LCDDATAL         MCF_REG08(0xFC0A404B)
-#define MCF_GPIO_PCLRR_LCDCTLH          MCF_REG08(0xFC0A404C)
-#define MCF_GPIO_PCLRR_LCDCTLL          MCF_REG08(0xFC0A404D)
-#define MCF_GPIO_PAR_FEC                MCF_REG08(0xFC0A4050)
-#define MCF_GPIO_PAR_PWM                MCF_REG08(0xFC0A4051)
-#define MCF_GPIO_PAR_BUSCTL             MCF_REG08(0xFC0A4052)
-#define MCF_GPIO_PAR_FECI2C             MCF_REG08(0xFC0A4053)
-#define MCF_GPIO_PAR_BE                 MCF_REG08(0xFC0A4054)
-#define MCF_GPIO_PAR_CS                 MCF_REG08(0xFC0A4055)
-#define MCF_GPIO_PAR_SSI                MCF_REG16(0xFC0A4056)
-#define MCF_GPIO_PAR_UART               MCF_REG16(0xFC0A4058)
-#define MCF_GPIO_PAR_QSPI               MCF_REG16(0xFC0A405A)
-#define MCF_GPIO_PAR_TIMER              MCF_REG08(0xFC0A405C)
-#define MCF_GPIO_PAR_LCDDATA            MCF_REG08(0xFC0A405D)
-#define MCF_GPIO_PAR_LCDCTL             MCF_REG16(0xFC0A405E)
-#define MCF_GPIO_PAR_IRQ                MCF_REG16(0xFC0A4060)
-#define MCF_GPIO_MSCR_FLEXBUS           MCF_REG08(0xFC0A4064)
-#define MCF_GPIO_MSCR_SDRAM             MCF_REG08(0xFC0A4065)
-#define MCF_GPIO_DSCR_I2C               MCF_REG08(0xFC0A4068)
-#define MCF_GPIO_DSCR_PWM               MCF_REG08(0xFC0A4069)
-#define MCF_GPIO_DSCR_FEC               MCF_REG08(0xFC0A406A)
-#define MCF_GPIO_DSCR_UART              MCF_REG08(0xFC0A406B)
-#define MCF_GPIO_DSCR_QSPI              MCF_REG08(0xFC0A406C)
-#define MCF_GPIO_DSCR_TIMER             MCF_REG08(0xFC0A406D)
-#define MCF_GPIO_DSCR_SSI               MCF_REG08(0xFC0A406E)
-#define MCF_GPIO_DSCR_LCD               MCF_REG08(0xFC0A406F)
-#define MCF_GPIO_DSCR_DEBUG             MCF_REG08(0xFC0A4070)
-#define MCF_GPIO_DSCR_CLKRST            MCF_REG08(0xFC0A4071)
-#define MCF_GPIO_DSCR_IRQ               MCF_REG08(0xFC0A4072)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
-#define MCF_GPIO_PODR_FECH_PODR_FECH0              (0x01)
-#define MCF_GPIO_PODR_FECH_PODR_FECH1              (0x02)
-#define MCF_GPIO_PODR_FECH_PODR_FECH2              (0x04)
-#define MCF_GPIO_PODR_FECH_PODR_FECH3              (0x08)
-#define MCF_GPIO_PODR_FECH_PODR_FECH4              (0x10)
-#define MCF_GPIO_PODR_FECH_PODR_FECH5              (0x20)
-#define MCF_GPIO_PODR_FECH_PODR_FECH6              (0x40)
-#define MCF_GPIO_PODR_FECH_PODR_FECH7              (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
-#define MCF_GPIO_PODR_FECL_PODR_FECL0              (0x01)
-#define MCF_GPIO_PODR_FECL_PODR_FECL1              (0x02)
-#define MCF_GPIO_PODR_FECL_PODR_FECL2              (0x04)
-#define MCF_GPIO_PODR_FECL_PODR_FECL3              (0x08)
-#define MCF_GPIO_PODR_FECL_PODR_FECL4              (0x10)
-#define MCF_GPIO_PODR_FECL_PODR_FECL5              (0x20)
-#define MCF_GPIO_PODR_FECL_PODR_FECL6              (0x40)
-#define MCF_GPIO_PODR_FECL_PODR_FECL7              (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
-#define MCF_GPIO_PODR_SSI_PODR_SSI0                (0x01)
-#define MCF_GPIO_PODR_SSI_PODR_SSI1                (0x02)
-#define MCF_GPIO_PODR_SSI_PODR_SSI2                (0x04)
-#define MCF_GPIO_PODR_SSI_PODR_SSI3                (0x08)
-#define MCF_GPIO_PODR_SSI_PODR_SSI4                (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
-#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0         (0x01)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1          (0x02)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2          (0x04)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3          (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_BE */
-#define MCF_GPIO_PODR_BE_PODR_BE0                  (0x01)
-#define MCF_GPIO_PODR_BE_PODR_BE1                  (0x02)
-#define MCF_GPIO_PODR_BE_PODR_BE2                  (0x04)
-#define MCF_GPIO_PODR_BE_PODR_BE3                  (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_CS */
-#define MCF_GPIO_PODR_CS_PODR_CS1                  (0x02)
-#define MCF_GPIO_PODR_CS_PODR_CS2                  (0x04)
-#define MCF_GPIO_PODR_CS_PODR_CS3                  (0x08)
-#define MCF_GPIO_PODR_CS_PODR_CS4                  (0x10)
-#define MCF_GPIO_PODR_CS_PODR_CS5                  (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
-#define MCF_GPIO_PODR_PWM_PODR_PWM2                (0x04)
-#define MCF_GPIO_PODR_PWM_PODR_PWM3                (0x08)
-#define MCF_GPIO_PODR_PWM_PODR_PWM4                (0x10)
-#define MCF_GPIO_PODR_PWM_PODR_PWM5                (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0          (0x01)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1          (0x02)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2          (0x04)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3          (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_UART */
-#define MCF_GPIO_PODR_UART_PODR_UART0              (0x01)
-#define MCF_GPIO_PODR_UART_PODR_UART1              (0x02)
-#define MCF_GPIO_PODR_UART_PODR_UART2              (0x04)
-#define MCF_GPIO_PODR_UART_PODR_UART3              (0x08)
-#define MCF_GPIO_PODR_UART_PODR_UART4              (0x10)
-#define MCF_GPIO_PODR_UART_PODR_UART5              (0x20)
-#define MCF_GPIO_PODR_UART_PODR_UART6              (0x40)
-#define MCF_GPIO_PODR_UART_PODR_UART7              (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI0              (0x01)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI1              (0x02)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI2              (0x04)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI3              (0x08)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI4              (0x10)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI5              (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER0            (0x01)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER1            (0x02)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER2            (0x04)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER3            (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
-#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0      (0x01)
-#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1      (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0      (0x01)
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1      (0x02)
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2      (0x04)
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3      (0x08)
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4      (0x10)
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5      (0x20)
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6      (0x40)
-#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0      (0x01)
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1      (0x02)
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2      (0x04)
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3      (0x08)
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4      (0x10)
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5      (0x20)
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6      (0x40)
-#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
-#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0        (0x01)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0        (0x01)
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1        (0x02)
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2        (0x04)
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3        (0x08)
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4        (0x10)
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5        (0x20)
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6        (0x40)
-#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH0              (0x01)
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH1              (0x02)
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH2              (0x04)
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH3              (0x08)
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH4              (0x10)
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH5              (0x20)
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH6              (0x40)
-#define MCF_GPIO_PDDR_FECH_PDDR_FECH7              (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL0              (0x01)
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL1              (0x02)
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL2              (0x04)
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL3              (0x08)
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL4              (0x10)
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL5              (0x20)
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL6              (0x40)
-#define MCF_GPIO_PDDR_FECL_PDDR_FECL7              (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
-#define MCF_GPIO_PDDR_SSI_PDDR_SSI0                (0x01)
-#define MCF_GPIO_PDDR_SSI_PDDR_SSI1                (0x02)
-#define MCF_GPIO_PDDR_SSI_PDDR_SSI2                (0x04)
-#define MCF_GPIO_PDDR_SSI_PDDR_SSI3                (0x08)
-#define MCF_GPIO_PDDR_SSI_PDDR_SSI4                (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
-#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0         (0x01)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1          (0x02)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2          (0x04)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3          (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
-#define MCF_GPIO_PDDR_BE_PDDR_BE0                  (0x01)
-#define MCF_GPIO_PDDR_BE_PDDR_BE1                  (0x02)
-#define MCF_GPIO_PDDR_BE_PDDR_BE2                  (0x04)
-#define MCF_GPIO_PDDR_BE_PDDR_BE3                  (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
-#define MCF_GPIO_PDDR_CS_PDDR_CS1                  (0x02)
-#define MCF_GPIO_PDDR_CS_PDDR_CS2                  (0x04)
-#define MCF_GPIO_PDDR_CS_PDDR_CS3                  (0x08)
-#define MCF_GPIO_PDDR_CS_PDDR_CS4                  (0x10)
-#define MCF_GPIO_PDDR_CS_PDDR_CS5                  (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
-#define MCF_GPIO_PDDR_PWM_PDDR_PWM2                (0x04)
-#define MCF_GPIO_PDDR_PWM_PDDR_PWM3                (0x08)
-#define MCF_GPIO_PDDR_PWM_PDDR_PWM4                (0x10)
-#define MCF_GPIO_PDDR_PWM_PDDR_PWM5                (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0          (0x01)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1          (0x02)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2          (0x04)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3          (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
-#define MCF_GPIO_PDDR_UART_PDDR_UART0              (0x01)
-#define MCF_GPIO_PDDR_UART_PDDR_UART1              (0x02)
-#define MCF_GPIO_PDDR_UART_PDDR_UART2              (0x04)
-#define MCF_GPIO_PDDR_UART_PDDR_UART3              (0x08)
-#define MCF_GPIO_PDDR_UART_PDDR_UART4              (0x10)
-#define MCF_GPIO_PDDR_UART_PDDR_UART5              (0x20)
-#define MCF_GPIO_PDDR_UART_PDDR_UART6              (0x40)
-#define MCF_GPIO_PDDR_UART_PDDR_UART7              (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0              (0x01)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1              (0x02)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2              (0x04)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3              (0x08)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4              (0x10)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5              (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0            (0x01)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1            (0x02)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2            (0x04)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3            (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
-#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0      (0x01)
-#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1      (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0      (0x01)
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1      (0x02)
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2      (0x04)
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3      (0x08)
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4      (0x10)
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5      (0x20)
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6      (0x40)
-#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0      (0x01)
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1      (0x02)
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2      (0x04)
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3      (0x08)
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4      (0x10)
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5      (0x20)
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6      (0x40)
-#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
-#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0        (0x01)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0        (0x01)
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1        (0x02)
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2        (0x04)
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3        (0x08)
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4        (0x10)
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5        (0x20)
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6        (0x40)
-#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0          (0x01)
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1          (0x02)
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2          (0x04)
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3          (0x08)
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4          (0x10)
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5          (0x20)
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6          (0x40)
-#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0          (0x01)
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1          (0x02)
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2          (0x04)
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3          (0x08)
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4          (0x10)
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5          (0x20)
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6          (0x40)
-#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
-#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0            (0x01)
-#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1            (0x02)
-#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2            (0x04)
-#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3            (0x08)
-#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4            (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
-#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0       (0x01)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1      (0x02)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2      (0x04)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3      (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
-#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0              (0x01)
-#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1              (0x02)
-#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2              (0x04)
-#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3              (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1              (0x02)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2              (0x04)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3              (0x08)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4              (0x10)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5              (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
-#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2            (0x04)
-#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3            (0x08)
-#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4            (0x10)
-#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5            (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0      (0x01)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1      (0x02)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2      (0x04)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3      (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0          (0x01)
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1          (0x02)
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2          (0x04)
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3          (0x08)
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4          (0x10)
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5          (0x20)
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6          (0x40)
-#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0          (0x01)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1          (0x02)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2          (0x04)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3          (0x08)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4          (0x10)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5          (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0        (0x01)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1        (0x02)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2        (0x04)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3        (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
-#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0  (0x01)
-#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1  (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0  (0x01)
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1  (0x02)
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2  (0x04)
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3  (0x08)
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4  (0x10)
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5  (0x20)
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6  (0x40)
-#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7  (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0  (0x01)
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1  (0x02)
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2  (0x04)
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3  (0x08)
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4  (0x10)
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5  (0x20)
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6  (0x40)
-#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7  (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
-#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0    (0x01)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0    (0x01)
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1    (0x02)
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2    (0x04)
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3    (0x08)
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4    (0x10)
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5    (0x20)
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6    (0x40)
-#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7    (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0            (0x01)
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1            (0x02)
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2            (0x04)
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3            (0x08)
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4            (0x10)
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5            (0x20)
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6            (0x40)
-#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7            (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0            (0x01)
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1            (0x02)
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2            (0x04)
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3            (0x08)
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4            (0x10)
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5            (0x20)
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6            (0x40)
-#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7            (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
-#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0              (0x01)
-#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1              (0x02)
-#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2              (0x04)
-#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3              (0x08)
-#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4              (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
-#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0        (0x01)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1        (0x02)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2        (0x04)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3        (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
-#define MCF_GPIO_PCLRR_BE_PCLRR_BE0                (0x01)
-#define MCF_GPIO_PCLRR_BE_PCLRR_BE1                (0x02)
-#define MCF_GPIO_PCLRR_BE_PCLRR_BE2                (0x04)
-#define MCF_GPIO_PCLRR_BE_PCLRR_BE3                (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS1                (0x02)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS2                (0x04)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS3                (0x08)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS4                (0x10)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS5                (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
-#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2              (0x04)
-#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3              (0x08)
-#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4              (0x10)
-#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5              (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0        (0x01)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1        (0x02)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2        (0x04)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3        (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART0            (0x01)
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART1            (0x02)
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART2            (0x04)
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART3            (0x08)
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART4            (0x10)
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART5            (0x20)
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART6            (0x40)
-#define MCF_GPIO_PCLRR_UART_PCLRR_UART7            (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0            (0x01)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1            (0x02)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2            (0x04)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3            (0x08)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4            (0x10)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5            (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0          (0x01)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1          (0x02)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2          (0x04)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3          (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
-#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0    (0x01)
-#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1    (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0    (0x01)
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1    (0x02)
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2    (0x04)
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3    (0x08)
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4    (0x10)
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5    (0x20)
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6    (0x40)
-#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7    (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0    (0x01)
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1    (0x02)
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2    (0x04)
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3    (0x08)
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4    (0x10)
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5    (0x20)
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6    (0x40)
-#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7    (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
-#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0      (0x01)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0      (0x01)
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1      (0x02)
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2      (0x04)
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3      (0x08)
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4      (0x10)
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5      (0x20)
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6      (0x40)
-#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
-#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x)            (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x)             (((x)&0x03)<<2)
-#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO           (0x00)
-#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1          (0x04)
-#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC            (0x0C)
-#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO          (0x00)
-#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART          (0x01)
-#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC           (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
-#define MCF_GPIO_PAR_PWM_PAR_PWM1(x)               (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_PWM_PAR_PWM3(x)               (((x)&0x03)<<2)
-#define MCF_GPIO_PAR_PWM_PAR_PWM5                  (0x10)
-#define MCF_GPIO_PAR_PWM_PAR_PWM7                  (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x)              (((x)&0x03)<<3)
-#define MCF_GPIO_PAR_BUSCTL_PAR_RWB                (0x20)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TA                 (0x40)
-#define MCF_GPIO_PAR_BUSCTL_PAR_OE                 (0x80)
-#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO            (0x00)
-#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE              (0x80)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO            (0x00)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA              (0x40)
-#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO           (0x00)
-#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB            (0x20)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO            (0x00)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0           (0x10)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS              (0x18)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x)             (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x)             (((x)&0x03)<<2)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x)            (((x)&0x03)<<4)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x)             (((x)&0x03)<<6)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO           (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2          (0x40)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL            (0x80)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC           (0xC0)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO          (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2         (0x10)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA           (0x20)
-#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO         (0x30)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO           (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2          (0x04)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL            (0x0C)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO           (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2          (0x02)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA            (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_BE */
-#define MCF_GPIO_PAR_BE_PAR_BE0                    (0x01)
-#define MCF_GPIO_PAR_BE_PAR_BE1                    (0x02)
-#define MCF_GPIO_PAR_BE_PAR_BE2                    (0x04)
-#define MCF_GPIO_PAR_BE_PAR_BE3                    (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_CS */
-#define MCF_GPIO_PAR_CS_PAR_CS1                    (0x02)
-#define MCF_GPIO_PAR_CS_PAR_CS2                    (0x04)
-#define MCF_GPIO_PAR_CS_PAR_CS3                    (0x08)
-#define MCF_GPIO_PAR_CS_PAR_CS4                    (0x10)
-#define MCF_GPIO_PAR_CS_PAR_CS5                    (0x20)
-#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO            (0x00)
-#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1           (0x01)
-#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1             (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
-#define MCF_GPIO_PAR_SSI_PAR_MCLK                  (0x0080)
-#define MCF_GPIO_PAR_SSI_PAR_TXD(x)                (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_SSI_PAR_RXD(x)                (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_SSI_PAR_FS(x)                 (((x)&0x0003)<<12)
-#define MCF_GPIO_PAR_SSI_PAR_BCLK(x)               (((x)&0x0003)<<14)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_UART */
-#define MCF_GPIO_PAR_UART_PAR_UTXD0                (0x0001)
-#define MCF_GPIO_PAR_UART_PAR_URXD0                (0x0002)
-#define MCF_GPIO_PAR_UART_PAR_URTS0                (0x0004)
-#define MCF_GPIO_PAR_UART_PAR_UCTS0                (0x0008)
-#define MCF_GPIO_PAR_UART_PAR_UTXD1(x)             (((x)&0x0003)<<4)
-#define MCF_GPIO_PAR_UART_PAR_URXD1(x)             (((x)&0x0003)<<6)
-#define MCF_GPIO_PAR_UART_PAR_URTS1(x)             (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_UART_PAR_UCTS1(x)             (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO           (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK       (0x0800)
-#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7        (0x0400)
-#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1          (0x0C00)
-#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO           (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS         (0x0200)
-#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6        (0x0100)
-#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1          (0x0300)
-#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO           (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD        (0x0080)
-#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5        (0x0040)
-#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1          (0x00C0)
-#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO           (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD        (0x0020)
-#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4        (0x0010)
-#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1          (0x0030)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
-#define MCF_GPIO_PAR_QSPI_PAR_SCK(x)               (((x)&0x0003)<<4)
-#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x)              (((x)&0x0003)<<6)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN(x)               (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x)              (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x)              (((x)&0x0003)<<12)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x)              (((x)&0x0003)<<14)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
-#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x)             (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x)             (((x)&0x03)<<2)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x)             (((x)&0x03)<<4)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x)             (((x)&0x03)<<6)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO           (0x00)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3          (0x80)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2          (0x40)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3           (0xC0)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO           (0x00)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2          (0x20)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2          (0x10)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2           (0x30)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO           (0x00)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1          (0x08)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1          (0x04)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1           (0x0C)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO           (0x00)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0          (0x02)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0          (0x01)
-#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0           (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
-#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x)          (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x)         (((x)&0x03)<<2)
-#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x)           (((x)&0x03)<<4)
-#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x)           (((x)&0x03)<<6)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
-#define MCF_GPIO_PAR_LCDCTL_PAR_CLS                (0x0001)
-#define MCF_GPIO_PAR_LCDCTL_PAR_PS                 (0x0002)
-#define MCF_GPIO_PAR_LCDCTL_PAR_REV                (0x0004)
-#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR            (0x0008)
-#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST           (0x0010)
-#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK              (0x0020)
-#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC           (0x0040)
-#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC          (0x0080)
-#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE             (0x0100)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
-#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x)               (((x)&0x0003)<<4)
-#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x)               (((x)&0x0003)<<6)
-#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x)               (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x)               (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x)               (((x)&0x0003)<<12)
-
-/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
-#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x)      (((x)&0x03)<<0)
-#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x)       (((x)&0x03)<<2)
-#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x)       (((x)&0x03)<<4)
-
-/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
-#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x)          (((x)&0x03)<<0)
-#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x)          (((x)&0x03)<<2)
-#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x)         (((x)&0x03)<<4)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
-#define MCF_GPIO_DSCR_I2C_I2C_DSE(x)               (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
-#define MCF_GPIO_DSCR_PWM_PWM_DSE(x)               (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
-#define MCF_GPIO_DSCR_FEC_FEC_DSE(x)               (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
-#define MCF_GPIO_DSCR_UART_UART0_DSE(x)            (((x)&0x03)<<0)
-#define MCF_GPIO_DSCR_UART_UART1_DSE(x)            (((x)&0x03)<<2)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
-#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x)             (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
-#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x)           (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
-#define MCF_GPIO_DSCR_SSI_SSI_DSE(x)               (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
-#define MCF_GPIO_DSCR_LCD_LCD_DSE(x)               (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
-#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x)           (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
-#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x)         (((x)&0x03)<<0)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
-#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x)               (((x)&0x03)<<0)
-
-/*********************************************************************
- *
- * Interrupt Controller (INTC)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC0_IPRH             MCF_REG32(0xFC048000)
-#define MCF_INTC0_IPRL             MCF_REG32(0xFC048004)
-#define MCF_INTC0_IMRH             MCF_REG32(0xFC048008)
-#define MCF_INTC0_IMRL             MCF_REG32(0xFC04800C)
-#define MCF_INTC0_INTFRCH          MCF_REG32(0xFC048010)
-#define MCF_INTC0_INTFRCL          MCF_REG32(0xFC048014)
-#define MCF_INTC0_ICONFIG          MCF_REG16(0xFC04801A)
-#define MCF_INTC0_SIMR             MCF_REG08(0xFC04801C)
-#define MCF_INTC0_CIMR             MCF_REG08(0xFC04801D)
-#define MCF_INTC0_CLMASK           MCF_REG08(0xFC04801E)
-#define MCF_INTC0_SLMASK           MCF_REG08(0xFC04801F)
-#define MCF_INTC0_ICR0             MCF_REG08(0xFC048040)
-#define MCF_INTC0_ICR1             MCF_REG08(0xFC048041)
-#define MCF_INTC0_ICR2             MCF_REG08(0xFC048042)
-#define MCF_INTC0_ICR3             MCF_REG08(0xFC048043)
-#define MCF_INTC0_ICR4             MCF_REG08(0xFC048044)
-#define MCF_INTC0_ICR5             MCF_REG08(0xFC048045)
-#define MCF_INTC0_ICR6             MCF_REG08(0xFC048046)
-#define MCF_INTC0_ICR7             MCF_REG08(0xFC048047)
-#define MCF_INTC0_ICR8             MCF_REG08(0xFC048048)
-#define MCF_INTC0_ICR9             MCF_REG08(0xFC048049)
-#define MCF_INTC0_ICR10            MCF_REG08(0xFC04804A)
-#define MCF_INTC0_ICR11            MCF_REG08(0xFC04804B)
-#define MCF_INTC0_ICR12            MCF_REG08(0xFC04804C)
-#define MCF_INTC0_ICR13            MCF_REG08(0xFC04804D)
-#define MCF_INTC0_ICR14            MCF_REG08(0xFC04804E)
-#define MCF_INTC0_ICR15            MCF_REG08(0xFC04804F)
-#define MCF_INTC0_ICR16            MCF_REG08(0xFC048050)
-#define MCF_INTC0_ICR17            MCF_REG08(0xFC048051)
-#define MCF_INTC0_ICR18            MCF_REG08(0xFC048052)
-#define MCF_INTC0_ICR19            MCF_REG08(0xFC048053)
-#define MCF_INTC0_ICR20            MCF_REG08(0xFC048054)
-#define MCF_INTC0_ICR21            MCF_REG08(0xFC048055)
-#define MCF_INTC0_ICR22            MCF_REG08(0xFC048056)
-#define MCF_INTC0_ICR23            MCF_REG08(0xFC048057)
-#define MCF_INTC0_ICR24            MCF_REG08(0xFC048058)
-#define MCF_INTC0_ICR25            MCF_REG08(0xFC048059)
-#define MCF_INTC0_ICR26            MCF_REG08(0xFC04805A)
-#define MCF_INTC0_ICR27            MCF_REG08(0xFC04805B)
-#define MCF_INTC0_ICR28            MCF_REG08(0xFC04805C)
-#define MCF_INTC0_ICR29            MCF_REG08(0xFC04805D)
-#define MCF_INTC0_ICR30            MCF_REG08(0xFC04805E)
-#define MCF_INTC0_ICR31            MCF_REG08(0xFC04805F)
-#define MCF_INTC0_ICR32            MCF_REG08(0xFC048060)
-#define MCF_INTC0_ICR33            MCF_REG08(0xFC048061)
-#define MCF_INTC0_ICR34            MCF_REG08(0xFC048062)
-#define MCF_INTC0_ICR35            MCF_REG08(0xFC048063)
-#define MCF_INTC0_ICR36            MCF_REG08(0xFC048064)
-#define MCF_INTC0_ICR37            MCF_REG08(0xFC048065)
-#define MCF_INTC0_ICR38            MCF_REG08(0xFC048066)
-#define MCF_INTC0_ICR39            MCF_REG08(0xFC048067)
-#define MCF_INTC0_ICR40            MCF_REG08(0xFC048068)
-#define MCF_INTC0_ICR41            MCF_REG08(0xFC048069)
-#define MCF_INTC0_ICR42            MCF_REG08(0xFC04806A)
-#define MCF_INTC0_ICR43            MCF_REG08(0xFC04806B)
-#define MCF_INTC0_ICR44            MCF_REG08(0xFC04806C)
-#define MCF_INTC0_ICR45            MCF_REG08(0xFC04806D)
-#define MCF_INTC0_ICR46            MCF_REG08(0xFC04806E)
-#define MCF_INTC0_ICR47            MCF_REG08(0xFC04806F)
-#define MCF_INTC0_ICR48            MCF_REG08(0xFC048070)
-#define MCF_INTC0_ICR49            MCF_REG08(0xFC048071)
-#define MCF_INTC0_ICR50            MCF_REG08(0xFC048072)
-#define MCF_INTC0_ICR51            MCF_REG08(0xFC048073)
-#define MCF_INTC0_ICR52            MCF_REG08(0xFC048074)
-#define MCF_INTC0_ICR53            MCF_REG08(0xFC048075)
-#define MCF_INTC0_ICR54            MCF_REG08(0xFC048076)
-#define MCF_INTC0_ICR55            MCF_REG08(0xFC048077)
-#define MCF_INTC0_ICR56            MCF_REG08(0xFC048078)
-#define MCF_INTC0_ICR57            MCF_REG08(0xFC048079)
-#define MCF_INTC0_ICR58            MCF_REG08(0xFC04807A)
-#define MCF_INTC0_ICR59            MCF_REG08(0xFC04807B)
-#define MCF_INTC0_ICR60            MCF_REG08(0xFC04807C)
-#define MCF_INTC0_ICR61            MCF_REG08(0xFC04807D)
-#define MCF_INTC0_ICR62            MCF_REG08(0xFC04807E)
-#define MCF_INTC0_ICR63            MCF_REG08(0xFC04807F)
-#define MCF_INTC0_ICR(x)           MCF_REG08(0xFC048040+((x)*0x001))
-#define MCF_INTC0_SWIACK           MCF_REG08(0xFC0480E0)
-#define MCF_INTC0_L1IACK           MCF_REG08(0xFC0480E4)
-#define MCF_INTC0_L2IACK           MCF_REG08(0xFC0480E8)
-#define MCF_INTC0_L3IACK           MCF_REG08(0xFC0480EC)
-#define MCF_INTC0_L4IACK           MCF_REG08(0xFC0480F0)
-#define MCF_INTC0_L5IACK           MCF_REG08(0xFC0480F4)
-#define MCF_INTC0_L6IACK           MCF_REG08(0xFC0480F8)
-#define MCF_INTC0_L7IACK           MCF_REG08(0xFC0480FC)
-#define MCF_INTC0_LIACK(x)         MCF_REG08(0xFC0480E4+((x)*0x004))
-#define MCF_INTC1_IPRH             MCF_REG32(0xFC04C000)
-#define MCF_INTC1_IPRL             MCF_REG32(0xFC04C004)
-#define MCF_INTC1_IMRH             MCF_REG32(0xFC04C008)
-#define MCF_INTC1_IMRL             MCF_REG32(0xFC04C00C)
-#define MCF_INTC1_INTFRCH          MCF_REG32(0xFC04C010)
-#define MCF_INTC1_INTFRCL          MCF_REG32(0xFC04C014)
-#define MCF_INTC1_ICONFIG          MCF_REG16(0xFC04C01A)
-#define MCF_INTC1_SIMR             MCF_REG08(0xFC04C01C)
-#define MCF_INTC1_CIMR             MCF_REG08(0xFC04C01D)
-#define MCF_INTC1_CLMASK           MCF_REG08(0xFC04C01E)
-#define MCF_INTC1_SLMASK           MCF_REG08(0xFC04C01F)
-#define MCF_INTC1_ICR0             MCF_REG08(0xFC04C040)
-#define MCF_INTC1_ICR1             MCF_REG08(0xFC04C041)
-#define MCF_INTC1_ICR2             MCF_REG08(0xFC04C042)
-#define MCF_INTC1_ICR3             MCF_REG08(0xFC04C043)
-#define MCF_INTC1_ICR4             MCF_REG08(0xFC04C044)
-#define MCF_INTC1_ICR5             MCF_REG08(0xFC04C045)
-#define MCF_INTC1_ICR6             MCF_REG08(0xFC04C046)
-#define MCF_INTC1_ICR7             MCF_REG08(0xFC04C047)
-#define MCF_INTC1_ICR8             MCF_REG08(0xFC04C048)
-#define MCF_INTC1_ICR9             MCF_REG08(0xFC04C049)
-#define MCF_INTC1_ICR10            MCF_REG08(0xFC04C04A)
-#define MCF_INTC1_ICR11            MCF_REG08(0xFC04C04B)
-#define MCF_INTC1_ICR12            MCF_REG08(0xFC04C04C)
-#define MCF_INTC1_ICR13            MCF_REG08(0xFC04C04D)
-#define MCF_INTC1_ICR14            MCF_REG08(0xFC04C04E)
-#define MCF_INTC1_ICR15            MCF_REG08(0xFC04C04F)
-#define MCF_INTC1_ICR16            MCF_REG08(0xFC04C050)
-#define MCF_INTC1_ICR17            MCF_REG08(0xFC04C051)
-#define MCF_INTC1_ICR18            MCF_REG08(0xFC04C052)
-#define MCF_INTC1_ICR19            MCF_REG08(0xFC04C053)
-#define MCF_INTC1_ICR20            MCF_REG08(0xFC04C054)
-#define MCF_INTC1_ICR21            MCF_REG08(0xFC04C055)
-#define MCF_INTC1_ICR22            MCF_REG08(0xFC04C056)
-#define MCF_INTC1_ICR23            MCF_REG08(0xFC04C057)
-#define MCF_INTC1_ICR24            MCF_REG08(0xFC04C058)
-#define MCF_INTC1_ICR25            MCF_REG08(0xFC04C059)
-#define MCF_INTC1_ICR26            MCF_REG08(0xFC04C05A)
-#define MCF_INTC1_ICR27            MCF_REG08(0xFC04C05B)
-#define MCF_INTC1_ICR28            MCF_REG08(0xFC04C05C)
-#define MCF_INTC1_ICR29            MCF_REG08(0xFC04C05D)
-#define MCF_INTC1_ICR30            MCF_REG08(0xFC04C05E)
-#define MCF_INTC1_ICR31            MCF_REG08(0xFC04C05F)
-#define MCF_INTC1_ICR32            MCF_REG08(0xFC04C060)
-#define MCF_INTC1_ICR33            MCF_REG08(0xFC04C061)
-#define MCF_INTC1_ICR34            MCF_REG08(0xFC04C062)
-#define MCF_INTC1_ICR35            MCF_REG08(0xFC04C063)
-#define MCF_INTC1_ICR36            MCF_REG08(0xFC04C064)
-#define MCF_INTC1_ICR37            MCF_REG08(0xFC04C065)
-#define MCF_INTC1_ICR38            MCF_REG08(0xFC04C066)
-#define MCF_INTC1_ICR39            MCF_REG08(0xFC04C067)
-#define MCF_INTC1_ICR40            MCF_REG08(0xFC04C068)
-#define MCF_INTC1_ICR41            MCF_REG08(0xFC04C069)
-#define MCF_INTC1_ICR42            MCF_REG08(0xFC04C06A)
-#define MCF_INTC1_ICR43            MCF_REG08(0xFC04C06B)
-#define MCF_INTC1_ICR44            MCF_REG08(0xFC04C06C)
-#define MCF_INTC1_ICR45            MCF_REG08(0xFC04C06D)
-#define MCF_INTC1_ICR46            MCF_REG08(0xFC04C06E)
-#define MCF_INTC1_ICR47            MCF_REG08(0xFC04C06F)
-#define MCF_INTC1_ICR48            MCF_REG08(0xFC04C070)
-#define MCF_INTC1_ICR49            MCF_REG08(0xFC04C071)
-#define MCF_INTC1_ICR50            MCF_REG08(0xFC04C072)
-#define MCF_INTC1_ICR51            MCF_REG08(0xFC04C073)
-#define MCF_INTC1_ICR52            MCF_REG08(0xFC04C074)
-#define MCF_INTC1_ICR53            MCF_REG08(0xFC04C075)
-#define MCF_INTC1_ICR54            MCF_REG08(0xFC04C076)
-#define MCF_INTC1_ICR55            MCF_REG08(0xFC04C077)
-#define MCF_INTC1_ICR56            MCF_REG08(0xFC04C078)
-#define MCF_INTC1_ICR57            MCF_REG08(0xFC04C079)
-#define MCF_INTC1_ICR58            MCF_REG08(0xFC04C07A)
-#define MCF_INTC1_ICR59            MCF_REG08(0xFC04C07B)
-#define MCF_INTC1_ICR60            MCF_REG08(0xFC04C07C)
-#define MCF_INTC1_ICR61            MCF_REG08(0xFC04C07D)
-#define MCF_INTC1_ICR62            MCF_REG08(0xFC04C07E)
-#define MCF_INTC1_ICR63            MCF_REG08(0xFC04C07F)
-#define MCF_INTC1_ICR(x)           MCF_REG08(0xFC04C040+((x)*0x001))
-#define MCF_INTC1_SWIACK           MCF_REG08(0xFC04C0E0)
-#define MCF_INTC1_L1IACK           MCF_REG08(0xFC04C0E4)
-#define MCF_INTC1_L2IACK           MCF_REG08(0xFC04C0E8)
-#define MCF_INTC1_L3IACK           MCF_REG08(0xFC04C0EC)
-#define MCF_INTC1_L4IACK           MCF_REG08(0xFC04C0F0)
-#define MCF_INTC1_L5IACK           MCF_REG08(0xFC04C0F4)
-#define MCF_INTC1_L6IACK           MCF_REG08(0xFC04C0F8)
-#define MCF_INTC1_L7IACK           MCF_REG08(0xFC04C0FC)
-#define MCF_INTC1_LIACK(x)         MCF_REG08(0xFC04C0E4+((x)*0x004))
-#define MCF_INTC_IPRH(x)           MCF_REG32(0xFC048000+((x)*0x4000))
-#define MCF_INTC_IPRL(x)           MCF_REG32(0xFC048004+((x)*0x4000))
-#define MCF_INTC_IMRH(x)           MCF_REG32(0xFC048008+((x)*0x4000))
-#define MCF_INTC_IMRL(x)           MCF_REG32(0xFC04800C+((x)*0x4000))
-#define MCF_INTC_INTFRCH(x)        MCF_REG32(0xFC048010+((x)*0x4000))
-#define MCF_INTC_INTFRCL(x)        MCF_REG32(0xFC048014+((x)*0x4000))
-#define MCF_INTC_ICONFIG(x)        MCF_REG16(0xFC04801A+((x)*0x4000))
-#define MCF_INTC_SIMR(x)           MCF_REG08(0xFC04801C+((x)*0x4000))
-#define MCF_INTC_CIMR(x)           MCF_REG08(0xFC04801D+((x)*0x4000))
-#define MCF_INTC_CLMASK(x)         MCF_REG08(0xFC04801E+((x)*0x4000))
-#define MCF_INTC_SLMASK(x)         MCF_REG08(0xFC04801F+((x)*0x4000))
-#define MCF_INTC_ICR0(x)           MCF_REG08(0xFC048040+((x)*0x4000))
-#define MCF_INTC_ICR1(x)           MCF_REG08(0xFC048041+((x)*0x4000))
-#define MCF_INTC_ICR2(x)           MCF_REG08(0xFC048042+((x)*0x4000))
-#define MCF_INTC_ICR3(x)           MCF_REG08(0xFC048043+((x)*0x4000))
-#define MCF_INTC_ICR4(x)           MCF_REG08(0xFC048044+((x)*0x4000))
-#define MCF_INTC_ICR5(x)           MCF_REG08(0xFC048045+((x)*0x4000))
-#define MCF_INTC_ICR6(x)           MCF_REG08(0xFC048046+((x)*0x4000))
-#define MCF_INTC_ICR7(x)           MCF_REG08(0xFC048047+((x)*0x4000))
-#define MCF_INTC_ICR8(x)           MCF_REG08(0xFC048048+((x)*0x4000))
-#define MCF_INTC_ICR9(x)           MCF_REG08(0xFC048049+((x)*0x4000))
-#define MCF_INTC_ICR10(x)          MCF_REG08(0xFC04804A+((x)*0x4000))
-#define MCF_INTC_ICR11(x)          MCF_REG08(0xFC04804B+((x)*0x4000))
-#define MCF_INTC_ICR12(x)          MCF_REG08(0xFC04804C+((x)*0x4000))
-#define MCF_INTC_ICR13(x)          MCF_REG08(0xFC04804D+((x)*0x4000))
-#define MCF_INTC_ICR14(x)          MCF_REG08(0xFC04804E+((x)*0x4000))
-#define MCF_INTC_ICR15(x)          MCF_REG08(0xFC04804F+((x)*0x4000))
-#define MCF_INTC_ICR16(x)          MCF_REG08(0xFC048050+((x)*0x4000))
-#define MCF_INTC_ICR17(x)          MCF_REG08(0xFC048051+((x)*0x4000))
-#define MCF_INTC_ICR18(x)          MCF_REG08(0xFC048052+((x)*0x4000))
-#define MCF_INTC_ICR19(x)          MCF_REG08(0xFC048053+((x)*0x4000))
-#define MCF_INTC_ICR20(x)          MCF_REG08(0xFC048054+((x)*0x4000))
-#define MCF_INTC_ICR21(x)          MCF_REG08(0xFC048055+((x)*0x4000))
-#define MCF_INTC_ICR22(x)          MCF_REG08(0xFC048056+((x)*0x4000))
-#define MCF_INTC_ICR23(x)          MCF_REG08(0xFC048057+((x)*0x4000))
-#define MCF_INTC_ICR24(x)          MCF_REG08(0xFC048058+((x)*0x4000))
-#define MCF_INTC_ICR25(x)          MCF_REG08(0xFC048059+((x)*0x4000))
-#define MCF_INTC_ICR26(x)          MCF_REG08(0xFC04805A+((x)*0x4000))
-#define MCF_INTC_ICR27(x)          MCF_REG08(0xFC04805B+((x)*0x4000))
-#define MCF_INTC_ICR28(x)          MCF_REG08(0xFC04805C+((x)*0x4000))
-#define MCF_INTC_ICR29(x)          MCF_REG08(0xFC04805D+((x)*0x4000))
-#define MCF_INTC_ICR30(x)          MCF_REG08(0xFC04805E+((x)*0x4000))
-#define MCF_INTC_ICR31(x)          MCF_REG08(0xFC04805F+((x)*0x4000))
-#define MCF_INTC_ICR32(x)          MCF_REG08(0xFC048060+((x)*0x4000))
-#define MCF_INTC_ICR33(x)          MCF_REG08(0xFC048061+((x)*0x4000))
-#define MCF_INTC_ICR34(x)          MCF_REG08(0xFC048062+((x)*0x4000))
-#define MCF_INTC_ICR35(x)          MCF_REG08(0xFC048063+((x)*0x4000))
-#define MCF_INTC_ICR36(x)          MCF_REG08(0xFC048064+((x)*0x4000))
-#define MCF_INTC_ICR37(x)          MCF_REG08(0xFC048065+((x)*0x4000))
-#define MCF_INTC_ICR38(x)          MCF_REG08(0xFC048066+((x)*0x4000))
-#define MCF_INTC_ICR39(x)          MCF_REG08(0xFC048067+((x)*0x4000))
-#define MCF_INTC_ICR40(x)          MCF_REG08(0xFC048068+((x)*0x4000))
-#define MCF_INTC_ICR41(x)          MCF_REG08(0xFC048069+((x)*0x4000))
-#define MCF_INTC_ICR42(x)          MCF_REG08(0xFC04806A+((x)*0x4000))
-#define MCF_INTC_ICR43(x)          MCF_REG08(0xFC04806B+((x)*0x4000))
-#define MCF_INTC_ICR44(x)          MCF_REG08(0xFC04806C+((x)*0x4000))
-#define MCF_INTC_ICR45(x)          MCF_REG08(0xFC04806D+((x)*0x4000))
-#define MCF_INTC_ICR46(x)          MCF_REG08(0xFC04806E+((x)*0x4000))
-#define MCF_INTC_ICR47(x)          MCF_REG08(0xFC04806F+((x)*0x4000))
-#define MCF_INTC_ICR48(x)          MCF_REG08(0xFC048070+((x)*0x4000))
-#define MCF_INTC_ICR49(x)          MCF_REG08(0xFC048071+((x)*0x4000))
-#define MCF_INTC_ICR50(x)          MCF_REG08(0xFC048072+((x)*0x4000))
-#define MCF_INTC_ICR51(x)          MCF_REG08(0xFC048073+((x)*0x4000))
-#define MCF_INTC_ICR52(x)          MCF_REG08(0xFC048074+((x)*0x4000))
-#define MCF_INTC_ICR53(x)          MCF_REG08(0xFC048075+((x)*0x4000))
-#define MCF_INTC_ICR54(x)          MCF_REG08(0xFC048076+((x)*0x4000))
-#define MCF_INTC_ICR55(x)          MCF_REG08(0xFC048077+((x)*0x4000))
-#define MCF_INTC_ICR56(x)          MCF_REG08(0xFC048078+((x)*0x4000))
-#define MCF_INTC_ICR57(x)          MCF_REG08(0xFC048079+((x)*0x4000))
-#define MCF_INTC_ICR58(x)          MCF_REG08(0xFC04807A+((x)*0x4000))
-#define MCF_INTC_ICR59(x)          MCF_REG08(0xFC04807B+((x)*0x4000))
-#define MCF_INTC_ICR60(x)          MCF_REG08(0xFC04807C+((x)*0x4000))
-#define MCF_INTC_ICR61(x)          MCF_REG08(0xFC04807D+((x)*0x4000))
-#define MCF_INTC_ICR62(x)          MCF_REG08(0xFC04807E+((x)*0x4000))
-#define MCF_INTC_ICR63(x)          MCF_REG08(0xFC04807F+((x)*0x4000))
-#define MCF_INTC_SWIACK(x)         MCF_REG08(0xFC0480E0+((x)*0x4000))
-#define MCF_INTC_L1IACK(x)         MCF_REG08(0xFC0480E4+((x)*0x4000))
-#define MCF_INTC_L2IACK(x)         MCF_REG08(0xFC0480E8+((x)*0x4000))
-#define MCF_INTC_L3IACK(x)         MCF_REG08(0xFC0480EC+((x)*0x4000))
-#define MCF_INTC_L4IACK(x)         MCF_REG08(0xFC0480F0+((x)*0x4000))
-#define MCF_INTC_L5IACK(x)         MCF_REG08(0xFC0480F4+((x)*0x4000))
-#define MCF_INTC_L6IACK(x)         MCF_REG08(0xFC0480F8+((x)*0x4000))
-#define MCF_INTC_L7IACK(x)         MCF_REG08(0xFC0480FC+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_INTC_IPRH */
-#define MCF_INTC_IPRH_INT32        (0x00000001)
-#define MCF_INTC_IPRH_INT33        (0x00000002)
-#define MCF_INTC_IPRH_INT34        (0x00000004)
-#define MCF_INTC_IPRH_INT35        (0x00000008)
-#define MCF_INTC_IPRH_INT36        (0x00000010)
-#define MCF_INTC_IPRH_INT37        (0x00000020)
-#define MCF_INTC_IPRH_INT38        (0x00000040)
-#define MCF_INTC_IPRH_INT39        (0x00000080)
-#define MCF_INTC_IPRH_INT40        (0x00000100)
-#define MCF_INTC_IPRH_INT41        (0x00000200)
-#define MCF_INTC_IPRH_INT42        (0x00000400)
-#define MCF_INTC_IPRH_INT43        (0x00000800)
-#define MCF_INTC_IPRH_INT44        (0x00001000)
-#define MCF_INTC_IPRH_INT45        (0x00002000)
-#define MCF_INTC_IPRH_INT46        (0x00004000)
-#define MCF_INTC_IPRH_INT47        (0x00008000)
-#define MCF_INTC_IPRH_INT48        (0x00010000)
-#define MCF_INTC_IPRH_INT49        (0x00020000)
-#define MCF_INTC_IPRH_INT50        (0x00040000)
-#define MCF_INTC_IPRH_INT51        (0x00080000)
-#define MCF_INTC_IPRH_INT52        (0x00100000)
-#define MCF_INTC_IPRH_INT53        (0x00200000)
-#define MCF_INTC_IPRH_INT54        (0x00400000)
-#define MCF_INTC_IPRH_INT55        (0x00800000)
-#define MCF_INTC_IPRH_INT56        (0x01000000)
-#define MCF_INTC_IPRH_INT57        (0x02000000)
-#define MCF_INTC_IPRH_INT58        (0x04000000)
-#define MCF_INTC_IPRH_INT59        (0x08000000)
-#define MCF_INTC_IPRH_INT60        (0x10000000)
-#define MCF_INTC_IPRH_INT61        (0x20000000)
-#define MCF_INTC_IPRH_INT62        (0x40000000)
-#define MCF_INTC_IPRH_INT63        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IPRL */
-#define MCF_INTC_IPRL_INT0         (0x00000001)
-#define MCF_INTC_IPRL_INT1         (0x00000002)
-#define MCF_INTC_IPRL_INT2         (0x00000004)
-#define MCF_INTC_IPRL_INT3         (0x00000008)
-#define MCF_INTC_IPRL_INT4         (0x00000010)
-#define MCF_INTC_IPRL_INT5         (0x00000020)
-#define MCF_INTC_IPRL_INT6         (0x00000040)
-#define MCF_INTC_IPRL_INT7         (0x00000080)
-#define MCF_INTC_IPRL_INT8         (0x00000100)
-#define MCF_INTC_IPRL_INT9         (0x00000200)
-#define MCF_INTC_IPRL_INT10        (0x00000400)
-#define MCF_INTC_IPRL_INT11        (0x00000800)
-#define MCF_INTC_IPRL_INT12        (0x00001000)
-#define MCF_INTC_IPRL_INT13        (0x00002000)
-#define MCF_INTC_IPRL_INT14        (0x00004000)
-#define MCF_INTC_IPRL_INT15        (0x00008000)
-#define MCF_INTC_IPRL_INT16        (0x00010000)
-#define MCF_INTC_IPRL_INT17        (0x00020000)
-#define MCF_INTC_IPRL_INT18        (0x00040000)
-#define MCF_INTC_IPRL_INT19        (0x00080000)
-#define MCF_INTC_IPRL_INT20        (0x00100000)
-#define MCF_INTC_IPRL_INT21        (0x00200000)
-#define MCF_INTC_IPRL_INT22        (0x00400000)
-#define MCF_INTC_IPRL_INT23        (0x00800000)
-#define MCF_INTC_IPRL_INT24        (0x01000000)
-#define MCF_INTC_IPRL_INT25        (0x02000000)
-#define MCF_INTC_IPRL_INT26        (0x04000000)
-#define MCF_INTC_IPRL_INT27        (0x08000000)
-#define MCF_INTC_IPRL_INT28        (0x10000000)
-#define MCF_INTC_IPRL_INT29        (0x20000000)
-#define MCF_INTC_IPRL_INT30        (0x40000000)
-#define MCF_INTC_IPRL_INT31        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRH */
-#define MCF_INTC_IMRH_INT_MASK32   (0x00000001)
-#define MCF_INTC_IMRH_INT_MASK33   (0x00000002)
-#define MCF_INTC_IMRH_INT_MASK34   (0x00000004)
-#define MCF_INTC_IMRH_INT_MASK35   (0x00000008)
-#define MCF_INTC_IMRH_INT_MASK36   (0x00000010)
-#define MCF_INTC_IMRH_INT_MASK37   (0x00000020)
-#define MCF_INTC_IMRH_INT_MASK38   (0x00000040)
-#define MCF_INTC_IMRH_INT_MASK39   (0x00000080)
-#define MCF_INTC_IMRH_INT_MASK40   (0x00000100)
-#define MCF_INTC_IMRH_INT_MASK41   (0x00000200)
-#define MCF_INTC_IMRH_INT_MASK42   (0x00000400)
-#define MCF_INTC_IMRH_INT_MASK43   (0x00000800)
-#define MCF_INTC_IMRH_INT_MASK44   (0x00001000)
-#define MCF_INTC_IMRH_INT_MASK45   (0x00002000)
-#define MCF_INTC_IMRH_INT_MASK46   (0x00004000)
-#define MCF_INTC_IMRH_INT_MASK47   (0x00008000)
-#define MCF_INTC_IMRH_INT_MASK48   (0x00010000)
-#define MCF_INTC_IMRH_INT_MASK49   (0x00020000)
-#define MCF_INTC_IMRH_INT_MASK50   (0x00040000)
-#define MCF_INTC_IMRH_INT_MASK51   (0x00080000)
-#define MCF_INTC_IMRH_INT_MASK52   (0x00100000)
-#define MCF_INTC_IMRH_INT_MASK53   (0x00200000)
-#define MCF_INTC_IMRH_INT_MASK54   (0x00400000)
-#define MCF_INTC_IMRH_INT_MASK55   (0x00800000)
-#define MCF_INTC_IMRH_INT_MASK56   (0x01000000)
-#define MCF_INTC_IMRH_INT_MASK57   (0x02000000)
-#define MCF_INTC_IMRH_INT_MASK58   (0x04000000)
-#define MCF_INTC_IMRH_INT_MASK59   (0x08000000)
-#define MCF_INTC_IMRH_INT_MASK60   (0x10000000)
-#define MCF_INTC_IMRH_INT_MASK61   (0x20000000)
-#define MCF_INTC_IMRH_INT_MASK62   (0x40000000)
-#define MCF_INTC_IMRH_INT_MASK63   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRL */
-#define MCF_INTC_IMRL_INT_MASK0    (0x00000001)
-#define MCF_INTC_IMRL_INT_MASK1    (0x00000002)
-#define MCF_INTC_IMRL_INT_MASK2    (0x00000004)
-#define MCF_INTC_IMRL_INT_MASK3    (0x00000008)
-#define MCF_INTC_IMRL_INT_MASK4    (0x00000010)
-#define MCF_INTC_IMRL_INT_MASK5    (0x00000020)
-#define MCF_INTC_IMRL_INT_MASK6    (0x00000040)
-#define MCF_INTC_IMRL_INT_MASK7    (0x00000080)
-#define MCF_INTC_IMRL_INT_MASK8    (0x00000100)
-#define MCF_INTC_IMRL_INT_MASK9    (0x00000200)
-#define MCF_INTC_IMRL_INT_MASK10   (0x00000400)
-#define MCF_INTC_IMRL_INT_MASK11   (0x00000800)
-#define MCF_INTC_IMRL_INT_MASK12   (0x00001000)
-#define MCF_INTC_IMRL_INT_MASK13   (0x00002000)
-#define MCF_INTC_IMRL_INT_MASK14   (0x00004000)
-#define MCF_INTC_IMRL_INT_MASK15   (0x00008000)
-#define MCF_INTC_IMRL_INT_MASK16   (0x00010000)
-#define MCF_INTC_IMRL_INT_MASK17   (0x00020000)
-#define MCF_INTC_IMRL_INT_MASK18   (0x00040000)
-#define MCF_INTC_IMRL_INT_MASK19   (0x00080000)
-#define MCF_INTC_IMRL_INT_MASK20   (0x00100000)
-#define MCF_INTC_IMRL_INT_MASK21   (0x00200000)
-#define MCF_INTC_IMRL_INT_MASK22   (0x00400000)
-#define MCF_INTC_IMRL_INT_MASK23   (0x00800000)
-#define MCF_INTC_IMRL_INT_MASK24   (0x01000000)
-#define MCF_INTC_IMRL_INT_MASK25   (0x02000000)
-#define MCF_INTC_IMRL_INT_MASK26   (0x04000000)
-#define MCF_INTC_IMRL_INT_MASK27   (0x08000000)
-#define MCF_INTC_IMRL_INT_MASK28   (0x10000000)
-#define MCF_INTC_IMRL_INT_MASK29   (0x20000000)
-#define MCF_INTC_IMRL_INT_MASK30   (0x40000000)
-#define MCF_INTC_IMRL_INT_MASK31   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCH */
-#define MCF_INTC_INTFRCH_INTFRC32  (0x00000001)
-#define MCF_INTC_INTFRCH_INTFRC33  (0x00000002)
-#define MCF_INTC_INTFRCH_INTFRC34  (0x00000004)
-#define MCF_INTC_INTFRCH_INTFRC35  (0x00000008)
-#define MCF_INTC_INTFRCH_INTFRC36  (0x00000010)
-#define MCF_INTC_INTFRCH_INTFRC37  (0x00000020)
-#define MCF_INTC_INTFRCH_INTFRC38  (0x00000040)
-#define MCF_INTC_INTFRCH_INTFRC39  (0x00000080)
-#define MCF_INTC_INTFRCH_INTFRC40  (0x00000100)
-#define MCF_INTC_INTFRCH_INTFRC41  (0x00000200)
-#define MCF_INTC_INTFRCH_INTFRC42  (0x00000400)
-#define MCF_INTC_INTFRCH_INTFRC43  (0x00000800)
-#define MCF_INTC_INTFRCH_INTFRC44  (0x00001000)
-#define MCF_INTC_INTFRCH_INTFRC45  (0x00002000)
-#define MCF_INTC_INTFRCH_INTFRC46  (0x00004000)
-#define MCF_INTC_INTFRCH_INTFRC47  (0x00008000)
-#define MCF_INTC_INTFRCH_INTFRC48  (0x00010000)
-#define MCF_INTC_INTFRCH_INTFRC49  (0x00020000)
-#define MCF_INTC_INTFRCH_INTFRC50  (0x00040000)
-#define MCF_INTC_INTFRCH_INTFRC51  (0x00080000)
-#define MCF_INTC_INTFRCH_INTFRC52  (0x00100000)
-#define MCF_INTC_INTFRCH_INTFRC53  (0x00200000)
-#define MCF_INTC_INTFRCH_INTFRC54  (0x00400000)
-#define MCF_INTC_INTFRCH_INTFRC55  (0x00800000)
-#define MCF_INTC_INTFRCH_INTFRC56  (0x01000000)
-#define MCF_INTC_INTFRCH_INTFRC57  (0x02000000)
-#define MCF_INTC_INTFRCH_INTFRC58  (0x04000000)
-#define MCF_INTC_INTFRCH_INTFRC59  (0x08000000)
-#define MCF_INTC_INTFRCH_INTFRC60  (0x10000000)
-#define MCF_INTC_INTFRCH_INTFRC61  (0x20000000)
-#define MCF_INTC_INTFRCH_INTFRC62  (0x40000000)
-#define MCF_INTC_INTFRCH_INTFRC63  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCL */
-#define MCF_INTC_INTFRCL_INTFRC0   (0x00000001)
-#define MCF_INTC_INTFRCL_INTFRC1   (0x00000002)
-#define MCF_INTC_INTFRCL_INTFRC2   (0x00000004)
-#define MCF_INTC_INTFRCL_INTFRC3   (0x00000008)
-#define MCF_INTC_INTFRCL_INTFRC4   (0x00000010)
-#define MCF_INTC_INTFRCL_INTFRC5   (0x00000020)
-#define MCF_INTC_INTFRCL_INTFRC6   (0x00000040)
-#define MCF_INTC_INTFRCL_INTFRC7   (0x00000080)
-#define MCF_INTC_INTFRCL_INTFRC8   (0x00000100)
-#define MCF_INTC_INTFRCL_INTFRC9   (0x00000200)
-#define MCF_INTC_INTFRCL_INTFRC10  (0x00000400)
-#define MCF_INTC_INTFRCL_INTFRC11  (0x00000800)
-#define MCF_INTC_INTFRCL_INTFRC12  (0x00001000)
-#define MCF_INTC_INTFRCL_INTFRC13  (0x00002000)
-#define MCF_INTC_INTFRCL_INTFRC14  (0x00004000)
-#define MCF_INTC_INTFRCL_INTFRC15  (0x00008000)
-#define MCF_INTC_INTFRCL_INTFRC16  (0x00010000)
-#define MCF_INTC_INTFRCL_INTFRC17  (0x00020000)
-#define MCF_INTC_INTFRCL_INTFRC18  (0x00040000)
-#define MCF_INTC_INTFRCL_INTFRC19  (0x00080000)
-#define MCF_INTC_INTFRCL_INTFRC20  (0x00100000)
-#define MCF_INTC_INTFRCL_INTFRC21  (0x00200000)
-#define MCF_INTC_INTFRCL_INTFRC22  (0x00400000)
-#define MCF_INTC_INTFRCL_INTFRC23  (0x00800000)
-#define MCF_INTC_INTFRCL_INTFRC24  (0x01000000)
-#define MCF_INTC_INTFRCL_INTFRC25  (0x02000000)
-#define MCF_INTC_INTFRCL_INTFRC26  (0x04000000)
-#define MCF_INTC_INTFRCL_INTFRC27  (0x08000000)
-#define MCF_INTC_INTFRCL_INTFRC28  (0x10000000)
-#define MCF_INTC_INTFRCL_INTFRC29  (0x20000000)
-#define MCF_INTC_INTFRCL_INTFRC30  (0x40000000)
-#define MCF_INTC_INTFRCL_INTFRC31  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_ICONFIG */
-#define MCF_INTC_ICONFIG_EMASK     (0x0020)
-#define MCF_INTC_ICONFIG_ELVLPRI1  (0x0200)
-#define MCF_INTC_ICONFIG_ELVLPRI2  (0x0400)
-#define MCF_INTC_ICONFIG_ELVLPRI3  (0x0800)
-#define MCF_INTC_ICONFIG_ELVLPRI4  (0x1000)
-#define MCF_INTC_ICONFIG_ELVLPRI5  (0x2000)
-#define MCF_INTC_ICONFIG_ELVLPRI6  (0x4000)
-#define MCF_INTC_ICONFIG_ELVLPRI7  (0x8000)
-
-/* Bit definitions and macros for MCF_INTC_SIMR */
-#define MCF_INTC_SIMR_SIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CIMR */
-#define MCF_INTC_CIMR_CIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CLMASK */
-#define MCF_INTC_CLMASK_CLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SLMASK */
-#define MCF_INTC_SLMASK_SLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_ICR */
-#define MCF_INTC_ICR_IL(x)         (((x)&0x07)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SWIACK */
-#define MCF_INTC_SWIACK_VECTOR(x)  (((x)&0xFF)<<0)
-
-/* Bit definitions and macros for MCF_INTC_LIACK */
-#define MCF_INTC_LIACK_VECTOR(x)   (((x)&0xFF)<<0)
-
-/********************************************************************/
-/*********************************************************************
-*
-* LCD Controller (LCDC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_LCDC_LSSAR                  MCF_REG32(0xFC0AC000)
-#define MCF_LCDC_LSR                    MCF_REG32(0xFC0AC004)
-#define MCF_LCDC_LVPWR                  MCF_REG32(0xFC0AC008)
-#define MCF_LCDC_LCPR                   MCF_REG32(0xFC0AC00C)
-#define MCF_LCDC_LCWHBR                 MCF_REG32(0xFC0AC010)
-#define MCF_LCDC_LCCMR                  MCF_REG32(0xFC0AC014)
-#define MCF_LCDC_LPCR                   MCF_REG32(0xFC0AC018)
-#define MCF_LCDC_LHCR                   MCF_REG32(0xFC0AC01C)
-#define MCF_LCDC_LVCR                   MCF_REG32(0xFC0AC020)
-#define MCF_LCDC_LPOR                   MCF_REG32(0xFC0AC024)
-#define MCF_LCDC_LSCR                   MCF_REG32(0xFC0AC028)
-#define MCF_LCDC_LPCCR                  MCF_REG32(0xFC0AC02C)
-#define MCF_LCDC_LDCR                   MCF_REG32(0xFC0AC030)
-#define MCF_LCDC_LRMCR                  MCF_REG32(0xFC0AC034)
-#define MCF_LCDC_LICR                   MCF_REG32(0xFC0AC038)
-#define MCF_LCDC_LIER                   MCF_REG32(0xFC0AC03C)
-#define MCF_LCDC_LISR                   MCF_REG32(0xFC0AC040)
-#define MCF_LCDC_LGWSAR                 MCF_REG32(0xFC0AC050)
-#define MCF_LCDC_LGWSR                  MCF_REG32(0xFC0AC054)
-#define MCF_LCDC_LGWVPWR                MCF_REG32(0xFC0AC058)
-#define MCF_LCDC_LGWPOR                 MCF_REG32(0xFC0AC05C)
-#define MCF_LCDC_LGWPR                  MCF_REG32(0xFC0AC060)
-#define MCF_LCDC_LGWCR                  MCF_REG32(0xFC0AC064)
-#define MCF_LCDC_LGWDCR                 MCF_REG32(0xFC0AC068)
-#define MCF_LCDC_BPLUT_BASE             MCF_REG32(0xFC0AC800)
-#define MCF_LCDC_GWLUT_BASE             MCF_REG32(0xFC0ACC00)
-
-/* Bit definitions and macros for MCF_LCDC_LSSAR */
-#define MCF_LCDC_LSSAR_SSA(x)           (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LSR */
-#define MCF_LCDC_LSR_YMAX(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LSR_XMAX(x)            (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LVPWR */
-#define MCF_LCDC_LVPWR_VPW(x)           (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LCPR */
-#define MCF_LCDC_LCPR_CYP(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LCPR_CXP(x)            (((x)&0x000003FF)<<16)
-#define MCF_LCDC_LCPR_OP                (0x10000000)
-#define MCF_LCDC_LCPR_CC(x)             (((x)&0x00000003)<<30)
-#define MCF_LCDC_LCPR_CC_TRANSPARENT    (0x00000000)
-#define MCF_LCDC_LCPR_CC_OR             (0x40000000)
-#define MCF_LCDC_LCPR_CC_XOR            (0x80000000)
-#define MCF_LCDC_LCPR_CC_AND            (0xC0000000)
-#define MCF_LCDC_LCPR_OP_ON             (0x10000000)
-#define MCF_LCDC_LCPR_OP_OFF            (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCWHBR */
-#define MCF_LCDC_LCWHBR_BD(x)           (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LCWHBR_CH(x)           (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LCWHBR_CW(x)           (((x)&0x0000001F)<<24)
-#define MCF_LCDC_LCWHBR_BK_EN           (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_ON        (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_OFF       (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCCMR */
-#define MCF_LCDC_LCCMR_CUR_COL_B(x)     (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LCCMR_CUR_COL_G(x)     (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LCCMR_CUR_COL_R(x)     (((x)&0x0000003F)<<12)
-
-/* Bit definitions and macros for MCF_LCDC_LPCR */
-#define MCF_LCDC_LPCR_PCD(x)            (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LPCR_SHARP             (0x00000040)
-#define MCF_LCDC_LPCR_SCLKSEL           (0x00000080)
-#define MCF_LCDC_LPCR_ACD(x)            (((x)&0x0000007F)<<8)
-#define MCF_LCDC_LPCR_ACDSEL            (0x00008000)
-#define MCF_LCDC_LPCR_REV_VS            (0x00010000)
-#define MCF_LCDC_LPCR_SWAP_SEL          (0x00020000)
-#define MCF_LCDC_LPCR_ENDSEL            (0x00040000)
-#define MCF_LCDC_LPCR_SCLKIDLE          (0x00080000)
-#define MCF_LCDC_LPCR_OEPOL             (0x00100000)
-#define MCF_LCDC_LPCR_CLKPOL            (0x00200000)
-#define MCF_LCDC_LPCR_LPPOL             (0x00400000)
-#define MCF_LCDC_LPCR_FLM               (0x00800000)
-#define MCF_LCDC_LPCR_PIXPOL            (0x01000000)
-#define MCF_LCDC_LPCR_BPIX(x)           (((x)&0x00000007)<<25)
-#define MCF_LCDC_LPCR_PBSIZ(x)          (((x)&0x00000003)<<28)
-#define MCF_LCDC_LPCR_COLOR             (0x40000000)
-#define MCF_LCDC_LPCR_TFT               (0x80000000)
-#define MCF_LCDC_LPCR_MODE_MONOCGROME   (0x00000000)
-#define MCF_LCDC_LPCR_MODE_CSTN         (0x40000000)
-#define MCF_LCDC_LPCR_MODE_TFT          (0xC0000000)
-#define MCF_LCDC_LPCR_PBSIZ_1           (0x00000000)
-#define MCF_LCDC_LPCR_PBSIZ_2           (0x10000000)
-#define MCF_LCDC_LPCR_PBSIZ_4           (0x20000000)
-#define MCF_LCDC_LPCR_PBSIZ_8           (0x30000000)
-#define MCF_LCDC_LPCR_BPIX_1bpp         (0x00000000)
-#define MCF_LCDC_LPCR_BPIX_2bpp         (0x02000000)
-#define MCF_LCDC_LPCR_BPIX_4bpp         (0x04000000)
-#define MCF_LCDC_LPCR_BPIX_8bpp         (0x06000000)
-#define MCF_LCDC_LPCR_BPIX_12bpp        (0x08000000)
-#define MCF_LCDC_LPCR_BPIX_16bpp        (0x0A000000)
-#define MCF_LCDC_LPCR_BPIX_18bpp        (0x0C000000)
-
-#define MCF_LCDC_LPCR_PANEL_TYPE(x)     (((x)&0x00000003)<<30) 
-
-/* Bit definitions and macros for MCF_LCDC_LHCR */
-#define MCF_LCDC_LHCR_H_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LHCR_H_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LHCR_H_WIDTH(x)        (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LVCR */
-#define MCF_LCDC_LVCR_V_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LVCR_V_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LVCR_V_WIDTH(x)      (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LPOR */
-#define MCF_LCDC_LPOR_POS(x)            (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LPCCR */
-#define MCF_LCDC_LPCCR_PW(x)            (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LPCCR_CC_EN            (0x00000100)
-#define MCF_LCDC_LPCCR_SCR(x)           (((x)&0x00000003)<<9)
-#define MCF_LCDC_LPCCR_LDMSK            (0x00008000)
-#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x)  (((x)&0x000001FF)<<16)
-#define MCF_LCDC_LPCCR_SCR_LINEPULSE    (0x00000000)
-#define MCF_LCDC_LPCCR_SCR_PIXELCLK     (0x00002000)
-#define MCF_LCDC_LPCCR_SCR_LCDCLOCK     (0x00004000)
-
-/* Bit definitions and macros for MCF_LCDC_LDCR */
-#define MCF_LCDC_LDCR_TM(x)             (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LDCR_HM(x)             (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LDCR_BURST             (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LRMCR */
-#define MCF_LCDC_LRMCR_SEL_REF          (0x00000001)
-
-/* Bit definitions and macros for MCF_LCDC_LICR */
-#define MCF_LCDC_LICR_INTCON            (0x00000001)
-#define MCF_LCDC_LICR_INTSYN            (0x00000004)
-#define MCF_LCDC_LICR_GW_INT_CON        (0x00000010)
-
-/* Bit definitions and macros for MCF_LCDC_LIER */
-#define MCF_LCDC_LIER_BOF_EN            (0x00000001)
-#define MCF_LCDC_LIER_EOF_EN            (0x00000002)
-#define MCF_LCDC_LIER_ERR_RES_EN        (0x00000004)
-#define MCF_LCDC_LIER_UDR_ERR_EN        (0x00000008)
-#define MCF_LCDC_LIER_GW_BOF_EN         (0x00000010)
-#define MCF_LCDC_LIER_GW_EOF_EN         (0x00000020)
-#define MCF_LCDC_LIER_GW_ERR_RES_EN     (0x00000040)
-#define MCF_LCDC_LIER_GW_UDR_ERR_EN     (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LISR */
-#define MCF_LCDC_LISR_BOF               (0x00000001)
-#define MCF_LCDC_LISR_EOF               (0x00000002)
-#define MCF_LCDC_LISR_ERR_RES           (0x00000004)
-#define MCF_LCDC_LISR_UDR_ERR           (0x00000008)
-#define MCF_LCDC_LISR_GW_BOF            (0x00000010)
-#define MCF_LCDC_LISR_GW_EOF            (0x00000020)
-#define MCF_LCDC_LISR_GW_ERR_RES        (0x00000040)
-#define MCF_LCDC_LISR_GW_UDR_ERR        (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSAR */
-#define MCF_LCDC_LGWSAR_GWSA(x)         (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSR */
-#define MCF_LCDC_LGWSR_GWH(x)           (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWSR_GWW(x)           (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
-#define MCF_LCDC_LGWVPWR_GWVPW(x)       (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPOR */
-#define MCF_LCDC_LGWPOR_GWPO(x)         (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPR */
-#define MCF_LCDC_LGWPR_GWYP(x)          (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWPR_GWXP(x)          (((x)&0x000003FF)<<16)
-
-/* Bit definitions and macros for MCF_LCDC_LGWCR */
-#define MCF_LCDC_LGWCR_GWCKB(x)         (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LGWCR_GWCKG(x)         (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LGWCR_GWCKR(x)         (((x)&0x0000003F)<<12)
-#define MCF_LCDC_LGWCR_GW_RVS           (0x00200000)
-#define MCF_LCDC_LGWCR_GWE              (0x00400000)
-#define MCF_LCDC_LGWCR_GWCKE            (0x00800000)
-#define MCF_LCDC_LGWCR_GWAV(x)          (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_LCDC_LGWDCR */
-#define MCF_LCDC_LGWDCR_GWTM(x)         (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LGWDCR_GWHM(x)         (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LGWDCR_GWBT            (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LSCR */
-#define MCF_LCDC_LSCR_PS_RISE_DELAY(x)    (((x)&0x0000003F)<<26)
-#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x)   (((x)&0x000000FF)<<16)
-#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
-#define MCF_LCDC_LSCR_GRAY_2(x)                   (((x)&0x0000000F)<<4)
-#define MCF_LCDC_LSCR_GRAY_1(x)                   (((x)&0x0000000F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
-#define MCF_LCDC_BPLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
-#define MCF_LCDC_GWLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
-/*********************************************************************
- *
- * Phase Locked Loop (PLL)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_PLL_PODR              MCF_REG08(0xFC0C0000)
-#define MCF_PLL_PLLCR             MCF_REG08(0xFC0C0004)
-#define MCF_PLL_PMDR              MCF_REG08(0xFC0C0008)
-#define MCF_PLL_PFDR              MCF_REG08(0xFC0C000C)
-
-/* Bit definitions and macros for MCF_PLL_PODR */
-#define MCF_PLL_PODR_BUSDIV(x)    (((x)&0x0F)<<0)
-#define MCF_PLL_PODR_CPUDIV(x)    (((x)&0x0F)<<4)
-
-/* Bit definitions and macros for MCF_PLL_PLLCR */
-#define MCF_PLL_PLLCR_DITHDEV(x)  (((x)&0x07)<<0)
-#define MCF_PLL_PLLCR_DITHEN      (0x80)
-
-/* Bit definitions and macros for MCF_PLL_PMDR */
-#define MCF_PLL_PMDR_MODDIV(x)    (((x)&0xFF)<<0)
-
-/* Bit definitions and macros for MCF_PLL_PFDR */
-#define MCF_PLL_PFDR_MFD(x)       (((x)&0xFF)<<0)
-
-/*********************************************************************
- *
- * System Control Module Registers (SCM)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SCM_MPR                     MCF_REG32(0xFC000000)
-#define MCF_SCM_PACRA                   MCF_REG32(0xFC000020)
-#define MCF_SCM_PACRB                   MCF_REG32(0xFC000024)
-#define MCF_SCM_PACRC                   MCF_REG32(0xFC000028)
-#define MCF_SCM_PACRD                   MCF_REG32(0xFC00002C)
-#define MCF_SCM_PACRE                   MCF_REG32(0xFC000040)
-#define MCF_SCM_PACRF                   MCF_REG32(0xFC000044)
-
-#define MCF_SCM_BCR                     MCF_REG32(0xFC040024)
-
-/*********************************************************************
- *
- * SDRAM Controller (SDRAMC)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SDRAMC_SDMR                 MCF_REG32(0xFC0B8000)
-#define MCF_SDRAMC_SDCR                 MCF_REG32(0xFC0B8004)
-#define MCF_SDRAMC_SDCFG1               MCF_REG32(0xFC0B8008)
-#define MCF_SDRAMC_SDCFG2               MCF_REG32(0xFC0B800C)
-#define MCF_SDRAMC_LIMP_FIX             MCF_REG32(0xFC0B8080)
-#define MCF_SDRAMC_SDDS                 MCF_REG32(0xFC0B8100)
-#define MCF_SDRAMC_SDCS0                MCF_REG32(0xFC0B8110)
-#define MCF_SDRAMC_SDCS1                MCF_REG32(0xFC0B8114)
-#define MCF_SDRAMC_SDCS2                MCF_REG32(0xFC0B8118)
-#define MCF_SDRAMC_SDCS3                MCF_REG32(0xFC0B811C)
-#define MCF_SDRAMC_SDCS(x)              MCF_REG32(0xFC0B8110+((x)*0x004))
-
-/* Bit definitions and macros for MCF_SDRAMC_SDMR */
-#define MCF_SDRAMC_SDMR_CMD             (0x00010000)
-#define MCF_SDRAMC_SDMR_AD(x)           (((x)&0x00000FFF)<<18)
-#define MCF_SDRAMC_SDMR_BNKAD(x)        (((x)&0x00000003)<<30)
-#define MCF_SDRAMC_SDMR_BNKAD_LMR       (0x00000000)
-#define MCF_SDRAMC_SDMR_BNKAD_LEMR      (0x40000000)
-
-/* Bit definitions and macros for MCF_SDRAMC_SDCR */
-#define MCF_SDRAMC_SDCR_IPALL           (0x00000002)
-#define MCF_SDRAMC_SDCR_IREF            (0x00000004)
-#define MCF_SDRAMC_SDCR_DQS_OE(x)       (((x)&0x0000000F)<<8)
-#define MCF_SDRAMC_SDCR_PS(x)           (((x)&0x00000003)<<12)
-#define MCF_SDRAMC_SDCR_RCNT(x)         (((x)&0x0000003F)<<16)
-#define MCF_SDRAMC_SDCR_OE_RULE         (0x00400000)
-#define MCF_SDRAMC_SDCR_MUX(x)          (((x)&0x00000003)<<24)
-#define MCF_SDRAMC_SDCR_REF             (0x10000000)
-#define MCF_SDRAMC_SDCR_DDR             (0x20000000)
-#define MCF_SDRAMC_SDCR_CKE             (0x40000000)
-#define MCF_SDRAMC_SDCR_MODE_EN         (0x80000000)
-#define MCF_SDRAMC_SDCR_PS_16           (0x00002000)
-#define MCF_SDRAMC_SDCR_PS_32           (0x00000000)
-
-/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
-#define MCF_SDRAMC_SDCFG1_WTLAT(x)      (((x)&0x00000007)<<4)
-#define MCF_SDRAMC_SDCFG1_REF2ACT(x)    (((x)&0x0000000F)<<8)
-#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)    (((x)&0x00000007)<<12)
-#define MCF_SDRAMC_SDCFG1_ACT2RW(x)     (((x)&0x00000007)<<16)
-#define MCF_SDRAMC_SDCFG1_RDLAT(x)      (((x)&0x0000000F)<<20)
-#define MCF_SDRAMC_SDCFG1_SWT2RD(x)     (((x)&0x00000007)<<24)
-#define MCF_SDRAMC_SDCFG1_SRD2RW(x)     (((x)&0x0000000F)<<28)
-
-/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
-#define MCF_SDRAMC_SDCFG2_BL(x)         (((x)&0x0000000F)<<16)
-#define MCF_SDRAMC_SDCFG2_BRD2WT(x)     (((x)&0x0000000F)<<20)
-#define MCF_SDRAMC_SDCFG2_BWT2RW(x)     (((x)&0x0000000F)<<24)
-#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)    (((x)&0x0000000F)<<28)
-
-/* Device Errata - LIMP mode work around */
-#define MCF_SDRAMC_REFRESH              (0x40000000)
-
-/* Bit definitions and macros for MCF_SDRAMC_SDDS */
-#define MCF_SDRAMC_SDDS_SB_D(x)         (((x)&0x00000003)<<0)
-#define MCF_SDRAMC_SDDS_SB_S(x)         (((x)&0x00000003)<<2)
-#define MCF_SDRAMC_SDDS_SB_A(x)         (((x)&0x00000003)<<4)
-#define MCF_SDRAMC_SDDS_SB_C(x)         (((x)&0x00000003)<<6)
-#define MCF_SDRAMC_SDDS_SB_E(x)         (((x)&0x00000003)<<8)
-
-/* Bit definitions and macros for MCF_SDRAMC_SDCS */
-#define MCF_SDRAMC_SDCS_CSSZ(x)         (((x)&0x0000001F)<<0)
-#define MCF_SDRAMC_SDCS_BASE(x)         (((x)&0x00000FFF)<<20)
-#define MCF_SDRAMC_SDCS_BA(x)           ((x)&0xFFF00000)
-#define MCF_SDRAMC_SDCS_CSSZ_DIABLE     (0x00000000)
-#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE     (0x00000013)
-#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE     (0x00000014)
-#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE     (0x00000015)
-#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE     (0x00000016)
-#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE    (0x00000017)
-#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE    (0x00000018)
-#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE    (0x00000019)
-#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE   (0x0000001A)
-#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE   (0x0000001B)
-#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE   (0x0000001C)
-#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE     (0x0000001D)
-#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE     (0x0000001E)
-#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE     (0x0000001F)
-
-/*********************************************************************
- *
- *      FlexCAN module registers
- *
- *********************************************************************/
-#define MCF_FLEXCAN_BASEADDR(x)         (0xFC020000+(x)*0x0800)
-#define MCF_FLEXCAN_CANMCR(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x00)
-#define MCF_FLEXCAN_CANCTRL(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x04)
-#define MCF_FLEXCAN_TIMER(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x08)
-#define MCF_FLEXCAN_RXGMASK(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x10)
-#define MCF_FLEXCAN_RX14MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x14)
-#define MCF_FLEXCAN_RX15MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x18)
-#define MCF_FLEXCAN_ERRCNT(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
-#define MCF_FLEXCAN_ERRSTAT(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x20)
-#define MCF_FLEXCAN_IMASK(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x28)
-#define MCF_FLEXCAN_IFLAG(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x30)
-
-#define MCF_FLEXCAN_MB_CNT(x,y)         MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
-#define MCF_FLEXCAN_MB_ID(x,y)          MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
-#define MCF_FLEXCAN_MB_DB(x,y,z)        MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
-
-/*
- *      FlexCAN Module Configuration Register
- */
-#define CANMCR_MDIS             (0x80000000)
-#define CANMCR_FRZ              (0x40000000)
-#define CANMCR_HALT             (0x10000000)
-#define CANMCR_SOFTRST          (0x02000000)
-#define CANMCR_FRZACK           (0x01000000)
-#define CANMCR_SUPV             (0x00800000)
-#define CANMCR_MAXMB(x)         ((x)&0x0F)
-
-/*
- *      FlexCAN Control Register
- */
-#define CANCTRL_PRESDIV(x)      (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x)          (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x)        (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x)        (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK         (0x00008000)
-#define CANCTRL_ERRMSK          (0x00004000)
-#define CANCTRL_CLKSRC          (0x00002000)
-#define CANCTRL_LPB             (0x00001000)
-#define CANCTRL_SAMP            (0x00000080)
-#define CANCTRL_BOFFREC         (0x00000040)
-#define CANCTRL_TSYNC           (0x00000020)
-#define CANCTRL_LBUF            (0x00000010)
-#define CANCTRL_LOM             (0x00000008)
-#define CANCTRL_PROPSEG(x)      ((x)&0x07)
-
-/*
- *      FlexCAN Error Counter Register
- */
-#define ERRCNT_RXECTR(x)        (((x)&0xFF)<<8)
-#define ERRCNT_TXECTR(x)        ((x)&0xFF)
-
-/*
- *      FlexCAN Error and Status Register
- */
-#define ERRSTAT_BITERR(x)       (((x)&0x03)<<14)
-#define ERRSTAT_ACKERR           (0x00002000)
-#define ERRSTAT_CRCERR           (0x00001000)
-#define ERRSTAT_FRMERR           (0x00000800)
-#define ERRSTAT_STFERR           (0x00000400)
-#define ERRSTAT_TXWRN            (0x00000200)
-#define ERRSTAT_RXWRN            (0x00000100)
-#define ERRSTAT_IDLE             (0x00000080)
-#define ERRSTAT_TXRX             (0x00000040)
-#define ERRSTAT_FLTCONF(x)       (((x)&0x03)<<4)
-#define ERRSTAT_BOFFINT          (0x00000004)
-#define ERRSTAT_ERRINT           (0x00000002)
-
-/*
- *      Interrupt Mask Register
- */
-#define IMASK_BUF15M            (0x8000)
-#define IMASK_BUF14M            (0x4000)
-#define IMASK_BUF13M            (0x2000)
-#define IMASK_BUF12M            (0x1000)
-#define IMASK_BUF11M            (0x0800)
-#define IMASK_BUF10M            (0x0400)
-#define IMASK_BUF9M             (0x0200)
-#define IMASK_BUF8M             (0x0100)
-#define IMASK_BUF7M             (0x0080)
-#define IMASK_BUF6M             (0x0040)
-#define IMASK_BUF5M             (0x0020)
-#define IMASK_BUF4M             (0x0010)
-#define IMASK_BUF3M             (0x0008)
-#define IMASK_BUF2M             (0x0004)
-#define IMASK_BUF1M             (0x0002)
-#define IMASK_BUF0M             (0x0001)
-#define IMASK_BUFnM(x)          (0x1<<(x))
-#define IMASK_BUFF_ENABLE_ALL   (0x1111)
-#define IMASK_BUFF_DISABLE_ALL  (0x0000)
-
-/*
- *      Interrupt Flag Register
- */
-#define IFLAG_BUF15M            (0x8000)
-#define IFLAG_BUF14M            (0x4000)
-#define IFLAG_BUF13M            (0x2000)
-#define IFLAG_BUF12M            (0x1000)
-#define IFLAG_BUF11M            (0x0800)
-#define IFLAG_BUF10M            (0x0400)
-#define IFLAG_BUF9M             (0x0200)
-#define IFLAG_BUF8M             (0x0100)
-#define IFLAG_BUF7M             (0x0080)
-#define IFLAG_BUF6M             (0x0040)
-#define IFLAG_BUF5M             (0x0020)
-#define IFLAG_BUF4M             (0x0010)
-#define IFLAG_BUF3M             (0x0008)
-#define IFLAG_BUF2M             (0x0004)
-#define IFLAG_BUF1M             (0x0002)
-#define IFLAG_BUF0M             (0x0001)
-#define IFLAG_BUFF_SET_ALL      (0xFFFF)
-#define IFLAG_BUFF_CLEAR_ALL    (0x0000)
-#define IFLAG_BUFnM(x)          (0x1<<(x))
-
-/*
- *      Message Buffers
- */
-#define MB_CNT_CODE(x)          (((x)&0x0F)<<24)
-#define MB_CNT_SRR              (0x00400000)
-#define MB_CNT_IDE              (0x00200000)
-#define MB_CNT_RTR              (0x00100000)
-#define MB_CNT_LENGTH(x)        (((x)&0x0F)<<16)
-#define MB_CNT_TIMESTAMP(x)     ((x)&0xFFFF)
-#define MB_ID_STD(x)            (((x)&0x07FF)<<18)
-#define MB_ID_EXT(x)            ((x)&0x3FFFF)
-
-/*********************************************************************
- *
- * Edge Port Module (EPORT)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_EPORT_EPPAR                MCF_REG16(0xFC094000)
-#define MCF_EPORT_EPDDR                MCF_REG08(0xFC094002)
-#define MCF_EPORT_EPIER                MCF_REG08(0xFC094003)
-#define MCF_EPORT_EPDR                 MCF_REG08(0xFC094004)
-#define MCF_EPORT_EPPDR                MCF_REG08(0xFC094005)
-#define MCF_EPORT_EPFR                 MCF_REG08(0xFC094006)
-
-/* Bit definitions and macros for MCF_EPORT_EPPAR */
-#define MCF_EPORT_EPPAR_EPPA1(x)       (((x)&0x0003)<<2)
-#define MCF_EPORT_EPPAR_EPPA2(x)       (((x)&0x0003)<<4)
-#define MCF_EPORT_EPPAR_EPPA3(x)       (((x)&0x0003)<<6)
-#define MCF_EPORT_EPPAR_EPPA4(x)       (((x)&0x0003)<<8)
-#define MCF_EPORT_EPPAR_EPPA5(x)       (((x)&0x0003)<<10)
-#define MCF_EPORT_EPPAR_EPPA6(x)       (((x)&0x0003)<<12)
-#define MCF_EPORT_EPPAR_EPPA7(x)       (((x)&0x0003)<<14)
-#define MCF_EPORT_EPPAR_LEVEL          (0)
-#define MCF_EPORT_EPPAR_RISING         (1)
-#define MCF_EPORT_EPPAR_FALLING        (2)
-#define MCF_EPORT_EPPAR_BOTH           (3)
-#define MCF_EPORT_EPPAR_EPPA7_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA7_RISING   (0x4000)
-#define MCF_EPORT_EPPAR_EPPA7_FALLING  (0x8000)
-#define MCF_EPORT_EPPAR_EPPA7_BOTH     (0xC000)
-#define MCF_EPORT_EPPAR_EPPA6_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA6_RISING   (0x1000)
-#define MCF_EPORT_EPPAR_EPPA6_FALLING  (0x2000)
-#define MCF_EPORT_EPPAR_EPPA6_BOTH     (0x3000)
-#define MCF_EPORT_EPPAR_EPPA5_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA5_RISING   (0x0400)
-#define MCF_EPORT_EPPAR_EPPA5_FALLING  (0x0800)
-#define MCF_EPORT_EPPAR_EPPA5_BOTH     (0x0C00)
-#define MCF_EPORT_EPPAR_EPPA4_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA4_RISING   (0x0100)
-#define MCF_EPORT_EPPAR_EPPA4_FALLING  (0x0200)
-#define MCF_EPORT_EPPAR_EPPA4_BOTH     (0x0300)
-#define MCF_EPORT_EPPAR_EPPA3_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA3_RISING   (0x0040)
-#define MCF_EPORT_EPPAR_EPPA3_FALLING  (0x0080)
-#define MCF_EPORT_EPPAR_EPPA3_BOTH     (0x00C0)
-#define MCF_EPORT_EPPAR_EPPA2_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA2_RISING   (0x0010)
-#define MCF_EPORT_EPPAR_EPPA2_FALLING  (0x0020)
-#define MCF_EPORT_EPPAR_EPPA2_BOTH     (0x0030)
-#define MCF_EPORT_EPPAR_EPPA1_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA1_RISING   (0x0004)
-#define MCF_EPORT_EPPAR_EPPA1_FALLING  (0x0008)
-#define MCF_EPORT_EPPAR_EPPA1_BOTH     (0x000C)
-
-/* Bit definitions and macros for MCF_EPORT_EPDDR */
-#define MCF_EPORT_EPDDR_EPDD1          (0x02)
-#define MCF_EPORT_EPDDR_EPDD2          (0x04)
-#define MCF_EPORT_EPDDR_EPDD3          (0x08)
-#define MCF_EPORT_EPDDR_EPDD4          (0x10)
-#define MCF_EPORT_EPDDR_EPDD5          (0x20)
-#define MCF_EPORT_EPDDR_EPDD6          (0x40)
-#define MCF_EPORT_EPDDR_EPDD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPIER */
-#define MCF_EPORT_EPIER_EPIE1          (0x02)
-#define MCF_EPORT_EPIER_EPIE2          (0x04)
-#define MCF_EPORT_EPIER_EPIE3          (0x08)
-#define MCF_EPORT_EPIER_EPIE4          (0x10)
-#define MCF_EPORT_EPIER_EPIE5          (0x20)
-#define MCF_EPORT_EPIER_EPIE6          (0x40)
-#define MCF_EPORT_EPIER_EPIE7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPDR */
-#define MCF_EPORT_EPDR_EPD1            (0x02)
-#define MCF_EPORT_EPDR_EPD2            (0x04)
-#define MCF_EPORT_EPDR_EPD3            (0x08)
-#define MCF_EPORT_EPDR_EPD4            (0x10)
-#define MCF_EPORT_EPDR_EPD5            (0x20)
-#define MCF_EPORT_EPDR_EPD6            (0x40)
-#define MCF_EPORT_EPDR_EPD7            (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPPDR */
-#define MCF_EPORT_EPPDR_EPPD1          (0x02)
-#define MCF_EPORT_EPPDR_EPPD2          (0x04)
-#define MCF_EPORT_EPPDR_EPPD3          (0x08)
-#define MCF_EPORT_EPPDR_EPPD4          (0x10)
-#define MCF_EPORT_EPPDR_EPPD5          (0x20)
-#define MCF_EPORT_EPPDR_EPPD6          (0x40)
-#define MCF_EPORT_EPPDR_EPPD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPFR */
-#define MCF_EPORT_EPFR_EPF1            (0x02)
-#define MCF_EPORT_EPFR_EPF2            (0x04)
-#define MCF_EPORT_EPFR_EPF3            (0x08)
-#define MCF_EPORT_EPFR_EPF4            (0x10)
-#define MCF_EPORT_EPFR_EPF5            (0x20)
-#define MCF_EPORT_EPFR_EPF6            (0x40)
-#define MCF_EPORT_EPFR_EPF7            (0x80)
-
-/********************************************************************/
-#endif  /* m532xsim_h */
diff --git a/arch/m68knommu/include/asm/m5407sim.h b/arch/m68knommu/include/asm/m5407sim.h
deleted file mode 100644
index cc22c4a53005..000000000000
--- a/arch/m68knommu/include/asm/m5407sim.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/****************************************************************************/
-
-/*
- *      m5407sim.h -- ColdFire 5407 System Integration Module support.
- *
- *      (C) Copyright 2000,  Lineo (www.lineo.com)
- *      (C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
- *
- *      Modified by David W. Miller for the MCF5307 Eval Board.
- */
-
-/****************************************************************************/
-#ifndef m5407sim_h
-#define m5407sim_h
-/****************************************************************************/
-
-/*
- *      Define the 5407 SIM register set addresses.
- */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Controll Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
-
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
-
-#define MCFSIM_PADDR            0x244           /* Parallel Direction (r/w) */
-#define MCFSIM_PADAT            0x248           /* Parallel Data (r/w) */
-
-
-/*
- *      Some symbol defines for the above...
- */
-#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
-#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
-#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
-#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
-#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
-#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
-#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
-#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
-#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
-
-/*
- *      Macro to set IMR register. It is 32 bits on the 5407.
- */
-#define mcf_getimr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
-
-#define mcf_setimr(imr)         \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
-
-#define mcf_getipr()            \
-        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
-
-
-/*
- *      Some symbol defines for the Parallel Port Pin Assignment Register
- */
-#define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
-                                                /* Clear to select par I/O */
-#define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
-                                                /* Clear to select par I/O */
-
-/*
- *       Defines for the IRQPAR Register
- */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
-
-
-/*
- *      Define the Cache register flags.
- */
-#define CACR_DEC                0x80000000      /* Enable data cache */
-#define CACR_DWP                0x40000000      /* Data write protection */
-#define CACR_DESB               0x20000000      /* Enable data store buffer */
-#define CACR_DDPI               0x10000000      /* Disable CPUSHL */
-#define CACR_DHCLK              0x08000000      /* Half data cache lock mode */
-#define CACR_DDCM_WT            0x00000000      /* Write through cache*/
-#define CACR_DDCM_CP            0x02000000      /* Copyback cache */
-#define CACR_DDCM_P             0x04000000      /* No cache, precise */
-#define CACR_DDCM_IMP           0x06000000      /* No cache, imprecise */
-#define CACR_DCINVA             0x01000000      /* Invalidate data cache */
-#define CACR_BEC                0x00080000      /* Enable branch cache */
-#define CACR_BCINVA             0x00040000      /* Invalidate branch cache */
-#define CACR_IEC                0x00008000      /* Enable instruction cache */
-#define CACR_DNFB               0x00002000      /* Inhibited fill buffer */
-#define CACR_IDPI               0x00001000      /* Disable CPUSHL */
-#define CACR_IHLCK              0x00000800      /* Intruction cache half lock */
-#define CACR_IDCM               0x00000400      /* Intruction cache inhibit */
-#define CACR_ICINVA             0x00000100      /* Invalidate instr cache */
-
-#define ACR_BASE_POS            24              /* Address Base */
-#define ACR_MASK_POS            16              /* Address Mask */
-#define ACR_ENABLE              0x00008000      /* Enable address */
-#define ACR_USER                0x00000000      /* User mode access only */
-#define ACR_SUPER               0x00002000      /* Supervisor mode only */
-#define ACR_ANY                 0x00004000      /* Match any access mode */
-#define ACR_CM_WT               0x00000000      /* Write through mode */
-#define ACR_CM_CP               0x00000020      /* Copyback mode */
-#define ACR_CM_OFF_PRE          0x00000040      /* No cache, precise */
-#define ACR_CM_OFF_IMP          0x00000060      /* No cache, imprecise */
-#define ACR_WPROTECT            0x00000004      /* Write protect */
-
-/****************************************************************************/
-#endif  /* m5407sim_h */
diff --git a/arch/m68knommu/include/asm/m68360.h b/arch/m68knommu/include/asm/m68360.h
deleted file mode 100644
index eb7d39ef2855..000000000000
--- a/arch/m68knommu/include/asm/m68360.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#include "m68360_regs.h"
-#include "m68360_pram.h"
-#include "m68360_quicc.h"
-#include "m68360_enet.h"
-
-#ifdef CONFIG_M68360
-
-#define CPM_INTERRUPT    4
-
-/* see MC68360 User's Manual, p. 7-377  */
-#define CPM_VECTOR_BASE  0x04           /* 3 MSbits of CPM vector */
-
-#endif /* CONFIG_M68360 */
diff --git a/arch/m68knommu/include/asm/m68360_enet.h b/arch/m68knommu/include/asm/m68360_enet.h
deleted file mode 100644
index c36f4d059203..000000000000
--- a/arch/m68knommu/include/asm/m68360_enet.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/***********************************
- * $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
- ***********************************
- *
- ***************************************
- * Definitions for the ETHERNET controllers
- ***************************************
- */
-
-#ifndef __ETHER_H
-#define __ETHER_H
-
-#include "quicc_simple.h"
-
-/*
- * transmit BD's
- */
-#define T_R     0x8000          /* ready bit */
-#define E_T_PAD 0x4000          /* short frame padding */
-#define T_W     0x2000          /* wrap bit */
-#define T_I     0x1000          /* interrupt on completion */
-#define T_L     0x0800          /* last in frame */
-#define T_TC    0x0400          /* transmit CRC (when last) */
-
-#define T_DEF   0x0200          /* defer indication */
-#define T_HB    0x0100          /* heartbeat */
-#define T_LC    0x0080          /* error: late collision */
-#define T_RL    0x0040          /* error: retransmission limit */
-#define T_RC    0x003c          /* retry count */
-#define T_UN    0x0002          /* error: underrun */
-#define T_CSL   0x0001          /* carier sense lost */
-#define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL)
-
-/*
- * receive BD's
- */
-#define R_E     0x8000          /* buffer empty */
-#define R_W     0x2000          /* wrap bit */
-#define R_I     0x1000          /* interrupt on reception */
-#define R_L     0x0800          /* last BD in frame */
-#define R_F     0x0400          /* first BD in frame */
-#define R_M     0x0100          /* received because of promisc. mode */
-
-#define R_LG    0x0020          /* frame too long */
-#define R_NO    0x0010          /* non-octet aligned */
-#define R_SH    0x0008          /* short frame */
-#define R_CR    0x0004          /* receive CRC error */
-#define R_OV    0x0002          /* receive overrun */
-#define R_CL    0x0001          /* collision */
-#define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL)
-
-
-/*
- * ethernet interrupts
- */
-#define ETHERNET_GRA    0x0080  /* graceful stop complete */
-#define ETHERNET_TXE    0x0010  /* transmit error         */
-#define ETHERNET_RXF    0x0008  /* receive frame          */
-#define ETHERNET_BSY    0x0004  /* busy condition         */
-#define ETHERNET_TXB    0x0002  /* transmit buffer        */
-#define ETHERNET_RXB    0x0001  /* receive buffer         */
-
-/*
- * ethernet protocol specific mode register (PSMR)
- */
-#define ETHER_HBC       0x8000    /* heartbeat checking      */
-#define ETHER_FC        0x4000    /* force collision         */
-#define ETHER_RSH       0x2000    /* receive short frames    */
-#define ETHER_IAM       0x1000    /* individual address mode */
-#define ETHER_CRC_32    (0x2<<10) /* Enable CRC              */
-#define ETHER_PRO       0x0200    /* promiscuous             */
-#define ETHER_BRO       0x0100    /* broadcast address       */
-#define ETHER_SBT       0x0080    /* stop backoff timer      */
-#define ETHER_LPB       0x0040    /* Loop Back Mode          */
-#define ETHER_SIP       0x0020    /* sample input pins       */
-#define ETHER_LCW       0x0010    /* late collision window   */
-#define ETHER_NIB_13    (0x0<<1)  /* # of ignored bits 13    */
-#define ETHER_NIB_14    (0x1<<1)  /* # of ignored bits 14    */
-#define ETHER_NIB_15    (0x2<<1)  /* # of ignored bits 15    */
-#define ETHER_NIB_16    (0x3<<1)  /* # of ignored bits 16    */
-#define ETHER_NIB_21    (0x4<<1)  /* # of ignored bits 21    */
-#define ETHER_NIB_22    (0x5<<1)  /* # of ignored bits 22    */
-#define ETHER_NIB_23    (0x6<<1)  /* # of ignored bits 23    */
-#define ETHER_NIB_24    (0x7<<1)  /* # of ignored bits 24    */
-
-/*
- * ethernet specific parameters
- */
-#define CRC_WORD 4          /* Length in bytes of CRC */               
-#define C_PRES   0xffffffff /* preform 32 bit CRC */
-#define C_MASK   0xdebb20e3 /* comply with 32 bit CRC */       
-#define CRCEC    0x00000000
-#define ALEC     0x00000000
-#define DISFC    0x00000000
-#define PADS     0x00000000
-#define RET_LIM  0x000f     /* retry 15 times to send a frame before interrupt */
-#define ETH_MFLR 0x05ee     /* 1518 max frame size */
-#define MINFLR   0x0040     /* Minimum frame size 64 */
-#define MAXD1    0x05ee     /* Max dma count 1518 */
-#define MAXD2    0x05ee
-#define GADDR1   0x00000000 /* Clear group address */  
-#define GADDR2   0x00000000
-#define GADDR3   0x00000000    
-#define GADDR4   0x00000000    
-#define P_PER    0x00000000 /*not used */              
-#define IADDR1   0x00000000 /* Individual hash table not used */       
-#define IADDR2   0x00000000
-#define IADDR3   0x00000000    
-#define IADDR4   0x00000000            
-#define TADDR_H  0x00000000 /* clear this regs */              
-#define TADDR_M  0x00000000            
-#define TADDR_L  0x00000000            
-
-/*       SCC Parameter Ram */
-#define RFCR    0x18 /* normal operation */
-#define TFCR    0x18 /* normal operation */
-#define E_MRBLR 1518 /* Max ethernet frame length */
-
-/*
- * ethernet specific structure
- */
-typedef union {
-        unsigned char b[6];
-        struct {
-            unsigned short high;
-            unsigned short middl;
-            unsigned short low;
-        } w;
-} ETHER_ADDR;
-
-typedef struct {
-    int        max_frame_length;
-    int        promisc_mode;
-    int        reject_broadcast;
-    ETHER_ADDR phys_adr;
-} ETHER_SPECIFIC;
-
-typedef struct {
-    ETHER_ADDR     dst_addr;
-    ETHER_ADDR     src_addr;
-    unsigned short type_or_len;
-    unsigned char  data[1];
-} ETHER_FRAME;
-
-#define MAX_DATALEN 1500
-typedef struct {
-    ETHER_ADDR     dst_addr;
-    ETHER_ADDR     src_addr;
-    unsigned short type_or_len;
-    unsigned char  data[MAX_DATALEN];
-    unsigned char  fcs[CRC_WORD];
-} ETHER_MAX_FRAME;
-
-
-/*
- * Internal ethernet function prototypes
- */
-void        ether_interrupt(int scc_num);
-/* mleslie: debug */
-/* static void ethernet_rx_internal(int scc_num); */
-/* static void ethernet_tx_internal(int scc_num); */
-
-/*
- * User callable routines prototypes (ethernet specific)
- */
-void ethernet_init(int                       scc_number,
-                   alloc_routine             *alloc_buffer,
-                   free_routine              *free_buffer,
-                   store_rx_buffer_routine   *store_rx_buffer,
-                   handle_tx_error_routine   *handle_tx_error,
-                   handle_rx_error_routine   *handle_rx_error,
-                   handle_lost_error_routine *handle_lost_error,
-                   ETHER_SPECIFIC            *ether_spec);
-int  ethernet_tx(int scc_number, void *buf, int length);
-
-#endif
-
diff --git a/arch/m68knommu/include/asm/m68360_pram.h b/arch/m68knommu/include/asm/m68360_pram.h
deleted file mode 100644
index e6088bbce93d..000000000000
--- a/arch/m68knommu/include/asm/m68360_pram.h
+++ /dev/null
@@ -1,431 +0,0 @@
-/***********************************
- * $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
- ***********************************
- *
- ***************************************
- * Definitions of the parameter area RAM.
- * Note that different structures are overlaid
- * at the same offsets for the different modes
- * of operation.
- ***************************************
- */
-
-#ifndef __PRAM_H
-#define __PRAM_H
-
-/* Time slot assignment table */
-#define VALID_SLOT      0x8000
-#define WRAP_SLOT       0x4000
-
-/*****************************************************************
-        Global Multichannel parameter RAM
-*****************************************************************/
-struct global_multi_pram {
-    /*
-     * Global Multichannel parameter RAM
-     */
-    unsigned long   mcbase;             /* Multichannel Base pointer */
-    unsigned short  qmcstate;           /* Multichannel Controller state */
-    unsigned short  mrblr;              /* Maximum Receive Buffer Length */
-    unsigned short  tx_s_ptr;           /* TSTATx Pointer */
-    unsigned short  rxptr;              /* Current Time slot entry in TSATRx */
-    unsigned short  grfthr;             /* Global Receive frame threshold */
-    unsigned short  grfcnt;             /* Global Receive Frame Count */
-    unsigned long   intbase;            /* Multichannel Base address */
-    unsigned long   iintptr;            /* Pointer to interrupt queue */
-    unsigned short  rx_s_ptr;           /* TSTARx Pointer */
-
-    unsigned short  txptr;              /* Current Time slot entry in TSATTx */
-    unsigned long   c_mask32;           /* CRC Constant (debb20e3) */
-    unsigned short  tsatrx[32];         /* Time Slot Assignment Table Rx */
-    unsigned short  tsattx[32];         /* Time Slot Assignment Table Tx */
-    unsigned short  c_mask16;           /* CRC Constant (f0b8) */
-};
-
-/*****************************************************************
-        Quicc32 HDLC parameter RAM
-*****************************************************************/
-struct quicc32_pram {
-
-    unsigned short  tbase;              /* Tx Buffer Descriptors Base Address */
-    unsigned short  chamr;              /* Channel Mode Register */
-    unsigned long   tstate;             /* Tx Internal State */
-    unsigned long   txintr;             /* Tx Internal Data Pointer */
-    unsigned short  tbptr;              /* Tx Buffer Descriptor Pointer */
-    unsigned short  txcntr;             /* Tx Internal Byte Count */
-    unsigned long   tupack;             /* (Tx Temp) */
-    unsigned long   zistate;            /* Zero Insertion machine state */
-    unsigned long   tcrc;               /* Temp Transmit CRC */
-    unsigned short  intmask;            /* Channel's interrupt mask flags */
-    unsigned short  bdflags;            
-    unsigned short  rbase;              /* Rx Buffer Descriptors Base Address */
-    unsigned short  mflr;               /* Max Frame Length Register */
-    unsigned long   rstate;             /* Rx Internal State */
-    unsigned long   rxintr;             /* Rx Internal Data Pointer */
-    unsigned short  rbptr;              /* Rx Buffer Descriptor Pointer */
-    unsigned short  rxbyc;              /* Rx Internal Byte Count */
-    unsigned long   rpack;              /* (Rx Temp) */
-    unsigned long   zdstate;            /* Zero Deletion machine state */
-    unsigned long   rcrc;               /* Temp Transmit CRC */
-    unsigned short  maxc;               /* Max_length counter */
-    unsigned short  tmp_mb;             /* Temp */
-};
-
-
-/*****************************************************************
-        HDLC parameter RAM
-*****************************************************************/
-
-struct hdlc_pram {
-    /*
-     * SCC parameter RAM
-     */
-    unsigned short  rbase;          /* RX BD base address */
-    unsigned short  tbase;          /* TX BD base address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rtemp;          /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-    unsigned long   rcrc;           /* temp receive CRC */
-    unsigned long   tcrc;           /* temp transmit CRC */
-   
-    /*
-     * HDLC specific parameter RAM
-     */
-    unsigned char   RESERVED1[4];   /* Reserved area */
-    unsigned long   c_mask;         /* CRC constant */
-    unsigned long   c_pres;         /* CRC preset */
-    unsigned short  disfc;          /* discarded frame counter */
-    unsigned short  crcec;          /* CRC error counter */
-    unsigned short  abtsc;          /* abort sequence counter */
-    unsigned short  nmarc;          /* nonmatching address rx cnt */
-    unsigned short  retrc;          /* frame retransmission cnt */
-    unsigned short  mflr;           /* maximum frame length reg */
-    unsigned short  max_cnt;        /* maximum length counter */
-    unsigned short  rfthr;          /* received frames threshold */
-    unsigned short  rfcnt;          /* received frames count */
-    unsigned short  hmask;          /* user defined frm addr mask */
-    unsigned short  haddr1;         /* user defined frm address 1 */
-    unsigned short  haddr2;         /* user defined frm address 2 */
-    unsigned short  haddr3;         /* user defined frm address 3 */
-    unsigned short  haddr4;         /* user defined frm address 4 */
-    unsigned short  tmp;            /* temp */
-    unsigned short  tmp_mb;         /* temp */
-};
-
-
-
-/*****************************************************************
-        UART parameter RAM
-*****************************************************************/
-
-/*
- * bits in uart control characters table
- */
-#define CC_INVALID  0x8000          /* control character is valid */
-#define CC_REJ      0x4000          /* don't store char in buffer */
-#define CC_CHAR     0x00ff          /* control character */
-
-/* UART */
-struct uart_pram {
-    /*
-     * SCC parameter RAM
-     */
-    unsigned short  rbase;          /* RX BD base address */
-    unsigned short  tbase;          /* TX BD base address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rx_temp;        /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-    unsigned long   rcrc;           /* temp receive CRC */
-    unsigned long   tcrc;           /* temp transmit CRC */
-   
-    /*
-     * UART specific parameter RAM
-     */
-    unsigned char   RESERVED1[8];   /* Reserved area */
-    unsigned short  max_idl;        /* maximum idle characters */
-    unsigned short  idlc;           /* rx idle counter (internal) */
-    unsigned short  brkcr;          /* break count register */
-                   
-    unsigned short  parec;          /* Rx parity error counter */
-    unsigned short  frmer;          /* Rx framing error counter */
-    unsigned short  nosec;          /* Rx noise counter */
-    unsigned short  brkec;          /* Rx break character counter */
-    unsigned short  brkln;          /* Reaceive break length */
-                   
-    unsigned short  uaddr1;         /* address character 1 */
-    unsigned short  uaddr2;         /* address character 2 */
-    unsigned short  rtemp;          /* temp storage */
-    unsigned short  toseq;          /* Tx out of sequence char */
-    unsigned short  cc[8];          /* Rx control characters */
-    unsigned short  rccm;           /* Rx control char mask */
-    unsigned short  rccr;           /* Rx control char register */
-    unsigned short  rlbc;           /* Receive last break char */
-};
-
-
-
-/*****************************************************************
-        BISYNC parameter RAM
-*****************************************************************/
-
-struct bisync_pram {
-    /*
-     * SCC parameter RAM
-     */
-    unsigned short  rbase;          /* RX BD base address */
-    unsigned short  tbase;          /* TX BD base address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rtemp;          /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-    unsigned long   rcrc;           /* temp receive CRC */
-    unsigned long   tcrc;           /* temp transmit CRC */
-   
-    /*
-     * BISYNC specific parameter RAM
-     */
-    unsigned char   RESERVED1[4];   /* Reserved area */
-    unsigned long   crcc;           /* CRC Constant Temp Value */
-    unsigned short  prcrc;          /* Preset Receiver CRC-16/LRC */
-    unsigned short  ptcrc;          /* Preset Transmitter CRC-16/LRC */
-    unsigned short  parec;          /* Receive Parity Error Counter */
-    unsigned short  bsync;          /* BISYNC SYNC Character */
-    unsigned short  bdle;           /* BISYNC DLE Character */
-    unsigned short  cc[8];          /* Rx control characters */
-    unsigned short  rccm;           /* Receive Control Character Mask */
-};
-
-/*****************************************************************
-        IOM2 parameter RAM
-        (overlaid on tx bd[5] of SCC channel[2])
-*****************************************************************/
-struct iom2_pram {
-    unsigned short  ci_data;        /* ci data */
-    unsigned short  monitor_data;   /* monitor data */
-    unsigned short  tstate;         /* transmitter state */
-    unsigned short  rstate;         /* receiver state */
-};
-
-/*****************************************************************
-        SPI/SMC parameter RAM
-        (overlaid on tx bd[6,7] of SCC channel[2])
-*****************************************************************/
-
-#define SPI_R       0x8000          /* Ready bit in BD */
-
-struct spi_pram {
-    unsigned short  rbase;          /* Rx BD Base Address */
-    unsigned short  tbase;          /* Tx BD Base Address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rtemp;          /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-};
-
-struct smc_uart_pram {
-    unsigned short  rbase;          /* Rx BD Base Address */
-    unsigned short  tbase;          /* Tx BD Base Address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rtemp;          /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-    unsigned short  max_idl;        /* Maximum IDLE Characters */
-    unsigned short  idlc;           /* Temporary IDLE Counter */
-    unsigned short  brkln;          /* Last Rx Break Length */
-    unsigned short  brkec;          /* Rx Break Condition Counter */
-    unsigned short  brkcr;          /* Break Count Register (Tx) */
-    unsigned short  r_mask;         /* Temporary bit mask */
-};
-
-struct smc_trnsp_pram {
-    unsigned short  rbase;          /* rx BD Base Address */
-    unsigned short  tbase;          /* Tx BD Base Address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rtemp;          /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-    unsigned short  reserved[5];    /* Reserved */
-};
-
-struct idma_pram {
-    unsigned short  ibase;          /* IDMA BD Base Address */
-    unsigned short  ibptr;          /* IDMA buffer descriptor pointer */
-    unsigned long   istate;         /* IDMA internal state */
-    unsigned long   itemp;          /* IDMA temp */
-};
-
-struct ethernet_pram {
-    /*
-     * SCC parameter RAM
-     */
-    unsigned short  rbase;          /* RX BD base address */
-    unsigned short  tbase;          /* TX BD base address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rtemp;          /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-    unsigned long   rcrc;           /* temp receive CRC */
-    unsigned long   tcrc;           /* temp transmit CRC */
-   
-    /*
-     * ETHERNET specific parameter RAM
-     */
-    unsigned long   c_pres;         /* preset CRC */
-    unsigned long   c_mask;         /* constant mask for CRC */
-    unsigned long   crcec;          /* CRC error counter */
-    unsigned long   alec;           /* alighnment error counter */
-    unsigned long   disfc;          /* discard frame counter */
-    unsigned short  pads;           /* short frame PAD characters */
-    unsigned short  ret_lim;        /* retry limit threshold */
-    unsigned short  ret_cnt;        /* retry limit counter */
-    unsigned short  mflr;           /* maximum frame length reg */
-    unsigned short  minflr;         /* minimum frame length reg */
-    unsigned short  maxd1;          /* maximum DMA1 length reg */
-    unsigned short  maxd2;          /* maximum DMA2 length reg */
-    unsigned short  maxd;           /* rx max DMA */
-    unsigned short  dma_cnt;        /* rx dma counter */
-    unsigned short  max_b;          /* max bd byte count */
-    unsigned short  gaddr1;         /* group address filter 1 */
-    unsigned short  gaddr2;         /* group address filter 2 */
-    unsigned short  gaddr3;         /* group address filter 3 */
-    unsigned short  gaddr4;         /* group address filter 4 */
-    unsigned long   tbuf0_data0;    /* save area 0 - current frm */
-    unsigned long   tbuf0_data1;    /* save area 1 - current frm */
-    unsigned long   tbuf0_rba0;
-    unsigned long   tbuf0_crc;
-    unsigned short  tbuf0_bcnt;
-    union {
-        unsigned char b[6];
-        struct {
-            unsigned short high;
-            unsigned short middl;
-            unsigned short low;
-        } w;
-    } paddr;
-    unsigned short  p_per;          /* persistence */
-    unsigned short  rfbd_ptr;       /* rx first bd pointer */
-    unsigned short  tfbd_ptr;       /* tx first bd pointer */
-    unsigned short  tlbd_ptr;       /* tx last bd pointer */
-    unsigned long   tbuf1_data0;    /* save area 0 - next frame */
-    unsigned long   tbuf1_data1;    /* save area 1 - next frame */
-    unsigned long   tbuf1_rba0;
-    unsigned long   tbuf1_crc;
-    unsigned short  tbuf1_bcnt;
-    unsigned short  tx_len;         /* tx frame length counter */
-    unsigned short  iaddr1;         /* individual address filter 1*/
-    unsigned short  iaddr2;         /* individual address filter 2*/
-    unsigned short  iaddr3;         /* individual address filter 3*/
-    unsigned short  iaddr4;         /* individual address filter 4*/
-    unsigned short  boff_cnt;       /* back-off counter */
-    unsigned short  taddr_h;        /* temp address (MSB) */
-    unsigned short  taddr_m;        /* temp address */
-    unsigned short  taddr_l;        /* temp address (LSB) */
-};
-
-struct transparent_pram {
-    /*
-     * SCC parameter RAM
-     */
-    unsigned short  rbase;          /* RX BD base address */
-    unsigned short  tbase;          /* TX BD base address */
-    unsigned char   rfcr;           /* Rx function code */
-    unsigned char   tfcr;           /* Tx function code */
-    unsigned short  mrblr;          /* Rx buffer length */
-    unsigned long   rstate;         /* Rx internal state */
-    unsigned long   rptr;           /* Rx internal data pointer */
-    unsigned short  rbptr;          /* rb BD Pointer */
-    unsigned short  rcount;         /* Rx internal byte count */
-    unsigned long   rtemp;          /* Rx temp */
-    unsigned long   tstate;         /* Tx internal state */
-    unsigned long   tptr;           /* Tx internal data pointer */
-    unsigned short  tbptr;          /* Tx BD pointer */
-    unsigned short  tcount;         /* Tx byte count */
-    unsigned long   ttemp;          /* Tx temp */
-    unsigned long   rcrc;           /* temp receive CRC */
-    unsigned long   tcrc;           /* temp transmit CRC */
-   
-    /*
-     * TRANSPARENT specific parameter RAM
-     */
-    unsigned long   crc_p;          /* CRC Preset */
-    unsigned long   crc_c;          /* CRC constant */
-};
-
-struct timer_pram {
-    /*
-     * RISC timers parameter RAM
-     */
-    unsigned short  tm_base;        /* RISC timer table base adr */
-    unsigned short  tm_ptr;         /* RISC timer table pointer */
-    unsigned short  r_tmr;          /* RISC timer mode register */
-    unsigned short  r_tmv;          /* RISC timer valid register */
-    unsigned long   tm_cmd;         /* RISC timer cmd register */
-    unsigned long   tm_cnt;         /* RISC timer internal cnt */
-};
-
-#endif
diff --git a/arch/m68knommu/include/asm/m68360_quicc.h b/arch/m68knommu/include/asm/m68360_quicc.h
deleted file mode 100644
index 6d40f4d18e10..000000000000
--- a/arch/m68knommu/include/asm/m68360_quicc.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/***********************************
- * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
- ***********************************
- *
- ***************************************
- * Definitions of QUICC memory structures
- ***************************************
- */
-
-#ifndef __M68360_QUICC_H
-#define __M68360_QUICC_H
-
-/*
- * include registers and
- * parameter ram definitions files
- */
-#include <asm/m68360_regs.h>
-#include <asm/m68360_pram.h>
-
-
-
-/* Buffer Descriptors */
-typedef struct quicc_bd {
-    volatile unsigned short     status;
-    volatile unsigned short     length;
-    volatile unsigned char      *buf;     /* WARNING: This is only true if *char is 32 bits */
-} QUICC_BD;
-
-
-#ifdef MOTOROLA_ORIGINAL
-struct user_data {
-    /* BASE + 0x000: user data memory */
-    volatile unsigned char      udata_bd_ucode[0x400]; /*user data bd's Ucode*/
-    volatile unsigned char      udata_bd[0x200];       /*user data Ucode     */
-    volatile unsigned char      ucode_ext[0x100];      /*Ucode Extention ram */
-    volatile unsigned char      RESERVED1[0x500];      /* Reserved area      */
-};
-#else
-struct user_data {
-    /* BASE + 0x000: user data memory */
-    volatile unsigned char      udata_bd_ucode[0x400]; /* user data, bds, Ucode*/
-    volatile unsigned char      udata_bd1[0x200];       /* user, bds */
-    volatile unsigned char      ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */
-    volatile unsigned char      udata_bd2[0x100];       /* user, bds */
-    volatile unsigned char      RESERVED1[0x400];      /* Reserved area      */
-};
-#endif
-
-
-/*
- * internal ram
- */
-typedef struct quicc {
-        union {
-                struct quicc32_pram ch_pram_tbl[32];    /* 32*64(bytes) per channel */  
-                struct user_data                u;
-        }ch_or_u;       /* multipul or user space */
-
-    /* BASE + 0xc00: PARAMETER RAM */
-        union {
-                struct scc_pram {
-                        union {
-                                struct hdlc_pram        h;
-                                struct uart_pram        u;
-                                struct bisync_pram      b;
-                                struct transparent_pram t;
-                                unsigned char   RESERVED66[0x70];
-                        } pscc;               /* scc parameter area (protocol dependent) */
-                        union {
-                                struct {
-                                        unsigned char       RESERVED70[0x10];
-                                        struct spi_pram     spi;
-                                        unsigned char       RESERVED72[0x8];
-                                        struct timer_pram   timer;
-                                } timer_spi;
-                                struct {
-                                        struct idma_pram idma;
-                                        unsigned char       RESERVED67[0x4];
-                                        union {
-                                                struct smc_uart_pram u;
-                                                struct smc_trnsp_pram t;
-                                        } psmc;
-                                } idma_smc;
-                        } pothers;
-                } scc;
-                struct ethernet_pram    enet_scc;
-                struct global_multi_pram        m;
-                unsigned char   pr[0x100];
-        } pram[4];
-
-    /* reserved */
-
-    /* BASE + 0x1000: INTERNAL REGISTERS */
-    /* SIM */
-    volatile unsigned long      sim_mcr;        /* module configuration reg */
-    volatile unsigned short     sim_simtr;      /* module test register     */
-    volatile unsigned char      RESERVED2[0x2]; /* Reserved area            */
-    volatile unsigned char      sim_avr;        /* auto vector reg          */
-    volatile unsigned char      sim_rsr;        /* reset status reg         */
-    volatile unsigned char      RESERVED3[0x2]; /* Reserved area            */
-    volatile unsigned char      sim_clkocr;     /* CLCO control register    */
-    volatile unsigned char      RESERVED62[0x3];        /* Reserved area    */
-    volatile unsigned short     sim_pllcr;      /* PLL control register     */
-    volatile unsigned char      RESERVED63[0x2];        /* Reserved area    */
-    volatile unsigned short     sim_cdvcr;      /* Clock devider control register */
-    volatile unsigned short     sim_pepar;      /* Port E pin assignment register */
-    volatile unsigned char      RESERVED64[0xa];        /* Reserved area    */
-    volatile unsigned char      sim_sypcr;      /* system protection control*/
-    volatile unsigned char      sim_swiv;       /* software interrupt vector*/
-    volatile unsigned char      RESERVED6[0x2]; /* Reserved area            */
-    volatile unsigned short     sim_picr;       /* periodic interrupt control reg */
-    volatile unsigned char      RESERVED7[0x2]; /* Reserved area            */
-    volatile unsigned short     sim_pitr;       /* periodic interrupt timing reg */
-    volatile unsigned char      RESERVED8[0x3]; /* Reserved area            */
-    volatile unsigned char      sim_swsr;       /* software service         */
-    volatile unsigned long      sim_bkar;       /* breakpoint address register*/
-    volatile unsigned long      sim_bkcr;       /* breakpoint control register*/
-    volatile unsigned char      RESERVED10[0x8];        /* Reserved area    */
-    /* MEMC */
-    volatile unsigned long      memc_gmr;       /* Global memory register   */
-    volatile unsigned short     memc_mstat;     /* MEMC status register     */
-    volatile unsigned char      RESERVED11[0xa];        /* Reserved area    */
-    volatile unsigned long      memc_br0;       /* base register 0          */
-    volatile unsigned long      memc_or0;       /* option register 0        */
-    volatile unsigned char      RESERVED12[0x8];        /* Reserved area    */
-    volatile unsigned long      memc_br1;       /* base register 1          */
-    volatile unsigned long      memc_or1;       /* option register 1        */
-    volatile unsigned char      RESERVED13[0x8];        /* Reserved area    */
-    volatile unsigned long      memc_br2;       /* base register 2          */
-    volatile unsigned long      memc_or2;       /* option register 2        */
-    volatile unsigned char      RESERVED14[0x8];        /* Reserved area    */
-    volatile unsigned long      memc_br3;       /* base register 3          */
-    volatile unsigned long      memc_or3;       /* option register 3        */
-    volatile unsigned char      RESERVED15[0x8];        /* Reserved area    */
-    volatile unsigned long      memc_br4;       /* base register 3          */
-    volatile unsigned long      memc_or4;       /* option register 3        */
-    volatile unsigned char      RESERVED16[0x8];        /* Reserved area    */
-    volatile unsigned long      memc_br5;       /* base register 3          */
-    volatile unsigned long      memc_or5;       /* option register 3        */
-    volatile unsigned char      RESERVED17[0x8];        /* Reserved area    */
-    volatile unsigned long      memc_br6;       /* base register 3          */
-    volatile unsigned long      memc_or6;       /* option register 3        */
-    volatile unsigned char      RESERVED18[0x8];        /* Reserved area    */
-    volatile unsigned long      memc_br7;       /* base register 3          */
-    volatile unsigned long      memc_or7;       /* option register 3        */
-    volatile unsigned char      RESERVED9[0x28];        /* Reserved area    */
-    /* TEST */
-    volatile unsigned short     test_tstmra;    /* master shift a           */
-    volatile unsigned short     test_tstmrb;    /* master shift b           */
-    volatile unsigned short     test_tstsc;     /* shift count              */
-    volatile unsigned short     test_tstrc;     /* repetition counter       */
-    volatile unsigned short     test_creg;      /* control                  */
-    volatile unsigned short     test_dreg;      /* destributed register     */
-    volatile unsigned char      RESERVED58[0x404];      /* Reserved area    */
-    /* IDMA1 */
-    volatile unsigned short     idma_iccr;      /* channel configuration reg*/
-    volatile unsigned char      RESERVED19[0x2];        /* Reserved area    */
-    volatile unsigned short     idma1_cmr;      /* dma mode reg             */
-    volatile unsigned char      RESERVED68[0x2];        /* Reserved area    */
-    volatile unsigned long      idma1_sapr;     /* dma source addr ptr      */
-    volatile unsigned long      idma1_dapr;     /* dma destination addr ptr */
-    volatile unsigned long      idma1_bcr;      /* dma byte count reg       */
-    volatile unsigned char      idma1_fcr;      /* function code reg        */
-    volatile unsigned char      RESERVED20;     /* Reserved area            */
-    volatile unsigned char      idma1_cmar;     /* channel mask reg         */
-    volatile unsigned char      RESERVED21;     /* Reserved area            */
-    volatile unsigned char      idma1_csr;      /* channel status reg       */
-    volatile unsigned char      RESERVED22[0x3];        /* Reserved area    */
-    /* SDMA */
-    volatile unsigned char      sdma_sdsr;      /* status reg               */
-    volatile unsigned char      RESERVED23;     /* Reserved area            */
-    volatile unsigned short     sdma_sdcr;      /* configuration reg        */
-    volatile unsigned long      sdma_sdar;      /* address reg              */
-    /* IDMA2 */
-    volatile unsigned char      RESERVED69[0x2];        /* Reserved area    */
-    volatile unsigned short     idma2_cmr;      /* dma mode reg             */
-    volatile unsigned long      idma2_sapr;     /* dma source addr ptr      */
-    volatile unsigned long      idma2_dapr;     /* dma destination addr ptr */
-    volatile unsigned long      idma2_bcr;      /* dma byte count reg       */
-    volatile unsigned char      idma2_fcr;      /* function code reg        */
-    volatile unsigned char      RESERVED24;     /* Reserved area            */
-    volatile unsigned char      idma2_cmar;     /* channel mask reg         */
-    volatile unsigned char      RESERVED25;     /* Reserved area            */
-    volatile unsigned char      idma2_csr;      /* channel status reg       */
-    volatile unsigned char      RESERVED26[0x7];        /* Reserved area    */
-    /* Interrupt Controller */
-    volatile unsigned long      intr_cicr;      /* CP interrupt configuration reg*/
-    volatile unsigned long      intr_cipr;      /* CP interrupt pending reg */
-    volatile unsigned long      intr_cimr;      /* CP interrupt mask reg    */
-    volatile unsigned long      intr_cisr;      /* CP interrupt in service reg*/
-    /* Parallel I/O */
-    volatile unsigned short     pio_padir;      /* port A data direction reg */
-    volatile unsigned short     pio_papar;      /* port A pin assignment reg */
-    volatile unsigned short     pio_paodr;      /* port A open drain reg    */
-    volatile unsigned short     pio_padat;      /* port A data register     */
-    volatile unsigned char      RESERVED28[0x8];        /* Reserved area    */
-    volatile unsigned short     pio_pcdir;      /* port C data direction reg*/
-    volatile unsigned short     pio_pcpar;      /* port C pin assignment reg*/
-    volatile unsigned short     pio_pcso;       /* port C special options   */
-    volatile unsigned short     pio_pcdat;      /* port C data register     */
-    volatile unsigned short     pio_pcint;      /* port C interrupt cntrl reg */
-    volatile unsigned char      RESERVED29[0x16];       /* Reserved area    */
-    /* Timer */
-    volatile unsigned short     timer_tgcr;     /* timer global configuration reg */
-    volatile unsigned char      RESERVED30[0xe];        /* Reserved area    */
-    volatile unsigned short     timer_tmr1;     /* timer 1 mode reg         */
-    volatile unsigned short     timer_tmr2;     /* timer 2 mode reg         */
-    volatile unsigned short     timer_trr1;     /* timer 1 referance reg    */
-    volatile unsigned short     timer_trr2;     /* timer 2 referance reg    */
-    volatile unsigned short     timer_tcr1;     /* timer 1 capture reg      */
-    volatile unsigned short     timer_tcr2;     /* timer 2 capture reg      */
-    volatile unsigned short     timer_tcn1;     /* timer 1 counter reg      */
-    volatile unsigned short     timer_tcn2;     /* timer 2 counter reg      */
-    volatile unsigned short     timer_tmr3;     /* timer 3 mode reg         */
-    volatile unsigned short     timer_tmr4;     /* timer 4 mode reg         */
-    volatile unsigned short     timer_trr3;     /* timer 3 referance reg    */
-    volatile unsigned short     timer_trr4;     /* timer 4 referance reg    */
-    volatile unsigned short     timer_tcr3;     /* timer 3 capture reg      */
-    volatile unsigned short     timer_tcr4;     /* timer 4 capture reg      */
-    volatile unsigned short     timer_tcn3;     /* timer 3 counter reg      */
-    volatile unsigned short     timer_tcn4;     /* timer 4 counter reg      */
-    volatile unsigned short     timer_ter1;     /* timer 1 event reg        */
-    volatile unsigned short     timer_ter2;     /* timer 2 event reg        */
-    volatile unsigned short     timer_ter3;     /* timer 3 event reg        */
-    volatile unsigned short     timer_ter4;     /* timer 4 event reg        */
-    volatile unsigned char      RESERVED34[0x8];        /* Reserved area    */
-    /* CP */
-    volatile unsigned short     cp_cr;          /* command register         */
-    volatile unsigned char      RESERVED35[0x2];        /* Reserved area    */
-    volatile unsigned short     cp_rccr;        /* main configuration reg   */
-    volatile unsigned char      RESERVED37;     /* Reserved area            */
-    volatile unsigned char      cp_rmds;        /* development support status reg */
-    volatile unsigned long      cp_rmdr;        /* development support control reg */
-    volatile unsigned short     cp_rctr1;       /* ram break register 1     */
-    volatile unsigned short     cp_rctr2;       /* ram break register 2     */
-    volatile unsigned short     cp_rctr3;       /* ram break register 3     */
-    volatile unsigned short     cp_rctr4;       /* ram break register 4     */
-    volatile unsigned char      RESERVED59[0x2];        /* Reserved area    */
-    volatile unsigned short     cp_rter;        /* RISC timers event reg    */
-    volatile unsigned char      RESERVED38[0x2];        /* Reserved area    */
-    volatile unsigned short     cp_rtmr;        /* RISC timers mask reg     */
-    volatile unsigned char      RESERVED39[0x14];       /* Reserved area    */
-    /* BRG */
-    union {
-        volatile unsigned long l;
-        struct {
-            volatile unsigned short BRGC_RESERV:14;
-            volatile unsigned short rst:1;
-            volatile unsigned short en:1;
-            volatile unsigned short extc:2;
-            volatile unsigned short atb:1;
-            volatile unsigned short cd:12;
-            volatile unsigned short div16:1;
-        } b;
-    } brgc[4];                                  /* BRG1-BRG4 configuration regs*/
-    /* SCC registers */
-    struct scc_regs {
-        union {
-            struct {
-                /* Low word. */
-                volatile unsigned short GSMR_RESERV2:1;
-                volatile unsigned short edge:2;
-                volatile unsigned short tci:1;
-                volatile unsigned short tsnc:2;
-                volatile unsigned short rinv:1;
-                volatile unsigned short tinv:1;
-                volatile unsigned short tpl:3;
-                volatile unsigned short tpp:2;
-                volatile unsigned short tend:1;
-                volatile unsigned short tdcr:2;
-                volatile unsigned short rdcr:2;
-                volatile unsigned short renc:3;
-                volatile unsigned short tenc:3;
-                volatile unsigned short diag:2;
-                volatile unsigned short enr:1;
-                volatile unsigned short ent:1;
-                volatile unsigned short mode:4;
-                /* High word. */
-                volatile unsigned short GSMR_RESERV1:14;
-                volatile unsigned short pri:1;
-                volatile unsigned short gde:1;
-                volatile unsigned short tcrc:2;
-                volatile unsigned short revd:1;
-                volatile unsigned short trx:1;
-                volatile unsigned short ttx:1;
-                volatile unsigned short cdp:1;
-                volatile unsigned short ctsp:1;
-                volatile unsigned short cds:1;
-                volatile unsigned short ctss:1;
-                volatile unsigned short tfl:1;
-                volatile unsigned short rfw:1;
-                volatile unsigned short txsy:1;
-                volatile unsigned short synl:2;
-                volatile unsigned short rtsm:1;
-                volatile unsigned short rsyn:1;
-            } b;
-            struct {
-                volatile unsigned long low;
-                volatile unsigned long high;
-            } w;
-        } scc_gsmr;                         /* SCC general mode reg         */
-        volatile unsigned short scc_psmr;   /* protocol specific mode reg   */
-        volatile unsigned char  RESERVED42[0x2]; /* Reserved area           */
-        volatile unsigned short scc_todr; /* SCC transmit on demand         */
-        volatile unsigned short scc_dsr;        /* SCC data sync reg        */
-        volatile unsigned short scc_scce;       /* SCC event reg            */
-        volatile unsigned char  RESERVED43[0x2];/* Reserved area            */
-        volatile unsigned short scc_sccm;       /* SCC mask reg             */
-        volatile unsigned char  RESERVED44[0x1];/* Reserved area            */
-        volatile unsigned char  scc_sccs;       /* SCC status reg           */
-        volatile unsigned char  RESERVED45[0x8]; /* Reserved area           */
-    } scc_regs[4];
-    /* SMC */
-    struct smc_regs {
-        volatile unsigned char  RESERVED46[0x2]; /* Reserved area           */
-        volatile unsigned short smc_smcmr;       /* SMC mode reg            */
-        volatile unsigned char  RESERVED60[0x2]; /* Reserved area           */
-        volatile unsigned char  smc_smce;        /* SMC event reg           */
-        volatile unsigned char  RESERVED47[0x3]; /* Reserved area           */
-        volatile unsigned char  smc_smcm;        /* SMC mask reg            */
-        volatile unsigned char  RESERVED48[0x5]; /* Reserved area           */
-    } smc_regs[2];
-    /* SPI */
-    volatile unsigned short     spi_spmode;     /* SPI mode reg             */
-    volatile unsigned char      RESERVED51[0x4];        /* Reserved area    */
-    volatile unsigned char      spi_spie;       /* SPI event reg            */
-    volatile unsigned char      RESERVED52[0x3];        /* Reserved area    */
-    volatile unsigned char      spi_spim;       /* SPI mask reg             */
-    volatile unsigned char      RESERVED53[0x2];        /* Reserved area    */
-    volatile unsigned char      spi_spcom;      /* SPI command reg          */
-    volatile unsigned char      RESERVED54[0x4];        /* Reserved area    */
-    /* PIP */
-    volatile unsigned short     pip_pipc;       /* pip configuration reg    */
-    volatile unsigned char      RESERVED65[0x2];        /* Reserved area    */
-    volatile unsigned short     pip_ptpr;       /* pip timing parameters reg */
-    volatile unsigned long      pip_pbdir;      /* port b data direction reg */
-    volatile unsigned long      pip_pbpar;      /* port b pin assignment reg */
-    volatile unsigned long      pip_pbodr;      /* port b open drain reg    */
-    volatile unsigned long      pip_pbdat;      /* port b data reg          */
-    volatile unsigned char      RESERVED71[0x18];       /* Reserved area    */
-    /* Serial Interface */
-    volatile unsigned long      si_simode;      /* SI mode register         */
-    volatile unsigned char      si_sigmr;       /* SI global mode register  */
-    volatile unsigned char      RESERVED55;     /* Reserved area            */
-    volatile unsigned char      si_sistr;       /* SI status register       */
-    volatile unsigned char      si_sicmr;       /* SI command register      */
-    volatile unsigned char      RESERVED56[0x4]; /* Reserved area           */
-    volatile unsigned long      si_sicr;        /* SI clock routing         */
-    volatile unsigned long      si_sirp;        /* SI ram pointers          */
-    volatile unsigned char      RESERVED57[0xc]; /* Reserved area           */
-    volatile unsigned short     si_siram[0x80]; /* SI routing ram          */
-} QUICC;
-
-#endif
-
-/*
- * Local variables:
- *  c-indent-level: 4
- *  c-basic-offset: 4
- *  tab-width: 4
- * End:
- */
diff --git a/arch/m68knommu/include/asm/m68360_regs.h b/arch/m68knommu/include/asm/m68360_regs.h
deleted file mode 100644
index d57217ca4f27..000000000000
--- a/arch/m68knommu/include/asm/m68360_regs.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/***********************************
- * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
- ***********************************
- *
- ***************************************
- * Definitions of the QUICC registers
- ***************************************
- */
-
-#ifndef __REGISTERS_H
-#define __REGISTERS_H
-
-#define CLEAR_BIT(x, bit)  x =bit 
-
-/*****************************************************************
-        Command Register
-*****************************************************************/
-
-/* bit fields within command register */
-#define SOFTWARE_RESET  0x8000
-#define CMD_OPCODE      0x0f00
-#define CMD_CHANNEL     0x00f0
-#define CMD_FLAG        0x0001
-
-/* general command opcodes */
-#define INIT_RXTX_PARAMS        0x0000
-#define INIT_RX_PARAMS          0x0100
-#define INIT_TX_PARAMS          0x0200
-#define ENTER_HUNT_MODE         0x0300
-#define STOP_TX                 0x0400
-#define GR_STOP_TX              0x0500
-#define RESTART_TX              0x0600
-#define CLOSE_RX_BD             0x0700
-#define SET_ENET_GROUP          0x0800
-#define RESET_ENET_GROUP        0x0900
-
-/* quicc32 CP commands */
-#define STOP_TX_32              0x0e00  /*add chan# bits 2-6 */
-#define ENTER_HUNT_MODE_32      0x1e00
-
-/* quicc32 mask/event SCC register */
-#define GOV     0x01
-#define GUN     0x02
-#define GINT    0x04
-#define IQOV    0x08
-
-
-/* Timer commands */
-#define SET_TIMER               0x0800
-
-/* Multi channel Interrupt structure */
-#define INTR_VALID      0x8000  /* Valid interrupt entry */
-#define INTR_WRAP       0x4000  /* Wrap bit in the interrupt entry table */
-#define INTR_CH_NU      0x07c0  /* Channel Num in interrupt table */
-#define INTR_MASK_BITS  0x383f
-
-/*
- * General SCC mode register (GSMR)
- */
-
-#define MODE_HDLC               0x0
-#define MODE_APPLE_TALK         0x2
-#define MODE_SS7                0x3
-#define MODE_UART               0x4
-#define MODE_PROFIBUS           0x5
-#define MODE_ASYNC_HDLC         0x6
-#define MODE_V14                0x7
-#define MODE_BISYNC             0x8
-#define MODE_DDCMP              0x9
-#define MODE_MULTI_CHANNEL      0xa
-#define MODE_ETHERNET           0xc
-
-#define DIAG_NORMAL             0x0
-#define DIAG_LOCAL_LPB          0x1
-#define DIAG_AUTO_ECHO          0x2
-#define DIAG_LBP_ECHO           0x3
-
-/* For RENC and TENC fields in GSMR */
-#define ENC_NRZ                 0x0
-#define ENC_NRZI                0x1
-#define ENC_FM0                 0x2
-#define ENC_MANCH               0x4
-#define ENC_DIFF_MANC           0x6
-
-/* For TDCR and RDCR fields in GSMR */
-#define CLOCK_RATE_1            0x0
-#define CLOCK_RATE_8            0x1
-#define CLOCK_RATE_16           0x2
-#define CLOCK_RATE_32           0x3
-
-#define TPP_00                  0x0
-#define TPP_10                  0x1
-#define TPP_01                  0x2
-#define TPP_11                  0x3
-
-#define TPL_NO                  0x0
-#define TPL_8                   0x1
-#define TPL_16                  0x2
-#define TPL_32                  0x3
-#define TPL_48                  0x4
-#define TPL_64                  0x5
-#define TPL_128                 0x6
-
-#define TSNC_INFINITE           0x0
-#define TSNC_14_65              0x1
-#define TSNC_4_15               0x2
-#define TSNC_3_1                0x3
-
-#define EDGE_BOTH               0x0
-#define EDGE_POS                0x1
-#define EDGE_NEG                0x2
-#define EDGE_NO                 0x3
-
-#define SYNL_NO                 0x0
-#define SYNL_4                  0x1
-#define SYNL_8                  0x2
-#define SYNL_16                 0x3
-
-#define TCRC_CCITT16            0x0
-#define TCRC_CRC16              0x1
-#define TCRC_CCITT32            0x2
-
-
-/*****************************************************************
-        TODR (Transmit on demand) Register
-*****************************************************************/
-#define TODR_TOD        0x8000  /* Transmit on demand */
-
-
-/*****************************************************************
-        CICR register settings
-*****************************************************************/
-
-/* note that relative irq priorities of the SCCs can be reordered
- * if desired - see p. 7-377 of the MC68360UM */
-#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
-#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
-#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
-#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
-
-#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
-#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
-#define CICR_VBA_MASK           ((uint)0x000000e0)      /* Vector Base Address */
-#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
-
-
-/*****************************************************************
-       Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379)
-*****************************************************************/
-
-#define INTR_PIO_PC0    0x80000000      /* parallel I/O C bit 0 */
-#define INTR_SCC1       0x40000000      /* SCC port 1 */
-#define INTR_SCC2       0x20000000      /* SCC port 2 */
-#define INTR_SCC3       0x10000000      /* SCC port 3 */
-#define INTR_SCC4       0x08000000      /* SCC port 4 */
-#define INTR_PIO_PC1    0x04000000      /* parallel i/o C bit 1 */
-#define INTR_TIMER1     0x02000000      /* timer 1 */
-#define INTR_PIO_PC2    0x01000000      /* parallel i/o C bit 2 */
-#define INTR_PIO_PC3    0x00800000      /* parallel i/o C bit 3 */
-#define INTR_SDMA_BERR  0x00400000      /* SDMA channel bus error */
-#define INTR_DMA1       0x00200000      /* idma 1 */
-#define INTR_DMA2       0x00100000      /* idma 2 */
-#define INTR_TIMER2     0x00040000      /* timer 2 */
-#define INTR_CP_TIMER   0x00020000      /* CP timer */
-#define INTR_PIP_STATUS 0x00010000      /* PIP status */
-#define INTR_PIO_PC4    0x00008000      /* parallel i/o C bit 4 */
-#define INTR_PIO_PC5    0x00004000      /* parallel i/o C bit 5 */
-#define INTR_TIMER3     0x00001000      /* timer 3 */
-#define INTR_PIO_PC6    0x00000800      /* parallel i/o C bit 6 */
-#define INTR_PIO_PC7    0x00000400      /* parallel i/o C bit 7 */
-#define INTR_PIO_PC8    0x00000200      /* parallel i/o C bit 8 */
-#define INTR_TIMER4     0x00000080      /* timer 4 */
-#define INTR_PIO_PC9    0x00000040      /* parallel i/o C bit 9 */
-#define INTR_SCP        0x00000020      /* SCP */
-#define INTR_SMC1       0x00000010      /* SMC 1 */
-#define INTR_SMC2       0x00000008      /* SMC 2 */
-#define INTR_PIO_PC10   0x00000004      /* parallel i/o C bit 10 */
-#define INTR_PIO_PC11   0x00000002      /* parallel i/o C bit 11 */
-#define INTR_ERR        0x00000001      /* error */
-
-
-/*****************************************************************
-        CPM Interrupt vector encodings (MC68360UM p. 7-376)
-*****************************************************************/
-
-#define CPMVEC_NR               32
-#define CPMVEC_PIO_PC0          0x1f
-#define CPMVEC_SCC1             0x1e
-#define CPMVEC_SCC2             0x1d
-#define CPMVEC_SCC3             0x1c
-#define CPMVEC_SCC4             0x1b
-#define CPMVEC_PIO_PC1          0x1a
-#define CPMVEC_TIMER1           0x19
-#define CPMVEC_PIO_PC2          0x18
-#define CPMVEC_PIO_PC3          0x17
-#define CPMVEC_SDMA_CB_ERR      0x16
-#define CPMVEC_IDMA1            0x15
-#define CPMVEC_IDMA2            0x14
-#define CPMVEC_RESERVED3        0x13
-#define CPMVEC_TIMER2           0x12
-#define CPMVEC_RISCTIMER        0x11
-#define CPMVEC_RESERVED2        0x10
-#define CPMVEC_PIO_PC4          0x0f
-#define CPMVEC_PIO_PC5          0x0e
-#define CPMVEC_TIMER3           0x0c
-#define CPMVEC_PIO_PC6          0x0b
-#define CPMVEC_PIO_PC7          0x0a
-#define CPMVEC_PIO_PC8          0x09
-#define CPMVEC_RESERVED1        0x08
-#define CPMVEC_TIMER4           0x07
-#define CPMVEC_PIO_PC9          0x06
-#define CPMVEC_SPI              0x05
-#define CPMVEC_SMC1             0x04
-#define CPMVEC_SMC2             0x03
-#define CPMVEC_PIO_PC10         0x02
-#define CPMVEC_PIO_PC11         0x01
-#define CPMVEC_ERROR            0x00
-
-/* #define CPMVEC_PIO_PC0               ((ushort)0x1f) */
-/* #define CPMVEC_SCC1          ((ushort)0x1e) */
-/* #define CPMVEC_SCC2          ((ushort)0x1d) */
-/* #define CPMVEC_SCC3          ((ushort)0x1c) */
-/* #define CPMVEC_SCC4          ((ushort)0x1b) */
-/* #define CPMVEC_PIO_PC1               ((ushort)0x1a) */
-/* #define CPMVEC_TIMER1                ((ushort)0x19) */
-/* #define CPMVEC_PIO_PC2               ((ushort)0x18) */
-/* #define CPMVEC_PIO_PC3               ((ushort)0x17) */
-/* #define CPMVEC_SDMA_CB_ERR   ((ushort)0x16) */
-/* #define CPMVEC_IDMA1         ((ushort)0x15) */
-/* #define CPMVEC_IDMA2         ((ushort)0x14) */
-/* #define CPMVEC_RESERVED3     ((ushort)0x13) */
-/* #define CPMVEC_TIMER2                ((ushort)0x12) */
-/* #define CPMVEC_RISCTIMER     ((ushort)0x11) */
-/* #define CPMVEC_RESERVED2     ((ushort)0x10) */
-/* #define CPMVEC_PIO_PC4               ((ushort)0x0f) */
-/* #define CPMVEC_PIO_PC5               ((ushort)0x0e) */
-/* #define CPMVEC_TIMER3                ((ushort)0x0c) */
-/* #define CPMVEC_PIO_PC6               ((ushort)0x0b) */
-/* #define CPMVEC_PIO_PC7               ((ushort)0x0a) */
-/* #define CPMVEC_PIO_PC8               ((ushort)0x09) */
-/* #define CPMVEC_RESERVED1     ((ushort)0x08) */
-/* #define CPMVEC_TIMER4                ((ushort)0x07) */
-/* #define CPMVEC_PIO_PC9               ((ushort)0x06) */
-/* #define CPMVEC_SPI           ((ushort)0x05) */
-/* #define CPMVEC_SMC1          ((ushort)0x04) */
-/* #define CPMVEC_SMC2          ((ushort)0x03) */
-/* #define CPMVEC_PIO_PC10              ((ushort)0x02) */
-/* #define CPMVEC_PIO_PC11              ((ushort)0x01) */
-/* #define CPMVEC_ERROR         ((ushort)0x00) */
-
-
-/*****************************************************************
- *        PIO control registers
- *****************************************************************/
-
-/* Port A - See 360UM p. 7-358
- * 
- *  Note that most of these pins have alternate functions
- */
-
-
-/* The macros are nice, but there are all sorts of references to 1-indexed
- * facilities on the 68360... */
-/* #define PA_RXD(n)    ((ushort)(0x01<<(2*n))) */
-/* #define PA_TXD(n)    ((ushort)(0x02<<(2*n))) */
-
-#define PA_RXD1         ((ushort)0x0001)
-#define PA_TXD1         ((ushort)0x0002)
-#define PA_RXD2         ((ushort)0x0004)
-#define PA_TXD2         ((ushort)0x0008)
-#define PA_RXD3         ((ushort)0x0010)
-#define PA_TXD3         ((ushort)0x0020)
-#define PA_RXD4         ((ushort)0x0040)
-#define PA_TXD4         ((ushort)0x0080)
-
-#define PA_CLK1         ((ushort)0x0100)
-#define PA_CLK2         ((ushort)0x0200)
-#define PA_CLK3         ((ushort)0x0400)
-#define PA_CLK4         ((ushort)0x0800)
-#define PA_CLK5         ((ushort)0x1000)
-#define PA_CLK6         ((ushort)0x2000)
-#define PA_CLK7         ((ushort)0x4000)
-#define PA_CLK8         ((ushort)0x8000)
-
-
-/* Port B - See 360UM p. 7-362
- */
-
-
-/* Port C - See 360UM p. 7-365
- */
-
-#define PC_RTS1         ((ushort)0x0001)
-#define PC_RTS2         ((ushort)0x0002)
-#define PC__RTS3        ((ushort)0x0004) /* !RTS3 */
-#define PC__RTS4        ((ushort)0x0008) /* !RTS4 */
-
-#define PC_CTS1         ((ushort)0x0010)
-#define PC_CD1          ((ushort)0x0020)
-#define PC_CTS2         ((ushort)0x0040)
-#define PC_CD2          ((ushort)0x0080)
-#define PC_CTS3         ((ushort)0x0100)
-#define PC_CD3          ((ushort)0x0200)
-#define PC_CTS4         ((ushort)0x0400)
-#define PC_CD4          ((ushort)0x0800)
-
-
-
-/*****************************************************************
-        chip select option register
-*****************************************************************/
-#define DTACK           0xe000
-#define ADR_MASK        0x1ffc
-#define RDWR_MASK       0x0002
-#define FC_MASK         0x0001
-
-/*****************************************************************
-        tbase and rbase registers
-*****************************************************************/
-#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \
-    (quicc->ch_or_u.u.udata_bd_ucode + pram->tbase))
-#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \
-    (quicc->ch_or_u.u.udata_bd_ucode + pram->rbase))
-#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
-    (quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr))
-#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
-    (quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr))
-#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \
-    ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
-#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \
-    ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
-#define INCREASE_TBD(bd,quicc,pram) {  \
-    if((bd)->status & T_W)             \
-        (bd) = TBD_ADDR(quicc,pram);   \
-    else                               \
-        (bd)++;                        \
-}
-#define DECREASE_TBD(bd,quicc,pram) {  \
-    if ((bd) == TBD_ADDR(quicc, pram)) \
-        while (!((bd)->status & T_W))  \
-            (bd)++;                    \
-    else                               \
-        (bd)--;                        \
-}
-#define INCREASE_RBD(bd,quicc,pram) {  \
-    if((bd)->status & R_W)             \
-        (bd) = RBD_ADDR(quicc,pram);   \
-    else                               \
-        (bd)++;                        \
-}
-#define DECREASE_RBD(bd,quicc,pram) {  \
-    if ((bd) == RBD_ADDR(quicc, pram)) \
-        while (!((bd)->status & T_W))  \
-            (bd)++;                    \
-    else                               \
-        (bd)--;                        \
-}
-
-/*****************************************************************
-        Macros for Multi channel
-*****************************************************************/
-#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page])
-#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase)
-#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \
-                (&(quicc->ch_or_u.ch_pram_tbl[channel])))
-#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
-    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase)))
-#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
-    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase)))
-#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
-    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr)))
-#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
-    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr)))
-#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
-     CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \
-    ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
-#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
-     CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \
-    ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
-
-#define INCREASE_TBD_32(bd,quicc,page,channel) {  \
-    if((bd)->status & T_W)                        \
-        (bd) = TBD_32_ADDR(quicc,page,channel);   \
-    else                                          \
-        (bd)++;                                   \
-}
-#define DECREASE_TBD_32(bd,quicc,page,channel) {  \
-    if ((bd) == TBD_32_ADDR(quicc, page,channel)) \
-        while (!((bd)->status & T_W))             \
-            (bd)++;                               \
-    else                                          \
-        (bd)--;                                   \
-}
-#define INCREASE_RBD_32(bd,quicc,page,channel) {  \
-    if((bd)->status & R_W)                        \
-        (bd) = RBD_32_ADDR(quicc,page,channel);   \
-    else                                          \
-        (bd)++;                                   \
-}
-#define DECREASE_RBD_32(bd,quicc,page,channel) {  \
-    if ((bd) == RBD_32_ADDR(quicc, page,channel)) \
-        while (!((bd)->status & T_W))             \
-            (bd)++;                               \
-    else                                          \
-        (bd)--;                                   \
-}
-
-#endif
diff --git a/arch/m68knommu/include/asm/machdep.h b/arch/m68knommu/include/asm/machdep.h
deleted file mode 100644
index de9f47a51cc2..000000000000
--- a/arch/m68knommu/include/asm/machdep.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef _M68KNOMMU_MACHDEP_H
-#define _M68KNOMMU_MACHDEP_H
-
-#include <linux/interrupt.h>
-
-/* Hardware clock functions */
-extern void hw_timer_init(void);
-extern unsigned long hw_timer_offset(void);
-
-extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
-
-/* Machine dependent time handling */
-extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
-                           int *min, int *sec);
-extern int (*mach_set_clock_mmss)(unsigned long);
-
-/* machine dependent power off functions */
-extern void (*mach_reset)( void );
-extern void (*mach_halt)( void );
-extern void (*mach_power_off)( void );
-
-extern void config_BSP(char *command, int len);
-
-extern void do_IRQ(int irq, struct pt_regs *fp);
-
-#endif /* _M68KNOMMU_MACHDEP_H */
diff --git a/arch/m68knommu/include/asm/math-emu.h b/arch/m68knommu/include/asm/math-emu.h
deleted file mode 100644
index 7e7090517b72..000000000000
--- a/arch/m68knommu/include/asm/math-emu.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/math-emu.h>
diff --git a/arch/m68knommu/include/asm/mc146818rtc.h b/arch/m68knommu/include/asm/mc146818rtc.h
deleted file mode 100644
index 907a0481a140..000000000000
--- a/arch/m68knommu/include/asm/mc146818rtc.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef _M68KNOMMU_MC146818RTC_H
-#define _M68KNOMMU_MC146818RTC_H
-
-/* empty include file to satisfy the include in genrtc.c/ide-geometry.c */
-
-#endif /* _M68KNOMMU_MC146818RTC_H */
diff --git a/arch/m68knommu/include/asm/mcfcache.h b/arch/m68knommu/include/asm/mcfcache.h
deleted file mode 100644
index c042634fadaa..000000000000
--- a/arch/m68knommu/include/asm/mcfcache.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfcache.h -- ColdFire CPU cache support code
- *
- *      (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
- */
-
-/****************************************************************************/
-#ifndef __M68KNOMMU_MCFCACHE_H
-#define __M68KNOMMU_MCFCACHE_H
-/****************************************************************************/
-
-
-/*
- *      The different ColdFire families have different cache arrangments.
- *      Everything from a small instruction only cache, to configurable
- *      data and/or instruction cache, to unified instruction/data, to 
- *      harvard style separate instruction and data caches.
- */
-
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
-/*
- *      Simple version 2 core cache. These have instruction cache only,
- *      we just need to invalidate it and enable it.
- */
-.macro CACHE_ENABLE
-        movel   #0x01000000,%d0         /* invalidate cache cmd */
-        movec   %d0,%CACR               /* do invalidate cache */
-        movel   #0x80000100,%d0         /* setup cache mask */
-        movec   %d0,%CACR               /* enable cache */
-.endm
-#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
-
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
-/*
- *      New version 2 cores have a configurable split cache arrangement.
- *      For now I am just enabling instruction cache - but ultimately I
- *      think a split instruction/data cache would be better.
- */
-.macro CACHE_ENABLE
-        movel   #0x01400000,%d0
-        movec   %d0,%CACR               /* invalidate cache */
-        nop
-        movel   #0x0000c000,%d0         /* set SDRAM cached only */
-        movec   %d0,%ACR0
-        movel   #0x00000000,%d0         /* no other regions cached */
-        movec   %d0,%ACR1
-        movel   #0x80400100,%d0         /* configure cache */
-        movec   %d0,%CACR               /* enable cache */
-        nop
-.endm
-#endif /* CONFIG_M523x || CONFIG_M527x */
-
-#if defined(CONFIG_M528x)
-.macro CACHE_ENABLE
-        nop
-        movel   #0x01000000, %d0
-        movec   %d0, %CACR              /* Invalidate cache */
-        nop
-        movel   #0x0000c020, %d0        /* Set SDRAM cached only */
-        movec   %d0, %ACR0
-        movel   #0x00000000, %d0        /* No other regions cached */
-        movec   %d0, %ACR1
-        movel   #0x80000200, %d0        /* Setup cache mask */
-        movec   %d0, %CACR              /* Enable cache */
-        nop
-.endm
-#endif /* CONFIG_M528x */
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
-/*
- *      The version 3 core cache. Oddly enough the version 2 core 5249
- *      has the same SDRAM and cache setup as the version 3 cores.
- *      This is a single unified instruction/data cache.
- */
-.macro CACHE_ENABLE
-        movel   #0x01000000,%d0         /* invalidate whole cache */
-        movec   %d0,%CACR
-        nop
-#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
-        movel   #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
-#else
-        movel   #0x0000c020,%d0         /* set SDRAM cached (copyback) */
-#endif
-        movec   %d0,%ACR0
-        movel   #0x00000000,%d0         /* no other regions cached */
-        movec   %d0,%ACR1
-        movel   #0xa0000200,%d0         /* enable cache */
-        movec   %d0,%CACR
-        nop
-.endm
-#endif /* CONFIG_M5249 || CONFIG_M5307 */
-
-#if defined(CONFIG_M532x)
-.macro CACHE_ENABLE
-        movel   #0x01000000,%d0         /* invalidate cache cmd */
-        movec   %d0,%CACR               /* do invalidate cache */
-        nop
-        movel   #0x4001C000,%d0         /* set SDRAM cached (write-thru) */
-        movec   %d0,%ACR0
-        movel   #0x00000000,%d0         /* no other regions cached */
-        movec   %d0,%ACR1
-        movel   #0x80000200,%d0         /* setup cache mask */
-        movec   %d0,%CACR               /* enable cache */
-        nop
-.endm
-#endif /* CONFIG_M532x */
-
-#if defined(CONFIG_M5407)
-/*
- *      Version 4 cores have a true harvard style separate instruction
- *      and data cache. Invalidate and enable cache, also enable write
- *      buffers and branch accelerator.
- */
-.macro CACHE_ENABLE
-        movel   #0x01040100,%d0         /* invalidate whole cache */
-        movec   %d0,%CACR
-        nop
-        movel   #0x000fc000,%d0         /* set SDRAM cached only */
-        movec   %d0, %ACR0
-        movel   #0x00000000,%d0         /* no other regions cached */
-        movec   %d0, %ACR1
-        movel   #0x000fc000,%d0         /* set SDRAM cached only */
-        movec   %d0, %ACR2
-        movel   #0x00000000,%d0         /* no other regions cached */
-        movec   %d0, %ACR3
-        movel   #0xb6088400,%d0         /* enable caches */
-        movec   %d0,%CACR
-        nop
-.endm
-#endif /* CONFIG_M5407 */
-
-#if defined(CONFIG_M520x)
-.macro CACHE_ENABLE
-        move.l  #0x01000000,%d0         /* invalidate whole cache */
-        movec   %d0,%CACR
-        nop
-        move.l  #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
-        movec   %d0,%ACR0
-        move.l  #0x00000000,%d0         /* no other regions cached */
-        movec   %d0,%ACR1
-        move.l  #0x80400000,%d0         /* enable 8K instruction cache */
-        movec   %d0,%CACR
-        nop
-.endm
-#endif /* CONFIG_M520x */
-
-/****************************************************************************/
-#endif  /* __M68KNOMMU_MCFCACHE_H */
diff --git a/arch/m68knommu/include/asm/mcfdma.h b/arch/m68knommu/include/asm/mcfdma.h
deleted file mode 100644
index 705c52c79cd8..000000000000
--- a/arch/m68knommu/include/asm/mcfdma.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfdma.h -- Coldfire internal DMA support defines.
- *
- *      (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org)
- */
-
-/****************************************************************************/
-#ifndef mcfdma_h
-#define mcfdma_h
-/****************************************************************************/
-
-
-/*
- *      Get address specific defines for this Coldfire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFDMA_BASE0            0x200           /* Base address of DMA 0 */
-#define MCFDMA_BASE1            0x240           /* Base address of DMA 1 */
-#elif defined(CONFIG_M5272)
-#define MCFDMA_BASE0            0x0e0           /* Base address of DMA 0 */
-#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-/* These are relative to the IPSBAR, not MBAR */
-#define MCFDMA_BASE0            0x100           /* Base address of DMA 0 */
-#define MCFDMA_BASE1            0x140           /* Base address of DMA 1 */
-#define MCFDMA_BASE2            0x180           /* Base address of DMA 2 */
-#define MCFDMA_BASE3            0x1C0           /* Base address of DMA 3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFDMA_BASE0            0x300           /* Base address of DMA 0 */
-#define MCFDMA_BASE1            0x340           /* Base address of DMA 1 */
-#define MCFDMA_BASE2            0x380           /* Base address of DMA 2 */
-#define MCFDMA_BASE3            0x3C0           /* Base address of DMA 3 */
-#endif
-
-
-#if !defined(CONFIG_M5272)
-
-/*
- *      Define the DMA register set addresses.
- *      Note: these are longword registers, use unsigned long as data type
- */
-#define MCFDMA_SAR              0x00            /* DMA source address (r/w) */
-#define MCFDMA_DAR              0x01            /* DMA destination adr (r/w) */
-/* these are word registers, use unsigned short data type */
-#define MCFDMA_DCR              0x04            /* DMA control reg (r/w) */
-#define MCFDMA_BCR              0x06            /* DMA byte count reg (r/w) */
-/* these are byte registers, use unsiged char data type */
-#define MCFDMA_DSR              0x10            /* DMA status reg (r/w) */
-#define MCFDMA_DIVR             0x14            /* DMA interrupt vec (r/w) */
-
-/*
- *      Bit definitions for the DMA Control Register (DCR).
- */
-#define MCFDMA_DCR_INT          0x8000          /* Enable completion irq */
-#define MCFDMA_DCR_EEXT         0x4000          /* Enable external DMA req */
-#define MCFDMA_DCR_CS           0x2000          /* Enable cycle steal */
-#define MCFDMA_DCR_AA           0x1000          /* Enable auto alignment */
-#define MCFDMA_DCR_BWC_MASK     0x0E00          /* Bandwidth ctl mask */
-#define MCFDMA_DCR_BWC_512      0x0200          /* Bandwidth:   512 Bytes */
-#define MCFDMA_DCR_BWC_1024     0x0400          /* Bandwidth:  1024 Bytes */
-#define MCFDMA_DCR_BWC_2048     0x0600          /* Bandwidth:  2048 Bytes */
-#define MCFDMA_DCR_BWC_4096     0x0800          /* Bandwidth:  4096 Bytes */
-#define MCFDMA_DCR_BWC_8192     0x0a00          /* Bandwidth:  8192 Bytes */
-#define MCFDMA_DCR_BWC_16384    0x0c00          /* Bandwidth: 16384 Bytes */
-#define MCFDMA_DCR_BWC_32768    0x0e00          /* Bandwidth: 32768 Bytes */
-#define MCFDMA_DCR_SAA          0x0100          /* Single Address Access */
-#define MCFDMA_DCR_S_RW         0x0080          /* SAA read/write value */
-#define MCFDMA_DCR_SINC         0x0040          /* Source addr inc enable */
-#define MCFDMA_DCR_SSIZE_MASK   0x0030          /* Src xfer size */
-#define MCFDMA_DCR_SSIZE_LONG   0x0000          /* Src xfer size, 00 = longw */
-#define MCFDMA_DCR_SSIZE_BYTE   0x0010          /* Src xfer size, 01 = byte */
-#define MCFDMA_DCR_SSIZE_WORD   0x0020          /* Src xfer size, 10 = word */
-#define MCFDMA_DCR_SSIZE_LINE   0x0030          /* Src xfer size, 11 = line */
-#define MCFDMA_DCR_DINC         0x0008          /* Dest addr inc enable */
-#define MCFDMA_DCR_DSIZE_MASK   0x0006          /* Dest xfer size */
-#define MCFDMA_DCR_DSIZE_LONG   0x0000          /* Dest xfer size, 00 = long */
-#define MCFDMA_DCR_DSIZE_BYTE   0x0002          /* Dest xfer size, 01 = byte */
-#define MCFDMA_DCR_DSIZE_WORD   0x0004          /* Dest xfer size, 10 = word */
-#define MCFDMA_DCR_DSIZE_LINE   0x0006          /* Dest xfer size, 11 = line */
-#define MCFDMA_DCR_START        0x0001          /* Start transfer */
-
-/*
- *      Bit definitions for the DMA Status Register (DSR).
- */
-#define MCFDMA_DSR_CE           0x40            /* Config error */
-#define MCFDMA_DSR_BES          0x20            /* Bus Error on source */
-#define MCFDMA_DSR_BED          0x10            /* Bus Error on dest */
-#define MCFDMA_DSR_REQ          0x04            /* Requests remaining */
-#define MCFDMA_DSR_BSY          0x02            /* Busy */
-#define MCFDMA_DSR_DONE         0x01            /* DMA transfer complete */
-
-#else /* This is an MCF5272 */
-
-#define MCFDMA_DMR        0x00    /* Mode Register (r/w) */
-#define MCFDMA_DIR        0x03    /* Interrupt trigger register (r/w) */
-#define MCFDMA_DSAR       0x03    /* Source Address register (r/w) */
-#define MCFDMA_DDAR       0x04    /* Destination Address register (r/w) */
-#define MCFDMA_DBCR       0x02    /* Byte Count Register (r/w) */
-
-/* Bit definitions for the DMA Mode Register (DMR) */
-#define MCFDMA_DMR_RESET     0x80000000L /* Reset bit */
-#define MCFDMA_DMR_EN        0x40000000L /* DMA enable */
-#define MCFDMA_DMR_RQM       0x000C0000L /* Request Mode Mask */
-#define MCFDMA_DMR_RQM_DUAL  0x000C0000L /* Dual address mode, the only valid mode */
-#define MCFDMA_DMR_DSTM      0x00002000L /* Destination addressing mask */
-#define MCFDMA_DMR_DSTM_SA   0x00000000L /* Destination uses static addressing */
-#define MCFDMA_DMR_DSTM_IA   0x00002000L /* Destination uses incremental addressing */
-#define MCFDMA_DMR_DSTT_UD   0x00000400L /* Destination is user data */
-#define MCFDMA_DMR_DSTT_UC   0x00000800L /* Destination is user code */
-#define MCFDMA_DMR_DSTT_SD   0x00001400L /* Destination is supervisor data */
-#define MCFDMA_DMR_DSTT_SC   0x00001800L /* Destination is supervisor code */
-#define MCFDMA_DMR_DSTS_OFF  0x8         /* offset to the destination size bits */
-#define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */
-#define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */
-#define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */
-#define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */
-#define MCFDMA_DMR_SRCM      0x00000020L /* Source addressing mask */
-#define MCFDMA_DMR_SRCM_SA   0x00000000L /* Source uses static addressing */
-#define MCFDMA_DMR_SRCM_IA   0x00000020L /* Source uses incremental addressing */
-#define MCFDMA_DMR_SRCT_UD   0x00000004L /* Source is user data */
-#define MCFDMA_DMR_SRCT_UC   0x00000008L /* Source is user code */
-#define MCFDMA_DMR_SRCT_SD   0x00000014L /* Source is supervisor data */
-#define MCFDMA_DMR_SRCT_SC   0x00000018L /* Source is supervisor code */
-#define MCFDMA_DMR_SRCS_OFF  0x0         /* Offset to the source size bits */
-#define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */
-#define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */
-#define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */
-#define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */
-
-/* Bit definitions for the DMA interrupt register (DIR) */
-#define MCFDMA_DIR_INVEN     0x1000 /* Invalid Combination interrupt enable */
-#define MCFDMA_DIR_ASCEN     0x0800 /* Address Sequence Complete (Completion) interrupt enable */
-#define MCFDMA_DIR_TEEN      0x0200 /* Transfer Error interrupt enable */
-#define MCFDMA_DIR_TCEN      0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */
-#define MCFDMA_DIR_INV       0x0010 /* Invalid Combination */
-#define MCFDMA_DIR_ASC       0x0008 /* Address Sequence Complete (DMA Completion) */
-#define MCFDMA_DIR_TE        0x0002 /* Transfer Error */
-#define MCFDMA_DIR_TC        0x0001 /* Transfer Complete */
-
-#endif /* !defined(CONFIG_M5272) */ 
-
-/****************************************************************************/
-#endif  /* mcfdma_h */
diff --git a/arch/m68knommu/include/asm/mcfmbus.h b/arch/m68knommu/include/asm/mcfmbus.h
deleted file mode 100644
index 319899c47a2c..000000000000
--- a/arch/m68knommu/include/asm/mcfmbus.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfmbus.h -- Coldfire MBUS support defines.
- *
- *      (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) 
- */
-
-/****************************************************************************/
-
-
-#ifndef mcfmbus_h
-#define mcfmbus_h
-
-
-#define MCFMBUS_BASE            0x280
-#define MCFMBUS_IRQ_VECTOR      0x19
-#define MCFMBUS_IRQ             0x1
-#define MCFMBUS_CLK             0x3f
-#define MCFMBUS_IRQ_LEVEL       0x07    /*IRQ Level 1*/
-#define MCFMBUS_ADDRESS         0x01
-
-
-/*
-*       Define the 5307 MBUS register set addresses
-*/
-
-#define MCFMBUS_MADR    0x00
-#define MCFMBUS_MFDR    0x04
-#define MCFMBUS_MBCR    0x08
-#define MCFMBUS_MBSR    0x0C
-#define MCFMBUS_MBDR    0x10
-
-
-#define MCFMBUS_MADR_ADDR(a)    (((a)&0x7F)<<0x01) /*Slave Address*/
-
-#define MCFMBUS_MFDR_MBC(a)     ((a)&0x3F)         /*M-Bus Clock*/
-
-/*
-*       Define bit flags in Control Register
-*/
-
-#define MCFMBUS_MBCR_MEN           (0x80)  /* M-Bus Enable                 */
-#define MCFMBUS_MBCR_MIEN          (0x40)  /* M-Bus Interrupt Enable       */
-#define MCFMBUS_MBCR_MSTA          (0x20)  /* Master/Slave Mode Select Bit */
-#define MCFMBUS_MBCR_MTX           (0x10)  /* Transmit/Rcv Mode Select Bit */
-#define MCFMBUS_MBCR_TXAK          (0x08)  /* Transmit Acknowledge Enable  */
-#define MCFMBUS_MBCR_RSTA          (0x04)  /* Repeat Start                 */
-
-/*
-*       Define bit flags in Status Register
-*/
-
-#define MCFMBUS_MBSR_MCF           (0x80)  /* Data Transfer Complete       */
-#define MCFMBUS_MBSR_MAAS          (0x40)  /* Addressed as a Slave         */
-#define MCFMBUS_MBSR_MBB           (0x20)  /* Bus Busy                     */
-#define MCFMBUS_MBSR_MAL           (0x10)  /* Arbitration Lost             */
-#define MCFMBUS_MBSR_SRW           (0x04)  /* Slave Transmit               */
-#define MCFMBUS_MBSR_MIF           (0x02)  /* M-Bus Interrupt              */
-#define MCFMBUS_MBSR_RXAK          (0x01)  /* No Acknowledge Received      */
-
-/*
-*       Define bit flags in DATA I/O Register
-*/
-
-#define MCFMBUS_MBDR_READ          (0x01)  /* 1=read 0=write MBUS */
-
-#define MBUSIOCSCLOCK           1
-#define MBUSIOCGCLOCK           2
-#define MBUSIOCSADDR                    3
-#define MBUSIOCGADDR                    4
-#define MBUSIOCSSLADDR                  5
-#define MBUSIOCGSLADDR                  6
-#define MBUSIOCSSUBADDR                 7
-#define MBUSIOCGSUBADDR                 8
-
-#endif
diff --git a/arch/m68knommu/include/asm/mcfne.h b/arch/m68knommu/include/asm/mcfne.h
deleted file mode 100644
index 431f63aadd0e..000000000000
--- a/arch/m68knommu/include/asm/mcfne.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfne.h -- NE2000 in ColdFire eval boards.
- *
- *      (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000,      Lineo (www.lineo.com)
- *      (C) Copyright 2001,      SnapGear (www.snapgear.com)
- *
- *      19990409 David W. Miller  Converted from m5206ne.h for 5307 eval board
- *
- *      Hacked support for m5206e Cadre III evaluation board
- *      Fred Stevens (fred.stevens@pemstar.com) 13 April 1999
- */
-
-/****************************************************************************/
-#ifndef mcfne_h
-#define mcfne_h
-/****************************************************************************/
-
-
-/*
- *      Support for NE2000 clones devices in ColdFire based boards.
- *      Not all boards address these parts the same way, some use a
- *      direct addressing method, others use a side-band address space
- *      to access odd address registers, some require byte swapping
- *      others do not.
- */
-#define BSWAP(w)        (((w) << 8) | ((w) >> 8))
-#define RSWAP(w)        (w)
-
-
-/*
- *      Define the basic hardware resources of NE2000 boards.
- */
-
-#if defined(CONFIG_ARN5206)
-#define NE2000_ADDR             0x40000300
-#define NE2000_ODDOFFSET        0x00010000
-#define NE2000_IRQ_VECTOR       0xf0
-#define NE2000_IRQ_PRIORITY     2
-#define NE2000_IRQ_LEVEL        4
-#define NE2000_BYTE             volatile unsigned short
-#endif
-
-#if defined(CONFIG_M5206eC3)
-#define NE2000_ADDR             0x40000300
-#define NE2000_ODDOFFSET        0x00010000
-#define NE2000_IRQ_VECTOR       0x1c
-#define NE2000_IRQ_PRIORITY     2
-#define NE2000_IRQ_LEVEL        4
-#define NE2000_BYTE             volatile unsigned short
-#endif
-
-#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
-#define NE2000_ADDR             0x30000300
-#define NE2000_IRQ_VECTOR       25
-#define NE2000_IRQ_PRIORITY     1
-#define NE2000_IRQ_LEVEL        3
-#define NE2000_BYTE             volatile unsigned char
-#endif
-
-#if defined(CONFIG_M5307C3)
-#define NE2000_ADDR             0x40000300
-#define NE2000_ODDOFFSET        0x00010000
-#define NE2000_IRQ_VECTOR       0x1b
-#define NE2000_BYTE             volatile unsigned short
-#endif
-
-#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
-#define NE2000_ADDR             0x30600300
-#define NE2000_ODDOFFSET        0x00008000
-#define NE2000_IRQ_VECTOR       67
-#undef  BSWAP
-#define BSWAP(w)                (w)
-#define NE2000_BYTE             volatile unsigned short
-#undef  RSWAP
-#define RSWAP(w)                (((w) << 8) | ((w) >> 8))
-#endif
-
-#if defined(CONFIG_M5307) && defined(CONFIG_NETtel)
-#define NE2000_ADDR0            0x30600300
-#define NE2000_ADDR1            0x30800300
-#define NE2000_ODDOFFSET        0x00008000
-#define NE2000_IRQ_VECTOR0      27
-#define NE2000_IRQ_VECTOR1      29
-#undef  BSWAP
-#define BSWAP(w)                (w)
-#define NE2000_BYTE             volatile unsigned short
-#undef  RSWAP
-#define RSWAP(w)                (((w) << 8) | ((w) >> 8))
-#endif
-
-#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
-#define NE2000_ADDR             0x30600300
-#define NE2000_ODDOFFSET        0x00008000
-#define NE2000_IRQ_VECTOR       27
-#undef  BSWAP
-#define BSWAP(w)                (w)
-#define NE2000_BYTE             volatile unsigned short
-#undef  RSWAP
-#define RSWAP(w)                (((w) << 8) | ((w) >> 8))
-#endif
-
-#if defined(CONFIG_ARN5307)
-#define NE2000_ADDR             0xfe600300
-#define NE2000_ODDOFFSET        0x00010000
-#define NE2000_IRQ_VECTOR       0x1b
-#define NE2000_IRQ_PRIORITY     2
-#define NE2000_IRQ_LEVEL        3
-#define NE2000_BYTE             volatile unsigned short
-#endif
-
-#if defined(CONFIG_M5407C3)
-#define NE2000_ADDR             0x40000300
-#define NE2000_ODDOFFSET        0x00010000
-#define NE2000_IRQ_VECTOR       0x1b
-#define NE2000_BYTE             volatile unsigned short
-#endif
-
-/****************************************************************************/
-
-/*
- *      Side-band address space for odd address requires re-mapping
- *      many of the standard ISA access functions.
- */
-#ifdef NE2000_ODDOFFSET
-
-#undef outb
-#undef outb_p
-#undef inb
-#undef inb_p
-#undef outsb
-#undef outsw
-#undef insb
-#undef insw
-
-#define outb    ne2000_outb
-#define inb     ne2000_inb
-#define outb_p  ne2000_outb
-#define inb_p   ne2000_inb
-#define outsb   ne2000_outsb
-#define outsw   ne2000_outsw
-#define insb    ne2000_insb
-#define insw    ne2000_insw
-
-
-#ifndef COLDFIRE_NE2000_FUNCS
-
-void ne2000_outb(unsigned int val, unsigned int addr);
-int  ne2000_inb(unsigned int addr);
-void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len);
-void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len);
-void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len);
-void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len);
-
-#else
-
-/*
- *      This macro converts a conventional register address into the
- *      real memory pointer of the mapped NE2000 device.
- *      On most NE2000 implementations on ColdFire boards the chip is
- *      mapped in kinda funny, due to its ISA heritage.
- */
-#define NE2000_PTR(addr)        ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr))
-#define NE2000_DATA_PTR(addr)   (addr)
-
-
-void ne2000_outb(unsigned int val, unsigned int addr)
-{
-        NE2000_BYTE     *rp;
-
-        rp = (NE2000_BYTE *) NE2000_PTR(addr);
-        *rp = RSWAP(val);
-}
-
-int ne2000_inb(unsigned int addr)
-{
-        NE2000_BYTE     *rp, val;
-
-        rp = (NE2000_BYTE *) NE2000_PTR(addr);
-        val = *rp;
-        return((int) ((NE2000_BYTE) RSWAP(val)));
-}
-
-void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len)
-{
-        NE2000_BYTE     *rp, val;
-        unsigned char   *buf;
-
-        buf = (unsigned char *) vbuf;
-        rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                val = *rp;
-                *buf++ = RSWAP(val);
-        }
-}
-
-void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          w, *buf;
-
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                w = *rp;
-                *buf++ = BSWAP(w);
-        }
-}
-
-void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        NE2000_BYTE     *rp, val;
-        unsigned char   *buf;
-
-        buf = (unsigned char *) vbuf;
-        rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                val = *buf++;
-                *rp = RSWAP(val);
-        }
-}
-
-void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          w, *buf;
-
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                w = *buf++;
-                *rp = BSWAP(w);
-        }
-}
-
-#endif /* COLDFIRE_NE2000_FUNCS */
-#endif /* NE2000_OFFOFFSET */
-
-/****************************************************************************/
-
-#ifdef COLDFIRE_NE2000_FUNCS
-
-/*
- *      Lastly the interrupt set up code...
- *      Minor differences between the different board types.
- */
-
-#if defined(CONFIG_ARN5206)
-void ne2000_irqsetup(int irq)
-{
-        volatile unsigned char  *icrp;
-
-        icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
-        *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2;
-        mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
-}
-#endif
-
-#if defined(CONFIG_M5206eC3)
-void ne2000_irqsetup(int irq)
-{
-        volatile unsigned char  *icrp;
-
-        icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
-        *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2 | MCFSIM_ICR_AUTOVEC;
-        mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
-}
-#endif
-
-#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
-void ne2000_irqsetup(int irq)
-{
-        mcf_autovector(irq);
-}
-#endif
-
-#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
-void ne2000_irqsetup(int irq)
-{
-        volatile unsigned long  *icrp;
-        volatile unsigned long  *pitr;
-
-        /* The NE2000 device uses external IRQ3 */
-        icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
-        *icrp = (*icrp & 0x77077777) | 0x00d00000;
-
-        pitr = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PITR);
-        *pitr = *pitr | 0x20000000;
-}
-
-void ne2000_irqack(int irq)
-{
-        volatile unsigned long  *icrp;
-
-        /* The NE2000 device uses external IRQ3 */
-        icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
-        *icrp = (*icrp & 0x77777777) | 0x00800000;
-}
-#endif
-
-#if defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
-
-void ne2000_irqsetup(int irq)
-{
-        mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3);
-        mcf_autovector(irq);
-}
-
-#else
-
-void ne2000_irqsetup(int irq)
-{
-        mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3);
-}
-
-#endif /* ! CONFIG_NETtel || CONFIG_SECUREEDGEMP3 */
-#endif /* CONFIG_M5307 || CONFIG_M5407 */
-
-#endif /* COLDFIRE_NE2000_FUNCS */
-
-/****************************************************************************/
-#endif  /* mcfne_h */
diff --git a/arch/m68knommu/include/asm/mcfpci.h b/arch/m68knommu/include/asm/mcfpci.h
deleted file mode 100644
index f1507dd06ec6..000000000000
--- a/arch/m68knommu/include/asm/mcfpci.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfpci.h -- PCI bridge on ColdFire eval boards.
- *
- *      (C) Copyright 2000, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
- */
-
-/****************************************************************************/
-#ifndef mcfpci_h
-#define mcfpci_h
-/****************************************************************************/
-
-
-#ifdef CONFIG_PCI
-
-/*
- *      Address regions in the PCI address space are not mapped into the
- *      normal memory space of the ColdFire. They must be accessed via
- *      handler routines. This is easy for I/O space (inb/outb/etc) but
- *      needs some code changes to support ordinary memory. Interrupts
- *      also need to be vectored through the PCI handler first, then it
- *      will call the actual driver sub-handlers.
- */
-
-/*
- *      Un-define all the standard I/O access routines.
- */
-#undef  inb
-#undef  inw
-#undef  inl
-#undef  inb_p
-#undef  inw_p
-#undef  insb
-#undef  insw
-#undef  insl
-#undef  outb
-#undef  outw
-#undef  outl
-#undef  outb_p
-#undef  outw_p
-#undef  outsb
-#undef  outsw
-#undef  outsl
-
-#undef  request_irq
-#undef  free_irq
-
-#undef  bus_to_virt
-#undef  virt_to_bus
-
-
-/*
- *      Re-direct all I/O memory accesses functions to PCI specific ones.
- */
-#define inb     pci_inb
-#define inw     pci_inw
-#define inl     pci_inl
-#define inb_p   pci_inb
-#define inw_p   pci_inw
-#define insb    pci_insb
-#define insw    pci_insw
-#define insl    pci_insl
-
-#define outb    pci_outb
-#define outw    pci_outw
-#define outl    pci_outl
-#define outb_p  pci_outb
-#define outw_p  pci_outw
-#define outsb   pci_outsb
-#define outsw   pci_outsw
-#define outsl   pci_outsl
-
-#define request_irq     pci_request_irq
-#define free_irq        pci_free_irq
-
-#define virt_to_bus     pci_virt_to_bus
-#define bus_to_virt     pci_bus_to_virt
-
-#define CONFIG_COMEMPCI 1
-
-
-/*
- *      Prototypes of the real PCI functions (defined in bios32.c).
- */
-unsigned char   pci_inb(unsigned int addr);
-unsigned short  pci_inw(unsigned int addr);
-unsigned int    pci_inl(unsigned int addr);
-void            pci_insb(void *addr, void *buf, int len);
-void            pci_insw(void *addr, void *buf, int len);
-void            pci_insl(void *addr, void *buf, int len);
-
-void            pci_outb(unsigned char val, unsigned int addr);
-void            pci_outw(unsigned short val, unsigned int addr);
-void            pci_outl(unsigned int val, unsigned int addr);
-void            pci_outsb(void *addr, void *buf, int len);
-void            pci_outsw(void *addr, void *buf, int len);
-void            pci_outsl(void *addr, void *buf, int len);
-
-int             pci_request_irq(unsigned int irq,
-                        void (*handler)(int, void *, struct pt_regs *),
-                        unsigned long flags,
-                        const char *device,
-                        void *dev_id);
-void            pci_free_irq(unsigned int irq, void *dev_id);
-
-void            *pci_bmalloc(int size);
-void            pci_bmfree(void *bmp, int len);
-void            pci_copytoshmem(unsigned long bmp, void *src, int size);
-void            pci_copyfromshmem(void *dst, unsigned long bmp, int size);
-unsigned long   pci_virt_to_bus(volatile void *address);
-void            *pci_bus_to_virt(unsigned long address);
-void            pci_bmcpyto(void *dst, void *src, int len);
-void            pci_bmcpyfrom(void *dst, void *src, int len);
-
-#endif /* CONFIG_PCI */
-/****************************************************************************/
-#endif  /* mcfpci_h */
diff --git a/arch/m68knommu/include/asm/mcfpit.h b/arch/m68knommu/include/asm/mcfpit.h
deleted file mode 100644
index f570cf64fd29..000000000000
--- a/arch/m68knommu/include/asm/mcfpit.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfpit.h -- ColdFire internal PIT timer support defines.
- *
- *      (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
- */
-
-/****************************************************************************/
-#ifndef mcfpit_h
-#define mcfpit_h
-/****************************************************************************/
-
-
-/*
- *      Get address specific defines for the 5270/5271, 5280/5282, and 5208.
- */
-#if defined(CONFIG_M520x)
-#define MCFPIT_BASE1            0x00080000      /* Base address of TIMER1 */
-#define MCFPIT_BASE2            0x00084000      /* Base address of TIMER2 */
-#else
-#define MCFPIT_BASE1            0x00150000      /* Base address of TIMER1 */
-#define MCFPIT_BASE2            0x00160000      /* Base address of TIMER2 */
-#define MCFPIT_BASE3            0x00170000      /* Base address of TIMER3 */
-#define MCFPIT_BASE4            0x00180000      /* Base address of TIMER4 */
-#endif
-
-/*
- *      Define the PIT timer register set addresses.
- */
-#define MCFPIT_PCSR             0x0             /* PIT control register */
-#define MCFPIT_PMR              0x2             /* PIT modulus register */
-#define MCFPIT_PCNTR            0x4             /* PIT count register */
-
-/*
- *      Bit definitions for the PIT Control and Status register.
- */
-#define MCFPIT_PCSR_CLK1        0x0000          /* System clock divisor */
-#define MCFPIT_PCSR_CLK2        0x0100          /* System clock divisor */
-#define MCFPIT_PCSR_CLK4        0x0200          /* System clock divisor */
-#define MCFPIT_PCSR_CLK8        0x0300          /* System clock divisor */
-#define MCFPIT_PCSR_CLK16       0x0400          /* System clock divisor */
-#define MCFPIT_PCSR_CLK32       0x0500          /* System clock divisor */
-#define MCFPIT_PCSR_CLK64       0x0600          /* System clock divisor */
-#define MCFPIT_PCSR_CLK128      0x0700          /* System clock divisor */
-#define MCFPIT_PCSR_CLK256      0x0800          /* System clock divisor */
-#define MCFPIT_PCSR_CLK512      0x0900          /* System clock divisor */
-#define MCFPIT_PCSR_CLK1024     0x0a00          /* System clock divisor */
-#define MCFPIT_PCSR_CLK2048     0x0b00          /* System clock divisor */
-#define MCFPIT_PCSR_CLK4096     0x0c00          /* System clock divisor */
-#define MCFPIT_PCSR_CLK8192     0x0d00          /* System clock divisor */
-#define MCFPIT_PCSR_CLK16384    0x0e00          /* System clock divisor */
-#define MCFPIT_PCSR_CLK32768    0x0f00          /* System clock divisor */
-#define MCFPIT_PCSR_DOZE        0x0040          /* Clock run in doze mode */
-#define MCFPIT_PCSR_HALTED      0x0020          /* Clock run in halt mode */
-#define MCFPIT_PCSR_OVW         0x0010          /* Overwrite PIT counter now */
-#define MCFPIT_PCSR_PIE         0x0008          /* Enable PIT interrupt */
-#define MCFPIT_PCSR_PIF         0x0004          /* PIT interrupt flag */
-#define MCFPIT_PCSR_RLD         0x0002          /* Reload counter */
-#define MCFPIT_PCSR_EN          0x0001          /* Enable PIT */
-#define MCFPIT_PCSR_DISABLE     0x0000          /* Disable PIT */
-
-/****************************************************************************/
-#endif  /* mcfpit_h */
diff --git a/arch/m68knommu/include/asm/mcfsim.h b/arch/m68knommu/include/asm/mcfsim.h
deleted file mode 100644
index da3f2ceff3a4..000000000000
--- a/arch/m68knommu/include/asm/mcfsim.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfsim.h -- ColdFire System Integration Module support.
- *
- *      (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com) 
- */
-
-/****************************************************************************/
-#ifndef mcfsim_h
-#define mcfsim_h
-/****************************************************************************/
-
-
-/*
- *      Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282,
- *      5307 or 5407 specific addresses.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#include <asm/m5206sim.h>
-#elif defined(CONFIG_M520x)
-#include <asm/m520xsim.h>
-#elif defined(CONFIG_M523x)
-#include <asm/m523xsim.h>
-#elif defined(CONFIG_M5249)
-#include <asm/m5249sim.h>
-#elif defined(CONFIG_M527x)
-#include <asm/m527xsim.h>
-#elif defined(CONFIG_M5272)
-#include <asm/m5272sim.h>
-#elif defined(CONFIG_M528x)
-#include <asm/m528xsim.h>
-#elif defined(CONFIG_M5307)
-#include <asm/m5307sim.h>
-#elif defined(CONFIG_M532x)
-#include <asm/m532xsim.h>
-#elif defined(CONFIG_M5407)
-#include <asm/m5407sim.h>
-#endif
-
-
-/*
- *      Define the base address of the SIM within the MBAR address space.
- */
-#define MCFSIM_BASE             0x0             /* Base address of SIM */
-
-
-/*
- *      Bit definitions for the ICR family of registers.
- */
-#define MCFSIM_ICR_AUTOVEC      0x80            /* Auto-vectored intr */
-#define MCFSIM_ICR_LEVEL0       0x00            /* Level 0 intr */
-#define MCFSIM_ICR_LEVEL1       0x04            /* Level 1 intr */
-#define MCFSIM_ICR_LEVEL2       0x08            /* Level 2 intr */
-#define MCFSIM_ICR_LEVEL3       0x0c            /* Level 3 intr */
-#define MCFSIM_ICR_LEVEL4       0x10            /* Level 4 intr */
-#define MCFSIM_ICR_LEVEL5       0x14            /* Level 5 intr */
-#define MCFSIM_ICR_LEVEL6       0x18            /* Level 6 intr */
-#define MCFSIM_ICR_LEVEL7       0x1c            /* Level 7 intr */
-
-#define MCFSIM_ICR_PRI0         0x00            /* Priority 0 intr */
-#define MCFSIM_ICR_PRI1         0x01            /* Priority 1 intr */
-#define MCFSIM_ICR_PRI2         0x02            /* Priority 2 intr */
-#define MCFSIM_ICR_PRI3         0x03            /* Priority 3 intr */
-
-/*
- *      Bit definitions for the Interrupt Mask register (IMR).
- */
-#define MCFSIM_IMR_EINT1        0x0002          /* External intr # 1 */
-#define MCFSIM_IMR_EINT2        0x0004          /* External intr # 2 */
-#define MCFSIM_IMR_EINT3        0x0008          /* External intr # 3 */
-#define MCFSIM_IMR_EINT4        0x0010          /* External intr # 4 */
-#define MCFSIM_IMR_EINT5        0x0020          /* External intr # 5 */
-#define MCFSIM_IMR_EINT6        0x0040          /* External intr # 6 */
-#define MCFSIM_IMR_EINT7        0x0080          /* External intr # 7 */
-
-#define MCFSIM_IMR_SWD          0x0100          /* Software Watchdog intr */
-#define MCFSIM_IMR_TIMER1       0x0200          /* TIMER 1 intr */
-#define MCFSIM_IMR_TIMER2       0x0400          /* TIMER 2 intr */
-#define MCFSIM_IMR_MBUS         0x0800          /* MBUS intr    */
-#define MCFSIM_IMR_UART1        0x1000          /* UART 1 intr */
-#define MCFSIM_IMR_UART2        0x2000          /* UART 2 intr */
-
-#if defined(CONFIG_M5206e)
-#define MCFSIM_IMR_DMA1         0x4000          /* DMA 1 intr */
-#define MCFSIM_IMR_DMA2         0x8000          /* DMA 2 intr */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
-#define MCFSIM_IMR_DMA0         0x4000          /* DMA 0 intr */
-#define MCFSIM_IMR_DMA1         0x8000          /* DMA 1 intr */
-#define MCFSIM_IMR_DMA2         0x10000         /* DMA 2 intr */
-#define MCFSIM_IMR_DMA3         0x20000         /* DMA 3 intr */
-#endif
-
-/*
- *      Mask for all of the SIM devices. Some parts have more or less
- *      SIM devices. This is a catchall for the sandard set.
- */
-#ifndef MCFSIM_IMR_MASKALL
-#define MCFSIM_IMR_MASKALL      0x3ffe          /* All intr sources */
-#endif
-
-
-/*
- *      PIT interrupt settings, if not found in mXXXXsim.h file.
- */
-#ifndef ICR_INTRCONF
-#define ICR_INTRCONF            0x2b            /* PIT1 level 5, priority 3 */
-#endif
-#ifndef MCFPIT_IMR
-#define MCFPIT_IMR              MCFINTC_IMRH
-#endif
-#ifndef MCFPIT_IMR_IBIT
-#define MCFPIT_IMR_IBIT         (1 << (MCFINT_PIT1 - 32))
-#endif
-
-
-#ifndef __ASSEMBLY__
-/*
- *      Definition for the interrupt auto-vectoring support.
- */
-extern void     mcf_autovector(unsigned int vec);
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************/
-#endif  /* mcfsim_h */
diff --git a/arch/m68knommu/include/asm/mcfsmc.h b/arch/m68knommu/include/asm/mcfsmc.h
deleted file mode 100644
index 2d7a4dbd9683..000000000000
--- a/arch/m68knommu/include/asm/mcfsmc.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfsmc.h -- SMC ethernet support for ColdFire environments.
- *
- *      (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com) 
- */
-
-/****************************************************************************/
-#ifndef mcfsmc_h
-#define mcfsmc_h
-/****************************************************************************/
-
-/*
- *      None of the current ColdFire targets that use the SMC91x111
- *      allow 8 bit accesses. So this code is 16bit access only.
- */
-
-
-#undef  outb
-#undef  inb
-#undef  outw
-#undef  outwd
-#undef  inw     
-#undef  outl
-#undef  inl
-
-#undef  outsb
-#undef  outsw
-#undef  outsl
-#undef  insb
-#undef  insw
-#undef  insl
-
-/*
- *      Re-defines for ColdFire environment... The SMC part is
- *      mapped into memory space, so remap the PC-style in/out
- *      routines to handle that.
- */
-#define outb    smc_outb
-#define inb     smc_inb
-#define outw    smc_outw
-#define outwd   smc_outwd
-#define inw     smc_inw
-#define outl    smc_outl
-#define inl     smc_inl
-
-#define outsb   smc_outsb
-#define outsw   smc_outsw
-#define outsl   smc_outsl
-#define insb    smc_insb
-#define insw    smc_insw
-#define insl    smc_insl
-
-
-static inline int smc_inb(unsigned int addr)
-{
-        register unsigned short w;
-        w = *((volatile unsigned short *) (addr & ~0x1));
-        return(((addr & 0x1) ? w : (w >> 8)) & 0xff);
-}
-
-static inline void smc_outw(unsigned int val, unsigned int addr)
-{
-        *((volatile unsigned short *) addr) = (val << 8) | (val >> 8);
-}
-
-static inline int smc_inw(unsigned int addr)
-{
-        register unsigned short w;
-        w = *((volatile unsigned short *) addr);
-        return(((w << 8) | (w >> 8)) & 0xffff);
-}
-
-static inline void smc_outl(unsigned long val, unsigned int addr)
-{
-        *((volatile unsigned long *) addr) = 
-                ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) |
-                ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff);
-}
-
-static inline void smc_outwd(unsigned int val, unsigned int addr)
-{
-        *((volatile unsigned short *) addr) = val;
-}
-
-
-/*
- *      The rep* functions are used to feed the data port with
- *      raw data. So we do not byte swap them when copying.
- */
-
-static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          *buf, *ebuf;
-
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) addr;
-
-        /* Copy as words for as long as possible */
-        for (ebuf = buf + (len >> 1); (buf < ebuf); )
-                *buf++ = *rp;
-
-        /* Lastly, handle left over byte */
-        if (len & 0x1)
-                *((unsigned char *) buf) = (*rp >> 8) & 0xff;
-}
-
-static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          *buf, *ebuf;
-
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) addr;
-        for (ebuf = buf + len; (buf < ebuf); )
-                *buf++ = *rp;
-}
-
-static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len)
-{
-        volatile unsigned long  *rp;
-        unsigned long           *buf, *ebuf;
-
-        buf = (unsigned long *) vbuf;
-        rp = (volatile unsigned long *) addr;
-        for (ebuf = buf + len; (buf < ebuf); )
-                *buf++ = *rp;
-}
-
-static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          *buf, *ebuf;
-
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) addr;
-        for (ebuf = buf + len; (buf < ebuf); )
-                *rp = *buf++;
-}
-
-static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len)
-{
-        volatile unsigned long  *rp;
-        unsigned long           *buf, *ebuf;
-
-        buf = (unsigned long *) vbuf;
-        rp = (volatile unsigned long *) addr;
-        for (ebuf = buf + len; (buf < ebuf); )
-                *rp = *buf++;
-}
-
-
-#ifdef CONFIG_NETtel
-/*
- *      Re-map the address space of at least one of the SMC ethernet
- *      parts. Both parts power up decoding the same address, so we
- *      need to move one of them first, before doing enything else.
- *
- *      We also increase the number of wait states for this part by one.
- */
-
-void smc_remap(unsigned int ioaddr)
-{
-        static int              once = 0;
-        extern unsigned short   ppdata;
-        if (once++ == 0) {
-                *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADDR)) = 0x00ec;
-                ppdata |= 0x0080;
-                *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata;
-                outw(0x0001, ioaddr + BANK_SELECT);
-                outw(0x0001, ioaddr + BANK_SELECT);
-                outw(0x0067, ioaddr + BASE);
-
-                ppdata &= ~0x0080;
-                *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata;
-        }
-        
-        *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180;
-}
-
-#endif
-
-/****************************************************************************/
-#endif  /* mcfsmc_h */
diff --git a/arch/m68knommu/include/asm/mcftimer.h b/arch/m68knommu/include/asm/mcftimer.h
deleted file mode 100644
index 0f90f6d2227a..000000000000
--- a/arch/m68knommu/include/asm/mcftimer.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcftimer.h -- ColdFire internal TIMER support defines.
- *
- *      (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com) 
- */
-
-/****************************************************************************/
-#ifndef mcftimer_h
-#define mcftimer_h
-/****************************************************************************/
-
-
-/*
- *      Get address specific defines for this ColdFire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFTIMER_BASE1          0x100           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0x120           /* Base address of TIMER2 */
-#elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1          0x200           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0x220           /* Base address of TIMER2 */
-#define MCFTIMER_BASE3          0x240           /* Base address of TIMER4 */
-#define MCFTIMER_BASE4          0x260           /* Base address of TIMER3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1          0x140           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0x180           /* Base address of TIMER2 */
-#elif defined(CONFIG_M532x)
-#define MCFTIMER_BASE1          0xfc070000      /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0xfc074000      /* Base address of TIMER2 */
-#define MCFTIMER_BASE3          0xfc078000      /* Base address of TIMER3 */
-#define MCFTIMER_BASE4          0xfc07c000      /* Base address of TIMER4 */
-#endif
-
-
-/*
- *      Define the TIMER register set addresses.
- */
-#define MCFTIMER_TMR            0x00            /* Timer Mode reg (r/w) */
-#define MCFTIMER_TRR            0x04            /* Timer Reference (r/w) */
-#define MCFTIMER_TCR            0x08            /* Timer Capture reg (r/w) */
-#define MCFTIMER_TCN            0x0C            /* Timer Counter reg (r/w) */
-#if defined(CONFIG_M532x)
-#define MCFTIMER_TER            0x03            /* Timer Event reg (r/w) */
-#else
-#define MCFTIMER_TER            0x11            /* Timer Event reg (r/w) */
-#endif
-
-/*
- *      Bit definitions for the Timer Mode Register (TMR).
- *      Register bit flags are common accross ColdFires.
- */
-#define MCFTIMER_TMR_PREMASK    0xff00          /* Prescalar mask */
-#define MCFTIMER_TMR_DISCE      0x0000          /* Disable capture */
-#define MCFTIMER_TMR_ANYCE      0x00c0          /* Capture any edge */
-#define MCFTIMER_TMR_FALLCE     0x0080          /* Capture fallingedge */
-#define MCFTIMER_TMR_RISECE     0x0040          /* Capture rising edge */
-#define MCFTIMER_TMR_ENOM       0x0020          /* Enable output toggle */
-#define MCFTIMER_TMR_DISOM      0x0000          /* Do single output pulse  */
-#define MCFTIMER_TMR_ENORI      0x0010          /* Enable ref interrupt */
-#define MCFTIMER_TMR_DISORI     0x0000          /* Disable ref interrupt */
-#define MCFTIMER_TMR_RESTART    0x0008          /* Restart counter */
-#define MCFTIMER_TMR_FREERUN    0x0000          /* Free running counter */
-#define MCFTIMER_TMR_CLKTIN     0x0006          /* Input clock is TIN */
-#define MCFTIMER_TMR_CLK16      0x0004          /* Input clock is /16 */
-#define MCFTIMER_TMR_CLK1       0x0002          /* Input clock is /1 */
-#define MCFTIMER_TMR_CLKSTOP    0x0000          /* Stop counter */
-#define MCFTIMER_TMR_ENABLE     0x0001          /* Enable timer */
-#define MCFTIMER_TMR_DISABLE    0x0000          /* Disable timer */
-
-/*
- *      Bit definitions for the Timer Event Registers (TER).
- */
-#define MCFTIMER_TER_CAP        0x01            /* Capture event */
-#define MCFTIMER_TER_REF        0x02            /* Refernece event */
-
-/****************************************************************************/
-#endif  /* mcftimer_h */
diff --git a/arch/m68knommu/include/asm/mcfuart.h b/arch/m68knommu/include/asm/mcfuart.h
deleted file mode 100644
index ef2293873612..000000000000
--- a/arch/m68knommu/include/asm/mcfuart.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfuart.h -- ColdFire internal UART support defines.
- *
- *      (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com) 
- */
-
-/****************************************************************************/
-#ifndef mcfuart_h
-#define mcfuart_h
-/****************************************************************************/
-
-/*
- *      Define the base address of the UARTS within the MBAR address
- *      space.
- */
-#if defined(CONFIG_M5272)
-#define MCFUART_BASE1           0x100           /* Base address of UART1 */
-#define MCFUART_BASE2           0x140           /* Base address of UART2 */
-#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#if defined(CONFIG_NETtel)
-#define MCFUART_BASE1           0x180           /* Base address of UART1 */
-#define MCFUART_BASE2           0x140           /* Base address of UART2 */
-#else
-#define MCFUART_BASE1           0x140           /* Base address of UART1 */
-#define MCFUART_BASE2           0x180           /* Base address of UART2 */
-#endif
-#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-#define MCFUART_BASE1           0x200           /* Base address of UART1 */
-#define MCFUART_BASE2           0x240           /* Base address of UART2 */
-#define MCFUART_BASE3           0x280           /* Base address of UART3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
-#define MCFUART_BASE1           0x200           /* Base address of UART1 */
-#define MCFUART_BASE2           0x1c0           /* Base address of UART2 */
-#else
-#define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
-#define MCFUART_BASE2           0x200           /* Base address of UART2 */
-#endif
-#elif defined(CONFIG_M520x)
-#define MCFUART_BASE1           0x60000         /* Base address of UART1 */
-#define MCFUART_BASE2           0x64000         /* Base address of UART2 */
-#define MCFUART_BASE3           0x68000         /* Base address of UART2 */
-#elif defined(CONFIG_M532x)
-#define MCFUART_BASE1           0xfc060000      /* Base address of UART1 */
-#define MCFUART_BASE2           0xfc064000      /* Base address of UART2 */
-#define MCFUART_BASE3           0xfc068000      /* Base address of UART3 */
-#endif
-
-
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-
-struct mcf_platform_uart {
-        unsigned long   mapbase;        /* Physical address base */
-        void __iomem    *membase;       /* Virtual address if mapped */
-        unsigned int    irq;            /* Interrupt vector */
-        unsigned int    uartclk;        /* UART clock rate */
-};
-
-/*
- *      Define the ColdFire UART register set addresses.
- */
-#define MCFUART_UMR             0x00            /* Mode register (r/w) */
-#define MCFUART_USR             0x04            /* Status register (r) */
-#define MCFUART_UCSR            0x04            /* Clock Select (w) */
-#define MCFUART_UCR             0x08            /* Command register (w) */
-#define MCFUART_URB             0x0c            /* Receiver Buffer (r) */
-#define MCFUART_UTB             0x0c            /* Transmit Buffer (w) */
-#define MCFUART_UIPCR           0x10            /* Input Port Change (r) */
-#define MCFUART_UACR            0x10            /* Auxiliary Control (w) */
-#define MCFUART_UISR            0x14            /* Interrupt Status (r) */
-#define MCFUART_UIMR            0x14            /* Interrupt Mask (w) */
-#define MCFUART_UBG1            0x18            /* Baud Rate MSB (r/w) */
-#define MCFUART_UBG2            0x1c            /* Baud Rate LSB (r/w) */
-#ifdef  CONFIG_M5272
-#define MCFUART_UTF             0x28            /* Transmitter FIFO (r/w) */
-#define MCFUART_URF             0x2c            /* Receiver FIFO (r/w) */
-#define MCFUART_UFPD            0x30            /* Frac Prec. Divider (r/w) */
-#else
-#define MCFUART_UIVR            0x30            /* Interrupt Vector (r/w) */
-#endif
-#define MCFUART_UIPR            0x34            /* Input Port (r) */
-#define MCFUART_UOP1            0x38            /* Output Port Bit Set (w) */
-#define MCFUART_UOP0            0x3c            /* Output Port Bit Reset (w) */
-
-
-/*
- *      Define bit flags in Mode Register 1 (MR1).
- */
-#define MCFUART_MR1_RXRTS       0x80            /* Auto RTS flow control */
-#define MCFUART_MR1_RXIRQFULL   0x40            /* RX IRQ type FULL */
-#define MCFUART_MR1_RXIRQRDY    0x00            /* RX IRQ type RDY */
-#define MCFUART_MR1_RXERRBLOCK  0x20            /* RX block error mode */
-#define MCFUART_MR1_RXERRCHAR   0x00            /* RX char error mode */
-
-#define MCFUART_MR1_PARITYNONE  0x10            /* No parity */
-#define MCFUART_MR1_PARITYEVEN  0x00            /* Even parity */
-#define MCFUART_MR1_PARITYODD   0x04            /* Odd parity */
-#define MCFUART_MR1_PARITYSPACE 0x08            /* Space parity */
-#define MCFUART_MR1_PARITYMARK  0x0c            /* Mark parity */
-
-#define MCFUART_MR1_CS5         0x00            /* 5 bits per char */
-#define MCFUART_MR1_CS6         0x01            /* 6 bits per char */
-#define MCFUART_MR1_CS7         0x02            /* 7 bits per char */
-#define MCFUART_MR1_CS8         0x03            /* 8 bits per char */
-
-/*
- *      Define bit flags in Mode Register 2 (MR2).
- */
-#define MCFUART_MR2_LOOPBACK    0x80            /* Loopback mode */
-#define MCFUART_MR2_REMOTELOOP  0xc0            /* Remote loopback mode */
-#define MCFUART_MR2_AUTOECHO    0x40            /* Automatic echo */
-#define MCFUART_MR2_TXRTS       0x20            /* Assert RTS on TX */
-#define MCFUART_MR2_TXCTS       0x10            /* Auto CTS flow control */
-
-#define MCFUART_MR2_STOP1       0x07            /* 1 stop bit */
-#define MCFUART_MR2_STOP15      0x08            /* 1.5 stop bits */
-#define MCFUART_MR2_STOP2       0x0f            /* 2 stop bits */
-
-/*
- *      Define bit flags in Status Register (USR).
- */
-#define MCFUART_USR_RXBREAK     0x80            /* Received BREAK */
-#define MCFUART_USR_RXFRAMING   0x40            /* Received framing error */
-#define MCFUART_USR_RXPARITY    0x20            /* Received parity error */
-#define MCFUART_USR_RXOVERRUN   0x10            /* Received overrun error */
-#define MCFUART_USR_TXEMPTY     0x08            /* Transmitter empty */
-#define MCFUART_USR_TXREADY     0x04            /* Transmitter ready */
-#define MCFUART_USR_RXFULL      0x02            /* Receiver full */
-#define MCFUART_USR_RXREADY     0x01            /* Receiver ready */
-
-#define MCFUART_USR_RXERR       (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
-                                MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
-
-/*
- *      Define bit flags in Clock Select Register (UCSR).
- */
-#define MCFUART_UCSR_RXCLKTIMER 0xd0            /* RX clock is timer */
-#define MCFUART_UCSR_RXCLKEXT16 0xe0            /* RX clock is external x16 */
-#define MCFUART_UCSR_RXCLKEXT1  0xf0            /* RX clock is external x1 */
-
-#define MCFUART_UCSR_TXCLKTIMER 0x0d            /* TX clock is timer */
-#define MCFUART_UCSR_TXCLKEXT16 0x0e            /* TX clock is external x16 */
-#define MCFUART_UCSR_TXCLKEXT1  0x0f            /* TX clock is external x1 */
-
-/*
- *      Define bit flags in Command Register (UCR).
- */
-#define MCFUART_UCR_CMDNULL             0x00    /* No command */
-#define MCFUART_UCR_CMDRESETMRPTR       0x10    /* Reset MR pointer */
-#define MCFUART_UCR_CMDRESETRX          0x20    /* Reset receiver */
-#define MCFUART_UCR_CMDRESETTX          0x30    /* Reset transmitter */
-#define MCFUART_UCR_CMDRESETERR         0x40    /* Reset error status */
-#define MCFUART_UCR_CMDRESETBREAK       0x50    /* Reset BREAK change */
-#define MCFUART_UCR_CMDBREAKSTART       0x60    /* Start BREAK */
-#define MCFUART_UCR_CMDBREAKSTOP        0x70    /* Stop BREAK */
-
-#define MCFUART_UCR_TXNULL      0x00            /* No TX command */
-#define MCFUART_UCR_TXENABLE    0x04            /* Enable TX */
-#define MCFUART_UCR_TXDISABLE   0x08            /* Disable TX */
-#define MCFUART_UCR_RXNULL      0x00            /* No RX command */
-#define MCFUART_UCR_RXENABLE    0x01            /* Enable RX */
-#define MCFUART_UCR_RXDISABLE   0x02            /* Disable RX */
-
-/*
- *      Define bit flags in Input Port Change Register (UIPCR).
- */
-#define MCFUART_UIPCR_CTSCOS    0x10            /* CTS change of state */
-#define MCFUART_UIPCR_CTS       0x01            /* CTS value */
-
-/*
- *      Define bit flags in Input Port Register (UIP).
- */
-#define MCFUART_UIPR_CTS        0x01            /* CTS value */
-
-/*
- *      Define bit flags in Output Port Registers (UOP).
- *      Clear bit by writing to UOP0, set by writing to UOP1.
- */
-#define MCFUART_UOP_RTS         0x01            /* RTS set or clear */
-
-/*
- *      Define bit flags in the Auxiliary Control Register (UACR).
- */
-#define MCFUART_UACR_IEC        0x01            /* Input enable control */
-
-/*
- *      Define bit flags in Interrupt Status Register (UISR).
- *      These same bits are used for the Interrupt Mask Register (UIMR).
- */
-#define MCFUART_UIR_COS         0x80            /* Change of state (CTS) */
-#define MCFUART_UIR_DELTABREAK  0x04            /* Break start or stop */
-#define MCFUART_UIR_RXREADY     0x02            /* Receiver ready */
-#define MCFUART_UIR_TXREADY     0x01            /* Transmitter ready */
-
-#ifdef  CONFIG_M5272
-/*
- *      Define bit flags in the Transmitter FIFO Register (UTF).
- */
-#define MCFUART_UTF_TXB         0x1f            /* Transmitter data level */
-#define MCFUART_UTF_FULL        0x20            /* Transmitter fifo full */
-#define MCFUART_UTF_TXS         0xc0            /* Transmitter status */
-
-/*
- *      Define bit flags in the Receiver FIFO Register (URF).
- */
-#define MCFUART_URF_RXB         0x1f            /* Receiver data level */
-#define MCFUART_URF_FULL        0x20            /* Receiver fifo full */
-#define MCFUART_URF_RXS         0xc0            /* Receiver status */
-#endif
-
-/****************************************************************************/
-#endif  /* mcfuart_h */
diff --git a/arch/m68knommu/include/asm/mcfwdebug.h b/arch/m68knommu/include/asm/mcfwdebug.h
deleted file mode 100644
index 27f70e45d700..000000000000
--- a/arch/m68knommu/include/asm/mcfwdebug.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfdebug.h -- ColdFire Debug Module support.
- *
- *      (C) Copyright 2001, Lineo Inc. (www.lineo.com) 
- */
-
-/****************************************************************************/
-#ifndef mcfdebug_h
-#define mcfdebug_h
-/****************************************************************************/
-
-/* Define the debug module registers */
-#define MCFDEBUG_CSR    0x0                     /* Configuration status         */
-#define MCFDEBUG_BAAR   0x5                     /* BDM address attribute        */
-#define MCFDEBUG_AATR   0x6                     /* Address attribute trigger    */
-#define MCFDEBUG_TDR    0x7                     /* Trigger definition           */
-#define MCFDEBUG_PBR    0x8                     /* PC breakpoint                */
-#define MCFDEBUG_PBMR   0x9                     /* PC breakpoint mask           */
-#define MCFDEBUG_ABHR   0xc                     /* High address breakpoint      */
-#define MCFDEBUG_ABLR   0xd                     /* Low address breakpoint       */
-#define MCFDEBUG_DBR    0xe                     /* Data breakpoint              */
-#define MCFDEBUG_DBMR   0xf                     /* Data breakpoint mask         */
-
-/* Define some handy constants for the trigger definition register */
-#define MCFDEBUG_TDR_TRC_DISP   0x00000000      /* display on DDATA only        */
-#define MCFDEBUG_TDR_TRC_HALT   0x40000000      /* Processor halt on BP         */
-#define MCFDEBUG_TDR_TRC_INTR   0x80000000      /* Debug intr on BP             */
-#define MCFDEBUG_TDR_LXT1       0x00004000      /* TDR level 1                  */
-#define MCFDEBUG_TDR_LXT2       0x00008000      /* TDR level 2                  */
-#define MCFDEBUG_TDR_EBL1       0x00002000      /* Enable breakpoint level 1    */
-#define MCFDEBUG_TDR_EBL2       0x20000000      /* Enable breakpoint level 2    */
-#define MCFDEBUG_TDR_EDLW1      0x00001000      /* Enable data BP longword      */
-#define MCFDEBUG_TDR_EDLW2      0x10000000
-#define MCFDEBUG_TDR_EDWL1      0x00000800      /* Enable data BP lower word    */
-#define MCFDEBUG_TDR_EDWL2      0x08000000
-#define MCFDEBUG_TDR_EDWU1      0x00000400      /* Enable data BP upper word    */
-#define MCFDEBUG_TDR_EDWU2      0x04000000
-#define MCFDEBUG_TDR_EDLL1      0x00000200      /* Enable data BP low low byte  */
-#define MCFDEBUG_TDR_EDLL2      0x02000000
-#define MCFDEBUG_TDR_EDLM1      0x00000100      /* Enable data BP low mid byte  */
-#define MCFDEBUG_TDR_EDLM2      0x01000000
-#define MCFDEBUG_TDR_EDUM1      0x00000080      /* Enable data BP up mid byte   */
-#define MCFDEBUG_TDR_EDUM2      0x00800000
-#define MCFDEBUG_TDR_EDUU1      0x00000040      /* Enable data BP up up byte    */
-#define MCFDEBUG_TDR_EDUU2      0x00400000
-#define MCFDEBUG_TDR_DI1        0x00000020      /* Data BP invert               */
-#define MCFDEBUG_TDR_DI2        0x00200000
-#define MCFDEBUG_TDR_EAI1       0x00000010      /* Enable address BP inverted   */
-#define MCFDEBUG_TDR_EAI2       0x00100000
-#define MCFDEBUG_TDR_EAR1       0x00000008      /* Enable address BP range      */
-#define MCFDEBUG_TDR_EAR2       0x00080000
-#define MCFDEBUG_TDR_EAL1       0x00000004      /* Enable address BP low        */
-#define MCFDEBUG_TDR_EAL2       0x00040000
-#define MCFDEBUG_TDR_EPC1       0x00000002      /* Enable PC BP                 */
-#define MCFDEBUG_TDR_EPC2       0x00020000
-#define MCFDEBUG_TDR_PCI1       0x00000001      /* PC BP invert                 */
-#define MCFDEBUG_TDR_PCI2       0x00010000
-
-/* Constants for the address attribute trigger register */
-#define MCFDEBUG_AAR_RESET      0x00000005
-/* Fields not yet implemented */
-
-/* And some definitions for the writable sections of the CSR */
-#define MCFDEBUG_CSR_RESET      0x00100000
-#define MCFDEBUG_CSR_PSTCLK     0x00020000      /* PSTCLK disable               */
-#define MCFDEBUG_CSR_IPW        0x00010000      /* Inhibit processor writes     */
-#define MCFDEBUG_CSR_MAP        0x00008000      /* Processor refs in emul mode  */
-#define MCFDEBUG_CSR_TRC        0x00004000      /* Emul mode on trace exception */
-#define MCFDEBUG_CSR_EMU        0x00002000      /* Force emulation mode         */
-#define MCFDEBUG_CSR_DDC_READ   0x00000800      /* Debug data control           */
-#define MCFDEBUG_CSR_DDC_WRITE  0x00001000
-#define MCFDEBUG_CSR_UHE        0x00000400      /* User mode halt enable        */
-#define MCFDEBUG_CSR_BTB0       0x00000000      /* Branch target 0 bytes        */
-#define MCFDEBUG_CSR_BTB2       0x00000100      /* Branch target 2 bytes        */
-#define MCFDEBUG_CSR_BTB3       0x00000200      /* Branch target 3 bytes        */
-#define MCFDEBUG_CSR_BTB4       0x00000300      /* Branch target 4 bytes        */
-#define MCFDEBUG_CSR_NPL        0x00000040      /* Non-pipelined mode           */
-#define MCFDEBUG_CSR_SSM        0x00000010      /* Single step mode             */
-
-/* Constants for the BDM address attribute register */
-#define MCFDEBUG_BAAR_RESET     0x00000005
-/* Fields not yet implemented */
-
-
-/* This routine wrappers up the wdebug asm instruction so that the register
- * and value can be relatively easily specified.  The biggest hassle here is
- * that the debug module instructions (2 longs) must be long word aligned and
- * some pointer fiddling is performed to ensure this.
- */
-static inline void wdebug(int reg, unsigned long data) {
-        unsigned short dbg_spc[6];
-        unsigned short *dbg;
-
-        // Force alignment to long word boundary
-        dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc);
-
-        // Build up the debug instruction
-        dbg[0] = 0x2c80 | (reg & 0xf);
-        dbg[1] = (data >> 16) & 0xffff;
-        dbg[2] = data & 0xffff;
-        dbg[3] = 0;
-
-        // Perform the wdebug instruction
-#if 0
-        // This strain is for gas which doesn't have the wdebug instructions defined
-        asm(    "move.l %0, %%a0\n\t"
-                ".word  0xfbd0\n\t"
-                ".word  0x0003\n\t"
-            :: "g" (dbg) : "a0");
-#else
-        // And this is for when it does
-        asm(    "wdebug (%0)" :: "a" (dbg));
-#endif
-}
-
-#endif
diff --git a/arch/m68knommu/include/asm/md.h b/arch/m68knommu/include/asm/md.h
deleted file mode 100644
index d810c78de5ff..000000000000
--- a/arch/m68knommu/include/asm/md.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/md.h>
diff --git a/arch/m68knommu/include/asm/mman.h b/arch/m68knommu/include/asm/mman.h
deleted file mode 100644
index 4846c682efed..000000000000
--- a/arch/m68knommu/include/asm/mman.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/mman.h>
diff --git a/arch/m68knommu/include/asm/mmu.h b/arch/m68knommu/include/asm/mmu.h
deleted file mode 100644
index e2da1e6f09fe..000000000000
--- a/arch/m68knommu/include/asm/mmu.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __M68KNOMMU_MMU_H
-#define __M68KNOMMU_MMU_H
-
-/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
-
-typedef struct {
-        unsigned long           end_brk;
-} mm_context_t;
-
-#endif /* __M68KNOMMU_MMU_H */
diff --git a/arch/m68knommu/include/asm/mmu_context.h b/arch/m68knommu/include/asm/mmu_context.h
deleted file mode 100644
index 9ccee4278c97..000000000000
--- a/arch/m68knommu/include/asm/mmu_context.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __M68KNOMMU_MMU_CONTEXT_H
-#define __M68KNOMMU_MMU_CONTEXT_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm-generic/mm_hooks.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-        // mm->context = virt_to_phys(mm->pgd);
-        return(0);
-}
-
-#define destroy_context(mm)             do { } while(0)
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
-{
-}
-
-#define deactivate_mm(tsk,mm)   do { } while (0)
-
-static inline void activate_mm(struct mm_struct *prev_mm,
-                               struct mm_struct *next_mm)
-{
-}
-
-#endif
diff --git a/arch/m68knommu/include/asm/module.h b/arch/m68knommu/include/asm/module.h
deleted file mode 100644
index 2e45ab50b232..000000000000
--- a/arch/m68knommu/include/asm/module.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef ASM_M68KNOMMU_MODULE_H
-#define ASM_M68KNOMMU_MODULE_H
-
-struct mod_arch_specific {
-};
-
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-
-#endif /* ASM_M68KNOMMU_MODULE_H */
diff --git a/arch/m68knommu/include/asm/movs.h b/arch/m68knommu/include/asm/movs.h
deleted file mode 100644
index 81a16779e833..000000000000
--- a/arch/m68knommu/include/asm/movs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/movs.h>
diff --git a/arch/m68knommu/include/asm/msgbuf.h b/arch/m68knommu/include/asm/msgbuf.h
deleted file mode 100644
index bdfadec4d52d..000000000000
--- a/arch/m68knommu/include/asm/msgbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/msgbuf.h>
diff --git a/arch/m68knommu/include/asm/mutex.h b/arch/m68knommu/include/asm/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/arch/m68knommu/include/asm/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/arch/m68knommu/include/asm/nettel.h b/arch/m68knommu/include/asm/nettel.h
deleted file mode 100644
index 0299f6a2deeb..000000000000
--- a/arch/m68knommu/include/asm/nettel.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/****************************************************************************/
-
-/*
- *      nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
- *
- *      (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
- *      (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com) 
- *      (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com) 
- */
-
-/****************************************************************************/
-#ifndef nettel_h
-#define nettel_h
-/****************************************************************************/
-
-
-/****************************************************************************/
-#ifdef CONFIG_NETtel
-/****************************************************************************/
-
-#ifdef CONFIG_COLDFIRE
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#endif
-
-/*---------------------------------------------------------------------------*/
-#if defined(CONFIG_M5307)
-/*
- *      NETtel/5307 based hardware first. DTR/DCD lines are wired to
- *      GPIO lines. Most of the LED's are driver through a latch
- *      connected to CS2.
- */
-#define MCFPP_DCD1      0x0001
-#define MCFPP_DCD0      0x0002
-#define MCFPP_DTR1      0x0004
-#define MCFPP_DTR0      0x0008
-
-#define NETtel_LEDADDR  0x30400000
-
-#ifndef __ASSEMBLY__
-
-extern volatile unsigned short ppdata;
-
-/*
- *      These functions defined to give quasi generic access to the
- *      PPIO bits used for DTR/DCD.
- */
-static __inline__ unsigned int mcf_getppdata(void)
-{
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT);
-        return((unsigned int) *pp);
-}
-
-static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
-{
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT);
-        ppdata = (ppdata & ~mask) | bits;
-        *pp = ppdata;
-}
-#endif
-
-/*---------------------------------------------------------------------------*/
-#elif defined(CONFIG_M5206e)
-/*
- *      NETtel/5206e based hardware has leds on latch on CS3.
- *      No support modem for lines??
- */
-#define NETtel_LEDADDR  0x50000000
-
-/*---------------------------------------------------------------------------*/
-#elif defined(CONFIG_M5272)
-/*
- *      NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines.
- */
-#define MCFPP_DCD0      0x0080
-#define MCFPP_DCD1      0x0000          /* Port 1 no DCD support */
-#define MCFPP_DTR0      0x0040
-#define MCFPP_DTR1      0x0000          /* Port 1 no DTR support */
-
-#ifndef __ASSEMBLY__
-/*
- *      These functions defined to give quasi generic access to the
- *      PPIO bits used for DTR/DCD.
- */
-static __inline__ unsigned int mcf_getppdata(void)
-{
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        return((unsigned int) *pp);
-}
-
-static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
-{
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        *pp = (*pp & ~mask) | bits;
-}
-#endif
-
-#endif
-/*---------------------------------------------------------------------------*/
-
-/****************************************************************************/
-#endif /* CONFIG_NETtel */
-/****************************************************************************/
-#endif  /* nettel_h */
diff --git a/arch/m68knommu/include/asm/openprom.h b/arch/m68knommu/include/asm/openprom.h
deleted file mode 100644
index fdba7953ff9f..000000000000
--- a/arch/m68knommu/include/asm/openprom.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/openprom.h>
diff --git a/arch/m68knommu/include/asm/oplib.h b/arch/m68knommu/include/asm/oplib.h
deleted file mode 100644
index ce079dc332d9..000000000000
--- a/arch/m68knommu/include/asm/oplib.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/oplib.h>
diff --git a/arch/m68knommu/include/asm/page.h b/arch/m68knommu/include/asm/page.h
deleted file mode 100644
index 3a1ede4544cb..000000000000
--- a/arch/m68knommu/include/asm/page.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef _M68KNOMMU_PAGE_H
-#define _M68KNOMMU_PAGE_H
-
-/* PAGE_SHIFT determines the page size */
-
-#define PAGE_SHIFT      (12)
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#define PAGE_MASK       (~(PAGE_SIZE-1))
-
-#include <asm/setup.h>
-
-#ifndef __ASSEMBLY__
- 
-#define get_user_page(vaddr)            __get_free_page(GFP_KERNEL)
-#define free_user_page(page, addr)      free_page(addr)
-
-#define clear_page(page)        memset((page), 0, PAGE_SIZE)
-#define copy_page(to,from)      memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr, pg)        clear_page(page)
-#define copy_user_page(to, from, vaddr, pg)     copy_page(to, from)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
-        alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pmd[16]; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x)      ((x).pte)
-#define pmd_val(x)      ((&x)->pmd[0])
-#define pgd_val(x)      ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
-#define __pgprot(x)     ((pgprot_t) { (x) } )
-
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
-#endif /* !__ASSEMBLY__ */
-
-#include <asm/page_offset.h>
-
-#define PAGE_OFFSET             (PAGE_OFFSET_RAW)
-
-#ifndef __ASSEMBLY__
-
-#define __pa(vaddr)             virt_to_phys((void *)(vaddr))
-#define __va(paddr)             phys_to_virt((unsigned long)(paddr))
-
-#define virt_to_pfn(kaddr)      (__pa(kaddr) >> PAGE_SHIFT)
-#define pfn_to_virt(pfn)        __va((pfn) << PAGE_SHIFT)
-
-#define virt_to_page(addr)      (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
-#define page_to_virt(page)      ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
-
-#define pfn_to_page(pfn)        virt_to_page(pfn_to_virt(pfn))
-#define page_to_pfn(page)       virt_to_pfn(page_to_virt(page))
-#define pfn_valid(pfn)          ((pfn) < max_mapnr)
-
-#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
-                                ((void *)(kaddr) < (void *)memory_end))
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm-generic/page.h>
-
-#endif /* _M68KNOMMU_PAGE_H */
diff --git a/arch/m68knommu/include/asm/page_offset.h b/arch/m68knommu/include/asm/page_offset.h
deleted file mode 100644
index d4e73e0ba646..000000000000
--- a/arch/m68knommu/include/asm/page_offset.h
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-/* This handles the memory map.. */
-#define PAGE_OFFSET_RAW         CONFIG_RAMBASE
-
diff --git a/arch/m68knommu/include/asm/param.h b/arch/m68knommu/include/asm/param.h
deleted file mode 100644
index 6044397adb64..000000000000
--- a/arch/m68knommu/include/asm/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _M68KNOMMU_PARAM_H
-#define _M68KNOMMU_PARAM_H
-
-#ifdef __KERNEL__
-#define HZ CONFIG_HZ
-#define USER_HZ         HZ
-#define CLOCKS_PER_SEC  (USER_HZ)
-#endif
-
-#ifndef HZ
-#define HZ      100
-#endif
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#endif /* _M68KNOMMU_PARAM_H */
diff --git a/arch/m68knommu/include/asm/pci.h b/arch/m68knommu/include/asm/pci.h
deleted file mode 100644
index a13f3cc87451..000000000000
--- a/arch/m68knommu/include/asm/pci.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef M68KNOMMU_PCI_H
-#define M68KNOMMU_PCI_H
-
-#include <asm-m68k/pci.h>
-
-#ifdef CONFIG_COMEMPCI
-/*
- *      These are pretty much arbitary with the CoMEM implementation.
- *      We have the whole address space to ourselves.
- */
-#define PCIBIOS_MIN_IO          0x100
-#define PCIBIOS_MIN_MEM         0x00010000
-
-#define pcibios_scan_all_fns(a, b)      0
-
-/*
- * Return whether the given PCI device DMA address mask can
- * be supported properly.  For example, if your device can
- * only drive the low 24-bits during PCI bus mastering, then
- * you would pass 0x00ffffff as the mask to this function.
- */
-static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
-{
-        return 1;
-}
-
-#endif /* CONFIG_COMEMPCI */
-
-#endif /* M68KNOMMU_PCI_H */
diff --git a/arch/m68knommu/include/asm/percpu.h b/arch/m68knommu/include/asm/percpu.h
deleted file mode 100644
index 5de72c327efd..000000000000
--- a/arch/m68knommu/include/asm/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ARCH_M68KNOMMU_PERCPU__
-#define __ARCH_M68KNOMMU_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_M68KNOMMU_PERCPU__ */
diff --git a/arch/m68knommu/include/asm/pgalloc.h b/arch/m68knommu/include/asm/pgalloc.h
deleted file mode 100644
index d6352f671ec0..000000000000
--- a/arch/m68knommu/include/asm/pgalloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _M68KNOMMU_PGALLOC_H
-#define _M68KNOMMU_PGALLOC_H
-
-#include <asm/setup.h>
-
-#define check_pgt_cache()       do { } while (0)
-
-#endif /* _M68KNOMMU_PGALLOC_H */
diff --git a/arch/m68knommu/include/asm/pgtable.h b/arch/m68knommu/include/asm/pgtable.h
deleted file mode 100644
index 46251016e821..000000000000
--- a/arch/m68knommu/include/asm/pgtable.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef _M68KNOMMU_PGTABLE_H
-#define _M68KNOMMU_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-/*
- * (C) Copyright 2000-2002, Greg Ungerer <gerg@snapgear.com>
- */
-
-#include <linux/slab.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/io.h>
-
-/*
- * Trivial page table functions.
- */
-#define pgd_present(pgd)        (1)
-#define pgd_none(pgd)           (0)
-#define pgd_bad(pgd)            (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr)   (1)
-#define pmd_offset(a, b)        ((void *)0)
-
-#define PAGE_NONE       __pgprot(0)
-#define PAGE_SHARED     __pgprot(0)
-#define PAGE_COPY       __pgprot(0)
-#define PAGE_READONLY   __pgprot(0)
-#define PAGE_KERNEL     __pgprot(0)
-
-extern void paging_init(void);
-#define swapper_pg_dir ((pgd_t *) 0)
-
-#define __swp_type(x)           (0)
-#define __swp_offset(x)         (0)
-#define __swp_entry(typ,off)    ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
-
-static inline int pte_file(pte_t pte) { return 0; }
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr)        (virt_to_page(0))
-
-/*
- * These would be in other places but having them here reduces the diffs.
- */
-extern unsigned int kobjsize(const void *objp);
-
-/*
- * No page table caches to initialise.
- */
-#define pgtable_cache_init()    do { } while (0)
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START   0
-#define VMALLOC_END     0xffffffff
-
-#include <asm-generic/pgtable.h>
-
-#endif /* _M68KNOMMU_PGTABLE_H */
diff --git a/arch/m68knommu/include/asm/poll.h b/arch/m68knommu/include/asm/poll.h
deleted file mode 100644
index ee1b6cb549ca..000000000000
--- a/arch/m68knommu/include/asm/poll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/poll.h>
diff --git a/arch/m68knommu/include/asm/posix_types.h b/arch/m68knommu/include/asm/posix_types.h
deleted file mode 100644
index 6205fb9392a3..000000000000
--- a/arch/m68knommu/include/asm/posix_types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/posix_types.h>
diff --git a/arch/m68knommu/include/asm/processor.h b/arch/m68knommu/include/asm/processor.h
deleted file mode 100644
index 91cba18acdd3..000000000000
--- a/arch/m68knommu/include/asm/processor.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * include/asm-m68knommu/processor.h
- *
- * Copyright (C) 1995 Hamish Macdonald
- */
-
-#ifndef __ASM_M68K_PROCESSOR_H
-#define __ASM_M68K_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <linux/compiler.h>
-#include <linux/threads.h>
-#include <asm/types.h>
-#include <asm/segment.h>
-#include <asm/fpu.h>
-#include <asm/ptrace.h>
-#include <asm/current.h>
-
-static inline unsigned long rdusp(void)
-{
-#ifdef CONFIG_COLDFIRE
-        extern unsigned int sw_usp;
-        return(sw_usp);
-#else
-        unsigned long usp;
-        __asm__ __volatile__("move %/usp,%0" : "=a" (usp));
-        return usp;
-#endif
-}
-
-static inline void wrusp(unsigned long usp)
-{
-#ifdef CONFIG_COLDFIRE
-        extern unsigned int sw_usp;
-        sw_usp = usp;
-#else
-        __asm__ __volatile__("move %0,%/usp" : : "a" (usp));
-#endif
-}
-
-/*
- * User space process size: 3.75GB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-#define TASK_SIZE       (0xF0000000UL)
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's. We won't be using it
- */
-#define TASK_UNMAPPED_BASE      0
-
-/* 
- * if you change this structure, you must change the code and offsets
- * in m68k/machasm.S
- */
-   
-struct thread_struct {
-        unsigned long  ksp;             /* kernel stack pointer */
-        unsigned long  usp;             /* user stack pointer */
-        unsigned short sr;              /* saved status register */
-        unsigned short fs;              /* saved fs (sfc, dfc) */
-        unsigned long  crp[2];          /* cpu root pointer */
-        unsigned long  esp0;            /* points to SR of stack frame */
-        unsigned long  fp[8*3];
-        unsigned long  fpcntl[3];       /* fp control regs */
-        unsigned char  fpstate[FPSTATESIZE];  /* floating point state */
-};
-
-#define INIT_THREAD  { \
-        sizeof(init_stack) + (unsigned long) init_stack, 0, \
-        PS_S, __KERNEL_DS, \
-        {0, 0}, 0, {0,}, {0, 0, 0}, {0,}, \
-}
-
-/*
- * Coldfire stacks need to be re-aligned on trap exit, conventional
- * 68k can handle this case cleanly.
- */
-#if defined(CONFIG_COLDFIRE)
-#define reformat(_regs)         do { (_regs)->format = 0x4; } while(0)
-#else
-#define reformat(_regs)         do { } while (0)
-#endif
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-#define start_thread(_regs, _pc, _usp)                  \
-do {                                                    \
-        set_fs(USER_DS); /* reads from user space */    \
-        (_regs)->pc = (_pc);                            \
-        ((struct switch_stack *)(_regs))[-1].a6 = 0;    \
-        reformat(_regs);                                \
-        if (current->mm)                                \
-                (_regs)->d5 = current->mm->start_data;  \
-        (_regs)->sr &= ~0x2000;                         \
-        wrusp(_usp);                                    \
-} while(0)
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk)    do { } while (0)
-
-extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-/*
- * Free current thread data structures etc..
- */
-static inline void exit_thread(void)
-{
-}
-
-unsigned long thread_saved_pc(struct task_struct *tsk);
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk)   \
-    ({                  \
-        unsigned long eip = 0;   \
-        if ((tsk)->thread.esp0 > PAGE_SIZE && \
-            (virt_addr_valid((tsk)->thread.esp0))) \
-              eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
-        eip; })
-#define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax()    barrier()
-
-#endif
diff --git a/arch/m68knommu/include/asm/ptrace.h b/arch/m68knommu/include/asm/ptrace.h
deleted file mode 100644
index 8c9194b98548..000000000000
--- a/arch/m68knommu/include/asm/ptrace.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef _M68K_PTRACE_H
-#define _M68K_PTRACE_H
-
-#define PT_D1      0
-#define PT_D2      1
-#define PT_D3      2
-#define PT_D4      3
-#define PT_D5      4
-#define PT_D6      5
-#define PT_D7      6
-#define PT_A0      7
-#define PT_A1      8
-#define PT_A2      9
-#define PT_A3      10
-#define PT_A4      11
-#define PT_A5      12
-#define PT_A6      13
-#define PT_D0      14
-#define PT_USP     15
-#define PT_ORIG_D0 16
-#define PT_SR      17
-#define PT_PC      18
-
-#ifndef __ASSEMBLY__
-
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-struct pt_regs {
-  long     d1;
-  long     d2;
-  long     d3;
-  long     d4;
-  long     d5;
-  long     a0;
-  long     a1;
-  long     a2;
-  long     d0;
-  long     orig_d0;
-  long     stkadj;
-#ifdef CONFIG_COLDFIRE
-  unsigned format :  4; /* frame format specifier */
-  unsigned vector : 12; /* vector offset */
-  unsigned short sr;
-  unsigned long  pc;
-#else
-  unsigned short sr;
-  unsigned long  pc;
-  unsigned format :  4; /* frame format specifier */
-  unsigned vector : 12; /* vector offset */
-#endif
-};
-
-/*
- * This is the extended stack used by signal handlers and the context
- * switcher: it's pushed after the normal "struct pt_regs".
- */
-struct switch_stack {
-        unsigned long  d6;
-        unsigned long  d7;
-        unsigned long  a3;
-        unsigned long  a4;
-        unsigned long  a5;
-        unsigned long  a6;
-        unsigned long  retpc;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13
-#define PTRACE_GETFPREGS          14
-#define PTRACE_SETFPREGS          15
-
-#ifdef __KERNEL__
-
-#ifndef PS_S
-#define PS_S  (0x2000)
-#define PS_M  (0x1000)
-#endif
-
-#define user_mode(regs) (!((regs)->sr & PS_S))
-#define instruction_pointer(regs) ((regs)->pc)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-#endif /* _M68K_PTRACE_H */
diff --git a/arch/m68knommu/include/asm/quicc_simple.h b/arch/m68knommu/include/asm/quicc_simple.h
deleted file mode 100644
index c3636932d4bc..000000000000
--- a/arch/m68knommu/include/asm/quicc_simple.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/***********************************
- * $Id: quicc_simple.h,v 1.1 2002/03/02 15:01:10 gerg Exp $
- ***********************************
- *
- ***************************************
- * Simple drivers common header
- ***************************************
- */
-
-#ifndef __SIMPLE_H
-#define __SIMPLE_H
-
-/* #include "quicc.h" */
-
-#define GLB_SCC_0   0
-#define GLB_SCC_1   1
-#define GLB_SCC_2   2
-#define GLB_SCC_3   3
-
-typedef void (int_routine)(unsigned short interrupt_event);
-typedef int_routine *int_routine_ptr; 
-typedef void *(alloc_routine)(int length);
-typedef void (free_routine)(int scc_num, int channel_num, void *buf);
-typedef void (store_rx_buffer_routine)(int scc_num, int channel_num, void *buff, int length);
-typedef int  (handle_tx_error_routine)(int scc_num, int channel_num, QUICC_BD *tbd);
-typedef void (handle_rx_error_routine)(int scc_num, int channel_num, QUICC_BD *rbd);
-typedef void (handle_lost_error_routine)(int scc_num, int channel_num);
-
-/* user defined functions for global errors */
-typedef void (handle_glob_overrun_routine)(int scc_number);
-typedef void (handle_glob_underrun_routine)(int scc_number);
-typedef void (glob_intr_q_overflow_routine)(int scc_number);
-
-/*
- * General initialization and command routines
- */
-void quicc_issue_cmd (unsigned short cmd, int scc_num);
-void quicc_init(void);
-void quicc_scc_init(int scc_number, int number_of_rx_buf, int number_of_tx_buf);
-void quicc_smc_init(int smc_number, int number_of_rx_buf, int number_of_tx_buf);
-void quicc_scc_start(int scc_num);
-void quicc_scc_loopback(int scc_num);
-
-/* Interrupt enable/disable routines for critical pieces of code*/
-unsigned short  IntrDis(void);
-void            IntrEna(unsigned short old_sr);
-
-/* For debugging */
-void print_rbd(int scc_num);
-void print_tbd(int scc_num);
-
-#endif
diff --git a/arch/m68knommu/include/asm/resource.h b/arch/m68knommu/include/asm/resource.h
deleted file mode 100644
index 7fa63d5ea576..000000000000
--- a/arch/m68knommu/include/asm/resource.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/resource.h>
diff --git a/arch/m68knommu/include/asm/rtc.h b/arch/m68knommu/include/asm/rtc.h
deleted file mode 100644
index eaf18ec83c8e..000000000000
--- a/arch/m68knommu/include/asm/rtc.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/rtc.h>
diff --git a/arch/m68knommu/include/asm/scatterlist.h b/arch/m68knommu/include/asm/scatterlist.h
deleted file mode 100644
index afc4788b0d2c..000000000000
--- a/arch/m68knommu/include/asm/scatterlist.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _M68KNOMMU_SCATTERLIST_H
-#define _M68KNOMMU_SCATTERLIST_H
-
-#include <linux/mm.h>
-#include <asm/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long   sg_magic;
-#endif
-        unsigned long   page_link;
-        unsigned int    offset;
-        dma_addr_t      dma_address;
-        unsigned int    length;
-};
-
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#define sg_dma_len(sg)          ((sg)->length)
-
-#define ISA_DMA_THRESHOLD       (0xffffffff)
-
-#endif /* !(_M68KNOMMU_SCATTERLIST_H) */
diff --git a/arch/m68knommu/include/asm/sections.h b/arch/m68knommu/include/asm/sections.h
deleted file mode 100644
index dd0ecb98ec08..000000000000
--- a/arch/m68knommu/include/asm/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _M68KNOMMU_SECTIONS_H
-#define _M68KNOMMU_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/m68knommu/include/asm/segment.h b/arch/m68knommu/include/asm/segment.h
deleted file mode 100644
index 42318ebec7ec..000000000000
--- a/arch/m68knommu/include/asm/segment.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef _M68K_SEGMENT_H
-#define _M68K_SEGMENT_H
-
-/* define constants */
-/* Address spaces (FC0-FC2) */
-#define USER_DATA     (1)
-#ifndef __USER_DS
-#define __USER_DS     (USER_DATA)
-#endif
-#define USER_PROGRAM  (2)
-#define SUPER_DATA    (5)
-#ifndef __KERNEL_DS
-#define __KERNEL_DS   (SUPER_DATA)
-#endif
-#define SUPER_PROGRAM (6)
-#define CPU_SPACE     (7)
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
-        unsigned long seg;
-} mm_segment_t;
-
-#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
-#define USER_DS         MAKE_MM_SEG(__USER_DS)
-#define KERNEL_DS       MAKE_MM_SEG(__KERNEL_DS)
-
-/*
- * Get/set the SFC/DFC registers for MOVES instructions
- */
-
-static inline mm_segment_t get_fs(void)
-{
-    return USER_DS;
-}
-
-static inline mm_segment_t get_ds(void)
-{
-    /* return the supervisor data space code */
-    return KERNEL_DS;
-}
-
-static inline void set_fs(mm_segment_t val)
-{
-}
-
-#define segment_eq(a,b) ((a).seg == (b).seg)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _M68K_SEGMENT_H */
diff --git a/arch/m68knommu/include/asm/sembuf.h b/arch/m68knommu/include/asm/sembuf.h
deleted file mode 100644
index 3a634f9ecf50..000000000000
--- a/arch/m68knommu/include/asm/sembuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/sembuf.h>
diff --git a/arch/m68knommu/include/asm/setup.h b/arch/m68knommu/include/asm/setup.h
deleted file mode 100644
index fb86bb2a6078..000000000000
--- a/arch/m68knommu/include/asm/setup.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifdef __KERNEL__
-
-#include <asm-m68k/setup.h>
-
-/* We have a bigger command line buffer. */
-#undef COMMAND_LINE_SIZE
-
-#endif  /*  __KERNEL__  */
-
-#define COMMAND_LINE_SIZE       512
diff --git a/arch/m68knommu/include/asm/shm.h b/arch/m68knommu/include/asm/shm.h
deleted file mode 100644
index cc8e522d9050..000000000000
--- a/arch/m68knommu/include/asm/shm.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/shm.h>
diff --git a/arch/m68knommu/include/asm/shmbuf.h b/arch/m68knommu/include/asm/shmbuf.h
deleted file mode 100644
index bc34cf8eefce..000000000000
--- a/arch/m68knommu/include/asm/shmbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/shmbuf.h>
diff --git a/arch/m68knommu/include/asm/shmparam.h b/arch/m68knommu/include/asm/shmparam.h
deleted file mode 100644
index d7ee69648ebf..000000000000
--- a/arch/m68knommu/include/asm/shmparam.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/shmparam.h>
diff --git a/arch/m68knommu/include/asm/sigcontext.h b/arch/m68knommu/include/asm/sigcontext.h
deleted file mode 100644
index 36c293fc133d..000000000000
--- a/arch/m68knommu/include/asm/sigcontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _ASM_M68KNOMMU_SIGCONTEXT_H
-#define _ASM_M68KNOMMU_SIGCONTEXT_H
-
-struct sigcontext {
-        unsigned long  sc_mask;         /* old sigmask */
-        unsigned long  sc_usp;          /* old user stack pointer */
-        unsigned long  sc_d0;
-        unsigned long  sc_d1;
-        unsigned long  sc_a0;
-        unsigned long  sc_a1;
-        unsigned long  sc_a5;
-        unsigned short sc_sr;
-        unsigned long  sc_pc;
-        unsigned short sc_formatvec;
-};
-
-#endif
diff --git a/arch/m68knommu/include/asm/siginfo.h b/arch/m68knommu/include/asm/siginfo.h
deleted file mode 100644
index b18e5f4064ae..000000000000
--- a/arch/m68knommu/include/asm/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _M68KNOMMU_SIGINFO_H
-#define _M68KNOMMU_SIGINFO_H
-
-#include <asm-generic/siginfo.h>
-
-#endif
diff --git a/arch/m68knommu/include/asm/signal.h b/arch/m68knommu/include/asm/signal.h
deleted file mode 100644
index 216c08be54a0..000000000000
--- a/arch/m68knommu/include/asm/signal.h
+++ /dev/null
@@ -1,159 +0,0 @@
-#ifndef _M68KNOMMU_SIGNAL_H
-#define _M68KNOMMU_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifdef __KERNEL__
-/* Most things should be clean enough to redefine this at will, if care
-   is taken to make libc match.  */
-
-#define _NSIG           64
-#define _NSIG_BPW       32
-#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;             /* at least 32 bits */
-
-typedef struct {
-        unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG            32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP           1
-#define SIGINT           2
-#define SIGQUIT          3
-#define SIGILL           4
-#define SIGTRAP          5
-#define SIGABRT          6
-#define SIGIOT           6
-#define SIGBUS           7
-#define SIGFPE           8
-#define SIGKILL          9
-#define SIGUSR1         10
-#define SIGSEGV         11
-#define SIGUSR2         12
-#define SIGPIPE         13
-#define SIGALRM         14
-#define SIGTERM         15
-#define SIGSTKFLT       16
-#define SIGCHLD         17
-#define SIGCONT         18
-#define SIGSTOP         19
-#define SIGTSTP         20
-#define SIGTTIN         21
-#define SIGTTOU         22
-#define SIGURG          23
-#define SIGXCPU         24
-#define SIGXFSZ         25
-#define SIGVTALRM       26
-#define SIGPROF         27
-#define SIGWINCH        28
-#define SIGIO           29
-#define SIGPOLL         SIGIO
-/*
-#define SIGLOST         29
-*/
-#define SIGPWR          30
-#define SIGSYS          31
-#define SIGUNUSED       31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP    0x00000001
-#define SA_NOCLDWAIT    0x00000002
-#define SA_SIGINFO      0x00000004
-#define SA_ONSTACK      0x08000000
-#define SA_RESTART      0x10000000
-#define SA_NODEFER      0x40000000
-#define SA_RESETHAND    0x80000000
-
-#define SA_NOMASK       SA_NODEFER
-#define SA_ONESHOT      SA_RESETHAND
-
-/* 
- * sigaltstack controls
- */
-#define SS_ONSTACK      1
-#define SS_DISABLE      2
-
-#define MINSIGSTKSZ     2048
-#define SIGSTKSZ        8192
-
-#include <asm-generic/signal.h>
-
-#ifdef __KERNEL__
-struct old_sigaction {
-        __sighandler_t sa_handler;
-        old_sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer)(void);
-};
-
-struct sigaction {
-        __sighandler_t sa_handler;
-        unsigned long sa_flags;
-        void (*sa_restorer)(void);
-        sigset_t sa_mask;               /* mask last for extensibility */
-};
-
-struct k_sigaction {
-        struct sigaction sa;
-};
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-        union {
-          __sighandler_t _sa_handler;
-          void (*_sa_sigaction)(int, struct siginfo *, void *);
-        } _u;
-        sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer)(void);
-};
-
-#define sa_handler      _u._sa_handler
-#define sa_sigaction    _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
-        void *ss_sp;
-        int ss_flags;
-        size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-
-#include <asm/sigcontext.h>
-#undef __HAVE_ARCH_SIG_BITOPS
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif /* __KERNEL__ */
-
-#endif /* _M68KNOMMU_SIGNAL_H */
diff --git a/arch/m68knommu/include/asm/smp.h b/arch/m68knommu/include/asm/smp.h
deleted file mode 100644
index 9e9bd7e58922..000000000000
--- a/arch/m68knommu/include/asm/smp.h
+++ /dev/null
@@ -1 +0,0 @@
-/* nothing required here yet */
diff --git a/arch/m68knommu/include/asm/socket.h b/arch/m68knommu/include/asm/socket.h
deleted file mode 100644
index ac5478bf6371..000000000000
--- a/arch/m68knommu/include/asm/socket.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/socket.h>
diff --git a/arch/m68knommu/include/asm/sockios.h b/arch/m68knommu/include/asm/sockios.h
deleted file mode 100644
index dcc6a8900ce2..000000000000
--- a/arch/m68knommu/include/asm/sockios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/sockios.h>
diff --git a/arch/m68knommu/include/asm/spinlock.h b/arch/m68knommu/include/asm/spinlock.h
deleted file mode 100644
index 6bb1f06c4781..000000000000
--- a/arch/m68knommu/include/asm/spinlock.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/spinlock.h>
diff --git a/arch/m68knommu/include/asm/stat.h b/arch/m68knommu/include/asm/stat.h
deleted file mode 100644
index 3d4b260e7c03..000000000000
--- a/arch/m68knommu/include/asm/stat.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/stat.h>
diff --git a/arch/m68knommu/include/asm/statfs.h b/arch/m68knommu/include/asm/statfs.h
deleted file mode 100644
index 2ce99eaf0970..000000000000
--- a/arch/m68knommu/include/asm/statfs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/statfs.h>
diff --git a/arch/m68knommu/include/asm/string.h b/arch/m68knommu/include/asm/string.h
deleted file mode 100644
index af09e17000fc..000000000000
--- a/arch/m68knommu/include/asm/string.h
+++ /dev/null
@@ -1,126 +0,0 @@
-#ifndef _M68KNOMMU_STRING_H_
-#define _M68KNOMMU_STRING_H_
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#define __HAVE_ARCH_STRCPY
-static inline char * strcpy(char * dest,const char *src)
-{
-  char *xdest = dest;
-
-  __asm__ __volatile__
-       ("1:\tmoveb %1@+,%0@+\n\t"
-        "jne 1b"
-        : "=a" (dest), "=a" (src)
-        : "0" (dest), "1" (src) : "memory");
-  return xdest;
-}
-
-#define __HAVE_ARCH_STRNCPY
-static inline char * strncpy(char *dest, const char *src, size_t n)
-{
-  char *xdest = dest;
-
-  if (n == 0)
-    return xdest;
-
-  __asm__ __volatile__
-       ("1:\tmoveb %1@+,%0@+\n\t"
-        "jeq 2f\n\t"
-        "subql #1,%2\n\t"
-        "jne 1b\n\t"
-        "2:"
-        : "=a" (dest), "=a" (src), "=d" (n)
-        : "0" (dest), "1" (src), "2" (n)
-        : "memory");
-  return xdest;
-}
-
-
-#ifndef CONFIG_COLDFIRE
-
-#define __HAVE_ARCH_STRCMP
-static inline int strcmp(const char * cs,const char * ct)
-{
-  char __res;
-
-  __asm__
-       ("1:\tmoveb %0@+,%2\n\t" /* get *cs */
-        "cmpb %1@+,%2\n\t"      /* compare a byte */
-        "jne  2f\n\t"           /* not equal, break out */
-        "tstb %2\n\t"           /* at end of cs? */
-        "jne  1b\n\t"           /* no, keep going */
-        "jra  3f\n\t"           /* strings are equal */
-        "2:\tsubb %1@-,%2\n\t"  /* *cs - *ct */
-        "3:"
-        : "=a" (cs), "=a" (ct), "=d" (__res)
-        : "0" (cs), "1" (ct));
-
-  return __res;
-}
-
-#define __HAVE_ARCH_STRNCMP
-static inline int strncmp(const char * cs,const char * ct,size_t count)
-{
-  char __res;
-
-  if (!count)
-    return 0;
-  __asm__
-       ("1:\tmovb %0@+,%3\n\t"          /* get *cs */
-        "cmpb   %1@+,%3\n\t"            /* compare a byte */
-        "jne    3f\n\t"                 /* not equal, break out */
-        "tstb   %3\n\t"                 /* at end of cs? */
-        "jeq    4f\n\t"                 /* yes, all done */
-        "subql  #1,%2\n\t"              /* no, adjust count */
-        "jne    1b\n\t"                 /* more to do, keep going */
-        "2:\tmoveq #0,%3\n\t"           /* strings are equal */
-        "jra    4f\n\t"
-        "3:\tsubb %1@-,%3\n\t"          /* *cs - *ct */
-        "4:"
-        : "=a" (cs), "=a" (ct), "=d" (count), "=d" (__res)
-        : "0" (cs), "1" (ct), "2" (count));
-  return __res;
-}
-
-#endif /* CONFIG_COLDFIRE */
-
-#define __HAVE_ARCH_MEMSET
-extern void * memset(void * s, int c, size_t count);
-
-#define __HAVE_ARCH_MEMCPY
-extern void * memcpy(void *d, const void *s, size_t count);
-
-#else /* KERNEL */
-
-/*
- *      let user libraries deal with these,
- *      IMHO the kernel has no place defining these functions for user apps
- */
-
-#define __HAVE_ARCH_STRCPY 1
-#define __HAVE_ARCH_STRNCPY 1
-#define __HAVE_ARCH_STRCAT 1
-#define __HAVE_ARCH_STRNCAT 1
-#define __HAVE_ARCH_STRCMP 1
-#define __HAVE_ARCH_STRNCMP 1
-#define __HAVE_ARCH_STRNICMP 1
-#define __HAVE_ARCH_STRCHR 1
-#define __HAVE_ARCH_STRRCHR 1
-#define __HAVE_ARCH_STRSTR 1
-#define __HAVE_ARCH_STRLEN 1
-#define __HAVE_ARCH_STRNLEN 1
-#define __HAVE_ARCH_MEMSET 1
-#define __HAVE_ARCH_MEMCPY 1
-#define __HAVE_ARCH_MEMMOVE 1
-#define __HAVE_ARCH_MEMSCAN 1
-#define __HAVE_ARCH_MEMCMP 1
-#define __HAVE_ARCH_MEMCHR 1
-#define __HAVE_ARCH_STRTOK 1
-
-#endif /* KERNEL */
-
-#endif /* _M68K_STRING_H_ */
diff --git a/arch/m68knommu/include/asm/swab.h b/arch/m68knommu/include/asm/swab.h
deleted file mode 100644
index e582257db300..000000000000
--- a/arch/m68knommu/include/asm/swab.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _M68KNOMMU_SWAB_H
-#define _M68KNOMMU_SWAB_H
-
-#include <linux/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __SWAB_64_THRU_32__
-#endif
-
-#if defined (__mcfisaaplus__) || defined (__mcfisac__)
-static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
-{
-        asm(
-                        "byterev %0"
-                        : "=d" (val)
-                        : "0" (val)
-           );
-        return val;
-}
-
-#define __arch_swab32 __arch_swab32
-#endif
-
-#endif /* _M68KNOMMU_SWAB_H */
diff --git a/arch/m68knommu/include/asm/system.h b/arch/m68knommu/include/asm/system.h
deleted file mode 100644
index 40f49de69821..000000000000
--- a/arch/m68knommu/include/asm/system.h
+++ /dev/null
@@ -1,324 +0,0 @@
-#ifndef _M68KNOMMU_SYSTEM_H
-#define _M68KNOMMU_SYSTEM_H
-
-#include <linux/linkage.h>
-#include <asm/segment.h>
-#include <asm/entry.h>
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.  This
- * also clears the TS-flag if the task we switched to has used the
- * math co-processor latest.
- */
-/*
- * switch_to() saves the extra registers, that are not saved
- * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
- * a0-a1. Some of these are used by schedule() and its predecessors
- * and so we might get see unexpected behaviors when a task returns
- * with unexpected register values.
- *
- * syscall stores these registers itself and none of them are used
- * by syscall after the function in the syscall has been called.
- *
- * Beware that resume now expects *next to be in d1 and the offset of
- * tss to be in a1. This saves a few instructions as we no longer have
- * to push them onto the stack and read them back right after.
- *
- * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
- *
- * Changed 96/09/19 by Andreas Schwab
- * pass prev in a0, next in a1, offset of tss in d1, and whether
- * the mm structures are shared in d2 (to avoid atc flushing).
- */
-asmlinkage void resume(void);
-#define switch_to(prev,next,last)                               \
-{                                                               \
-  void *_last;                                                  \
-  __asm__ __volatile__(                                         \
-        "movel  %1, %%a0\n\t"                                   \
-        "movel  %2, %%a1\n\t"                                   \
-        "jbsr resume\n\t"                                       \
-        "movel  %%d1, %0\n\t"                                   \
-       : "=d" (_last)                                           \
-       : "d" (prev), "d" (next)                                 \
-       : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
-  (last) = _last;                                               \
-}
-
-#ifdef CONFIG_COLDFIRE
-#define local_irq_enable() __asm__ __volatile__ (               \
-        "move %/sr,%%d0\n\t"                                    \
-        "andi.l #0xf8ff,%%d0\n\t"                               \
-        "move %%d0,%/sr\n"                                      \
-        : /* no outputs */                                      \
-        :                                                       \
-        : "cc", "%d0", "memory")
-#define local_irq_disable() __asm__ __volatile__ (              \
-        "move %/sr,%%d0\n\t"                                    \
-        "ori.l #0x0700,%%d0\n\t"                                \
-        "move %%d0,%/sr\n"                                      \
-        : /* no outputs */                                      \
-        :                                                       \
-        : "cc", "%d0", "memory")
-/* For spinlocks etc */
-#define local_irq_save(x) __asm__ __volatile__ (                \
-        "movew %%sr,%0\n\t"                                     \
-        "movew #0x0700,%%d0\n\t"                                \
-        "or.l  %0,%%d0\n\t"                                     \
-        "movew %%d0,%/sr"                                       \
-        : "=d" (x)                                              \
-        :                                                       \
-        : "cc", "%d0", "memory")
-#else
-
-/* portable version */ /* FIXME - see entry.h*/
-#define ALLOWINT 0xf8ff
-
-#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
-#define local_irq_disable() asm volatile ("oriw  #0x0700,%%sr": : : "memory")
-#endif
-
-#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
-#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
-
-/* For spinlocks etc */
-#ifndef local_irq_save
-#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
-#endif
-
-#define irqs_disabled()                 \
-({                                      \
-        unsigned long flags;            \
-        local_save_flags(flags);        \
-        ((flags & 0x0700) == 0x0700);   \
-})
-
-#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
-
-/*
- * Force strict CPU ordering.
- * Not really required on m68k...
- */
-#define nop()  asm volatile ("nop"::)
-#define mb()   asm volatile (""   : : :"memory")
-#define rmb()  asm volatile (""   : : :"memory")
-#define wmb()  asm volatile (""   : : :"memory")
-#define set_mb(var, value)      ({ (var) = (value); wmb(); })
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while(0)
-#endif
-
-#define read_barrier_depends()  ((void)0)
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-#ifndef CONFIG_RMW_INSNS
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-  unsigned long tmp, flags;
-
-  local_irq_save(flags);
-
-  switch (size) {
-  case 1:
-    __asm__ __volatile__
-    ("moveb %2,%0\n\t"
-     "moveb %1,%2"
-    : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-    break;
-  case 2:
-    __asm__ __volatile__
-    ("movew %2,%0\n\t"
-     "movew %1,%2"
-    : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-    break;
-  case 4:
-    __asm__ __volatile__
-    ("movel %2,%0\n\t"
-     "movel %1,%2"
-    : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-    break;
-  }
-  local_irq_restore(flags);
-  return tmp;
-}
-#else
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-        switch (size) {
-            case 1:
-                __asm__ __volatile__
-                        ("moveb %2,%0\n\t"
-                         "1:\n\t"
-                         "casb %0,%1,%2\n\t"
-                         "jne 1b"
-                         : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-            case 2:
-                __asm__ __volatile__
-                        ("movew %2,%0\n\t"
-                         "1:\n\t"
-                         "casw %0,%1,%2\n\t"
-                         "jne 1b"
-                         : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-            case 4:
-                __asm__ __volatile__
-                        ("movel %2,%0\n\t"
-                         "1:\n\t"
-                         "casl %0,%1,%2\n\t"
-                         "jne 1b"
-                         : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        }
-        return x;
-}
-#endif
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)                                               \
-        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-                        (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#ifndef CONFIG_SMP
-#include <asm-generic/cmpxchg.h>
-#endif
-
-#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \
-        defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 )
-#define HARD_RESET_NOW() ({             \
-        local_irq_disable();            \
-        asm("                           \
-        moveal #0x10c00000, %a0;        \
-        moveb #0, 0xFFFFF300;           \
-        moveal 0(%a0), %sp;             \
-        moveal 4(%a0), %a0;             \
-        jmp (%a0);                      \
-        ");                             \
-})
-#endif
-
-#ifdef CONFIG_COLDFIRE
-#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
-/*
- * Need to account for broken early mask of 5272 silicon. So don't
- * jump through the original start address. Jump strait into the
- * known start of the FLASH code.
- */
-#define HARD_RESET_NOW() ({             \
-        asm("                           \
-        movew #0x2700, %sr;             \
-        jmp 0xf0000400;                 \
-        ");                             \
-})
-#elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
-      defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
-#define HARD_RESET_NOW() ({             \
-        asm("                           \
-        movew #0x2700, %sr;             \
-        moveal #0x10000044, %a0;        \
-        movel #0xffffffff, (%a0);       \
-        moveal #0x10000001, %a0;        \
-        moveb #0x00, (%a0);             \
-        moveal #0xf0000004, %a0;        \
-        moveal (%a0), %a0;              \
-        jmp (%a0);                      \
-        ");                             \
-})
-#elif defined(CONFIG_M5272)
-/*
- * Retrieve the boot address in flash using CSBR0 and CSOR0
- * find the reset vector at flash_address + 4 (e.g. 0x400)
- * remap it in the flash's current location (e.g. 0xf0000400)
- * and jump there.
- */ 
-#define HARD_RESET_NOW() ({             \
-        asm("                           \
-        movew #0x2700, %%sr;            \
-        move.l  %0+0x40,%%d0;           \
-        and.l   %0+0x44,%%d0;           \
-        andi.l  #0xfffff000,%%d0;       \
-        mov.l   %%d0,%%a0;              \
-        or.l    4(%%a0),%%d0;           \
-        mov.l   %%d0,%%a0;              \
-        jmp (%%a0);"                    \
-        : /* No output */               \
-        : "o" (*(char *)MCF_MBAR) );    \
-})
-#elif defined(CONFIG_M528x)
-/*
- * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
- * that when set, resets the MCF528x.
- */
-#define HARD_RESET_NOW() \
-({                                              \
-        unsigned char volatile *reset;          \
-        asm("move.w     #0x2700, %sr");         \
-        reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000));    \
-        while(1)                                \
-        *reset |= (0x01 << 7);\
-})
-#elif defined(CONFIG_M523x)
-#define HARD_RESET_NOW() ({             \
-        asm("                           \
-        movew #0x2700, %sr;             \
-        movel #0x01000000, %sp;         \
-        moveal #0x40110000, %a0;        \
-        moveb #0x80, (%a0);             \
-        ");                             \
-})
-#elif defined(CONFIG_M520x)
-        /*
-         * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register 
-         * RCR), that when set, resets the MCF5208.
-         */
-#define HARD_RESET_NOW()                \
-({                                      \
-        unsigned char volatile *reset;  \
-        asm("move.w     #0x2700, %sr"); \
-        reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000));     \
-        while(1)                        \
-                *reset |= 0x80;         \
-})
-#else
-#define HARD_RESET_NOW() ({             \
-        asm("                           \
-        movew #0x2700, %sr;             \
-        moveal #0x4, %a0;               \
-        moveal (%a0), %a0;              \
-        jmp (%a0);                      \
-        ");                             \
-})
-#endif
-#endif
-#define arch_align_stack(x) (x)
-
-
-static inline int irqs_disabled_flags(unsigned long flags)
-{
-        if (flags & 0x0700)
-                return 0;
-        else
-                return 1;
-}
-
-#endif /* _M68KNOMMU_SYSTEM_H */
diff --git a/arch/m68knommu/include/asm/termbits.h b/arch/m68knommu/include/asm/termbits.h
deleted file mode 100644
index 05dd6bc27285..000000000000
--- a/arch/m68knommu/include/asm/termbits.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/termbits.h>
diff --git a/arch/m68knommu/include/asm/termios.h b/arch/m68knommu/include/asm/termios.h
deleted file mode 100644
index e7337881a985..000000000000
--- a/arch/m68knommu/include/asm/termios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/termios.h>
diff --git a/arch/m68knommu/include/asm/thread_info.h b/arch/m68knommu/include/asm/thread_info.h
deleted file mode 100644
index 82529f424ea3..000000000000
--- a/arch/m68knommu/include/asm/thread_info.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* thread_info.h: m68knommu low-level thread information
- * adapted from the i386 and PPC versions by Greg Ungerer (gerg@snapgear.com)
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#ifdef CONFIG_4KSTACKS
-#define THREAD_SIZE_ORDER (0)
-#else
-#define THREAD_SIZE_ORDER (1)
-#endif
-                                                                                
-/*
- * for asm files, THREAD_SIZE is now generated by asm-offsets.c
- */
-#define THREAD_SIZE (PAGE_SIZE<<THREAD_SIZE_ORDER)
-
-/*
- * low level task data.
- */
-struct thread_info {
-        struct task_struct *task;               /* main task structure */
-        struct exec_domain *exec_domain;        /* execution domain */
-        unsigned long      flags;               /* low level flags */
-        int                cpu;                 /* cpu we're on */
-        int                preempt_count;       /* 0 => preemptable, <0 => BUG */
-        struct restart_block restart_block;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task           = &tsk,                 \
-        .exec_domain    = &default_exec_domain, \
-        .flags          = 0,                    \
-        .cpu            = 0,                    \
-        .restart_block  = {                     \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-        struct thread_info *ti;
-        __asm__(
-                "move.l %%sp, %0 \n\t"
-                "and.l  %1, %0"
-                : "=&d"(ti)
-                : "di" (~(THREAD_SIZE-1))
-                );
-        return ti;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#define PREEMPT_ACTIVE  0x4000000
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
-#define TIF_SIGPENDING          1       /* signal pending */
-#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
-                                           TIF_NEED_RESCHED */
-#define TIF_MEMDIE              4
-#define TIF_FREEZE              16      /* is freezing for suspend */
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_FREEZE             (1<<TIF_FREEZE)
-
-#define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/m68knommu/include/asm/timex.h b/arch/m68knommu/include/asm/timex.h
deleted file mode 100644
index 109050f3fe91..000000000000
--- a/arch/m68knommu/include/asm/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/include/asm-m68knommu/timex.h
- *
- * m68knommu architecture timex specifications
- */
-#ifndef _ASM_M68KNOMMU_TIMEX_H
-#define _ASM_M68KNOMMU_TIMEX_H
-
-#ifdef CONFIG_COLDFIRE
-#include <asm/coldfire.h>
-#define CLOCK_TICK_RATE MCF_CLK
-#else
-#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
-#endif
-
-typedef unsigned long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
-        return 0;
-}
-
-#endif
diff --git a/arch/m68knommu/include/asm/tlb.h b/arch/m68knommu/include/asm/tlb.h
deleted file mode 100644
index 77a7c51ca299..000000000000
--- a/arch/m68knommu/include/asm/tlb.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/tlb.h>
diff --git a/arch/m68knommu/include/asm/tlbflush.h b/arch/m68knommu/include/asm/tlbflush.h
deleted file mode 100644
index a470cfb803eb..000000000000
--- a/arch/m68knommu/include/asm/tlbflush.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _M68KNOMMU_TLBFLUSH_H
-#define _M68KNOMMU_TLBFLUSH_H
-
-/*
- * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
- * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
- */
-
-#include <asm/setup.h>
-
-/*
- * flush all user-space atc entries.
- */
-static inline void __flush_tlb(void)
-{
-        BUG();
-}
-
-static inline void __flush_tlb_one(unsigned long addr)
-{
-        BUG();
-}
-
-#define flush_tlb() __flush_tlb()
-
-/*
- * flush all atc entries (both kernel and user-space entries).
- */
-static inline void flush_tlb_all(void)
-{
-        BUG();
-}
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-        BUG();
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
-        BUG();
-}
-
-static inline void flush_tlb_range(struct mm_struct *mm,
-                                   unsigned long start, unsigned long end)
-{
-        BUG();
-}
-
-static inline void flush_tlb_kernel_page(unsigned long addr)
-{
-        BUG();
-}
-
-#endif /* _M68KNOMMU_TLBFLUSH_H */
diff --git a/arch/m68knommu/include/asm/topology.h b/arch/m68knommu/include/asm/topology.h
deleted file mode 100644
index ca173e9f26ff..000000000000
--- a/arch/m68knommu/include/asm/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_M68K_TOPOLOGY_H
-#define _ASM_M68K_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_M68K_TOPOLOGY_H */
diff --git a/arch/m68knommu/include/asm/traps.h b/arch/m68knommu/include/asm/traps.h
deleted file mode 100644
index d0671e5f8e29..000000000000
--- a/arch/m68knommu/include/asm/traps.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- *  linux/include/asm/traps.h
- *
- *  Copyright (C) 1993        Hamish Macdonald
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _M68KNOMMU_TRAPS_H
-#define _M68KNOMMU_TRAPS_H
-
-#ifndef __ASSEMBLY__
-
-typedef void (*e_vector)(void);
-
-extern e_vector vectors[];
-extern void init_vectors(void);
-extern void enable_vector(unsigned int irq);
-extern void disable_vector(unsigned int irq);
-extern void ack_vector(unsigned int irq);
-
-#endif
-
-#define VEC_BUSERR  (2)
-#define VEC_ADDRERR (3)
-#define VEC_ILLEGAL (4)
-#define VEC_ZERODIV (5)
-#define VEC_CHK     (6)
-#define VEC_TRAP    (7)
-#define VEC_PRIV    (8)
-#define VEC_TRACE   (9)
-#define VEC_LINE10  (10)
-#define VEC_LINE11  (11)
-#define VEC_RESV1   (12)
-#define VEC_COPROC  (13)
-#define VEC_FORMAT  (14)
-#define VEC_UNINT   (15)
-#define VEC_SPUR    (24)
-#define VEC_INT1    (25)
-#define VEC_INT2    (26)
-#define VEC_INT3    (27)
-#define VEC_INT4    (28)
-#define VEC_INT5    (29)
-#define VEC_INT6    (30)
-#define VEC_INT7    (31)
-#define VEC_SYS     (32)
-#define VEC_TRAP1   (33)
-#define VEC_TRAP2   (34)
-#define VEC_TRAP3   (35)
-#define VEC_TRAP4   (36)
-#define VEC_TRAP5   (37)
-#define VEC_TRAP6   (38)
-#define VEC_TRAP7   (39)
-#define VEC_TRAP8   (40)
-#define VEC_TRAP9   (41)
-#define VEC_TRAP10  (42)
-#define VEC_TRAP11  (43)
-#define VEC_TRAP12  (44)
-#define VEC_TRAP13  (45)
-#define VEC_TRAP14  (46)
-#define VEC_TRAP15  (47)
-#define VEC_FPBRUC  (48)
-#define VEC_FPIR    (49)
-#define VEC_FPDIVZ  (50)
-#define VEC_FPUNDER (51)
-#define VEC_FPOE    (52)
-#define VEC_FPOVER  (53)
-#define VEC_FPNAN   (54)
-#define VEC_FPUNSUP (55)
-#define VEC_UNIMPEA (60)
-#define VEC_UNIMPII (61)
-#define VEC_USER    (64)
-
-#define VECOFF(vec) ((vec)<<2)
-
-#ifndef __ASSEMBLY__
-
-/* Status register bits */
-#define PS_T  (0x8000)
-#define PS_S  (0x2000)
-#define PS_M  (0x1000)
-#define PS_C  (0x0001)
-
-/* structure for stack frames */
-
-struct frame {
-    struct pt_regs ptregs;
-    union {
-            struct {
-                    unsigned long  iaddr;    /* instruction address */
-            } fmt2;
-            struct {
-                    unsigned long  effaddr;  /* effective address */
-            } fmt3;
-            struct {
-                    unsigned long  effaddr;  /* effective address */
-                    unsigned long  pc;       /* pc of faulted instr */
-            } fmt4;
-            struct {
-                    unsigned long  effaddr;  /* effective address */
-                    unsigned short ssw;      /* special status word */
-                    unsigned short wb3s;     /* write back 3 status */
-                    unsigned short wb2s;     /* write back 2 status */
-                    unsigned short wb1s;     /* write back 1 status */
-                    unsigned long  faddr;    /* fault address */
-                    unsigned long  wb3a;     /* write back 3 address */
-                    unsigned long  wb3d;     /* write back 3 data */
-                    unsigned long  wb2a;     /* write back 2 address */
-                    unsigned long  wb2d;     /* write back 2 data */
-                    unsigned long  wb1a;     /* write back 1 address */
-                    unsigned long  wb1dpd0;  /* write back 1 data/push data 0*/
-                    unsigned long  pd1;      /* push data 1*/
-                    unsigned long  pd2;      /* push data 2*/
-                    unsigned long  pd3;      /* push data 3*/
-            } fmt7;
-            struct {
-                    unsigned long  iaddr;    /* instruction address */
-                    unsigned short int1[4];  /* internal registers */
-            } fmt9;
-            struct {
-                    unsigned short int1;
-                    unsigned short ssw;      /* special status word */
-                    unsigned short isc;      /* instruction stage c */
-                    unsigned short isb;      /* instruction stage b */
-                    unsigned long  daddr;    /* data cycle fault address */
-                    unsigned short int2[2];
-                    unsigned long  dobuf;    /* data cycle output buffer */
-                    unsigned short int3[2];
-            } fmta;
-            struct {
-                    unsigned short int1;
-                    unsigned short ssw;     /* special status word */
-                    unsigned short isc;     /* instruction stage c */
-                    unsigned short isb;     /* instruction stage b */
-                    unsigned long  daddr;   /* data cycle fault address */
-                    unsigned short int2[2];
-                    unsigned long  dobuf;   /* data cycle output buffer */
-                    unsigned short int3[4];
-                    unsigned long  baddr;   /* stage B address */
-                    unsigned short int4[2];
-                    unsigned long  dibuf;   /* data cycle input buffer */
-                    unsigned short int5[3];
-                    unsigned       ver : 4; /* stack frame version # */
-                    unsigned       int6:12;
-                    unsigned short int7[18];
-            } fmtb;
-    } un;
-};
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _M68KNOMMU_TRAPS_H */
diff --git a/arch/m68knommu/include/asm/types.h b/arch/m68knommu/include/asm/types.h
deleted file mode 100644
index 031238c2d180..000000000000
--- a/arch/m68knommu/include/asm/types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/types.h>
diff --git a/arch/m68knommu/include/asm/uaccess.h b/arch/m68knommu/include/asm/uaccess.h
deleted file mode 100644
index 68bbe9b312f1..000000000000
--- a/arch/m68knommu/include/asm/uaccess.h
+++ /dev/null
@@ -1,181 +0,0 @@
-#ifndef __M68KNOMMU_UACCESS_H
-#define __M68KNOMMU_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-
-#define VERIFY_READ     0
-#define VERIFY_WRITE    1
-
-#define access_ok(type,addr,size)       _access_ok((unsigned long)(addr),(size))
-
-/*
- * It is not enough to just have access_ok check for a real RAM address.
- * This would disallow the case of code/ro-data running XIP in flash/rom.
- * Ideally we would check the possible flash ranges too, but that is
- * currently not so easy.
- */
-static inline int _access_ok(unsigned long addr, unsigned long size)
-{
-        return 1;
-}
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry
-{
-        unsigned long insn, fixup;
-};
-
-/* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table(unsigned long);
-
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x, ptr)                                \
-({                                                      \
-    int __pu_err = 0;                                   \
-    typeof(*(ptr)) __pu_val = (x);                      \
-    switch (sizeof (*(ptr))) {                          \
-    case 1:                                             \
-        __put_user_asm(__pu_err, __pu_val, ptr, b);     \
-        break;                                          \
-    case 2:                                             \
-        __put_user_asm(__pu_err, __pu_val, ptr, w);     \
-        break;                                          \
-    case 4:                                             \
-        __put_user_asm(__pu_err, __pu_val, ptr, l);     \
-        break;                                          \
-    case 8:                                             \
-        memcpy(ptr, &__pu_val, sizeof (*(ptr))); \
-        break;                                          \
-    default:                                            \
-        __pu_err = __put_user_bad();                    \
-        break;                                          \
-    }                                                   \
-    __pu_err;                                           \
-})
-#define __put_user(x, ptr) put_user(x, ptr)
-
-extern int __put_user_bad(void);
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long *)(x))
-
-#define __put_user_asm(err,x,ptr,bwl)                           \
-        __asm__ ("move" #bwl " %0,%1"                           \
-                : /* no outputs */                                              \
-                :"d" (x),"m" (*__ptr(ptr)) : "memory")
-
-#define get_user(x, ptr)                                        \
-({                                                              \
-    int __gu_err = 0;                                           \
-    typeof(x) __gu_val = 0;                                     \
-    switch (sizeof(*(ptr))) {                                   \
-    case 1:                                                     \
-        __get_user_asm(__gu_err, __gu_val, ptr, b, "=d");       \
-        break;                                                  \
-    case 2:                                                     \
-        __get_user_asm(__gu_err, __gu_val, ptr, w, "=r");       \
-        break;                                                  \
-    case 4:                                                     \
-        __get_user_asm(__gu_err, __gu_val, ptr, l, "=r");       \
-        break;                                                  \
-    case 8:                                                     \
-        memcpy((void *) &__gu_val, ptr, sizeof (*(ptr)));       \
-        break;                                                  \
-    default:                                                    \
-        __gu_val = 0;                                           \
-        __gu_err = __get_user_bad();                            \
-        break;                                                  \
-    }                                                           \
-    (x) = (typeof(*(ptr))) __gu_val;                            \
-    __gu_err;                                                   \
-})
-#define __get_user(x, ptr) get_user(x, ptr)
-
-extern int __get_user_bad(void);
-
-#define __get_user_asm(err,x,ptr,bwl,reg)                       \
-        __asm__ ("move" #bwl " %1,%0"                           \
-                 : "=d" (x)                                     \
-                 : "m" (*__ptr(ptr)))
-
-#define copy_from_user(to, from, n)             (memcpy(to, from, n), 0)
-#define copy_to_user(to, from, n)               (memcpy(to, from, n), 0)
-
-#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
-#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; })
-
-#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; })
-
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long
-strncpy_from_user(char *dst, const char *src, long count)
-{
-        char *tmp;
-        strncpy(dst, src, count);
-        for (tmp = dst; *tmp && count > 0; tmp++, count--)
-                ;
-        return(tmp - dst); /* DAVIDM should we count a NUL ?  check getname */
-}
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-static inline long strnlen_user(const char *src, long n)
-{
-        return(strlen(src) + 1); /* DAVIDM make safer */
-}
-
-#define strlen_user(str) strnlen_user(str, 32767)
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long
-__clear_user(void *to, unsigned long n)
-{
-        memset(to, 0, n);
-        return 0;
-}
-
-#define clear_user(to,n)        __clear_user(to,n)
-
-#endif /* _M68KNOMMU_UACCESS_H */
diff --git a/arch/m68knommu/include/asm/ucontext.h b/arch/m68knommu/include/asm/ucontext.h
deleted file mode 100644
index 713a27f901cd..000000000000
--- a/arch/m68knommu/include/asm/ucontext.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef _M68KNOMMU_UCONTEXT_H
-#define _M68KNOMMU_UCONTEXT_H
-
-typedef int greg_t;
-#define NGREG 18
-typedef greg_t gregset_t[NGREG];
-
-typedef struct fpregset {
-        int f_pcr;
-        int f_psr;
-        int f_fpiaddr;
-        int f_fpregs[8][3];
-} fpregset_t;
-
-struct mcontext {
-        int version;
-        gregset_t gregs;
-        fpregset_t fpregs;
-};
-
-#define MCONTEXT_VERSION 2
-
-struct ucontext {
-        unsigned long     uc_flags;
-        struct ucontext  *uc_link;
-        stack_t           uc_stack;
-        struct mcontext   uc_mcontext;
-        unsigned long     uc_filler[80];
-        sigset_t          uc_sigmask;   /* mask last for extensibility */
-};
-
-#endif
diff --git a/arch/m68knommu/include/asm/unaligned.h b/arch/m68knommu/include/asm/unaligned.h
deleted file mode 100644
index eb1ea4cb9a59..000000000000
--- a/arch/m68knommu/include/asm/unaligned.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASM_M68KNOMMU_UNALIGNED_H
-#define _ASM_M68KNOMMU_UNALIGNED_H
-
-
-#ifdef CONFIG_COLDFIRE
-#include <linux/unaligned/be_struct.h>
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned   __get_unaligned_be
-#define put_unaligned   __put_unaligned_be
-
-#else
-/*
- * The m68k can do unaligned accesses itself. 
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned   __get_unaligned_be
-#define put_unaligned   __put_unaligned_be
-
-#endif
-
-#endif /* _ASM_M68KNOMMU_UNALIGNED_H */
diff --git a/arch/m68knommu/include/asm/unistd.h b/arch/m68knommu/include/asm/unistd.h
deleted file mode 100644
index b034a2f7b444..000000000000
--- a/arch/m68knommu/include/asm/unistd.h
+++ /dev/null
@@ -1,372 +0,0 @@
-#ifndef _ASM_M68K_UNISTD_H_
-#define _ASM_M68K_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_restart_syscall      0
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-#define __NR_waitpid              7
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_time                13
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_chown               16
-#define __NR_break               17
-#define __NR_oldstat             18
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-#define __NR_umount              22
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_stime               25
-#define __NR_ptrace              26
-#define __NR_alarm               27
-#define __NR_oldfstat            28
-#define __NR_pause               29
-#define __NR_utime               30
-#define __NR_stty                31
-#define __NR_gtty                32
-#define __NR_access              33
-#define __NR_nice                34
-#define __NR_ftime               35
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-#define __NR_prof                44
-#define __NR_brk                 45
-#define __NR_setgid              46
-#define __NR_getgid              47
-#define __NR_signal              48
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_acct                51
-#define __NR_umount2             52
-#define __NR_lock                53
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-#define __NR_mpx                 56
-#define __NR_setpgid             57
-#define __NR_ulimit              58
-#define __NR_oldolduname         59
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_getpgrp             65
-#define __NR_setsid              66
-#define __NR_sigaction           67
-#define __NR_sgetmask            68
-#define __NR_ssetmask            69
-#define __NR_setreuid            70
-#define __NR_setregid            71
-#define __NR_sigsuspend          72
-#define __NR_sigpending          73
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-#define __NR_getrlimit           76
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-#define __NR_select              82
-#define __NR_symlink             83
-#define __NR_oldlstat            84
-#define __NR_readlink            85
-#define __NR_uselib              86
-#define __NR_swapon              87
-#define __NR_reboot              88
-#define __NR_readdir             89
-#define __NR_mmap                90
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_fchown              95
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-#define __NR_profil              98
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-#define __NR_ioperm             101
-#define __NR_socketcall         102
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-#define __NR_olduname           109
-#define __NR_iopl               /* 110 */ not supported
-#define __NR_vhangup            111
-#define __NR_idle               /* 112 */ Obsolete
-#define __NR_vm86               /* 113 */ not supported
-#define __NR_wait4              114
-#define __NR_swapoff            115
-#define __NR_sysinfo            116
-#define __NR_ipc                117
-#define __NR_fsync              118
-#define __NR_sigreturn          119
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-#define __NR_cacheflush         123
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-#define __NR_sigprocmask        126
-#define __NR_create_module      127
-#define __NR_init_module        128
-#define __NR_delete_module      129
-#define __NR_get_kernel_syms    130
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-#define __NR_sysfs              135
-#define __NR_personality        136
-#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR_getdents           141
-#define __NR__newselect         142
-#define __NR_flock              143
-#define __NR_msync              144
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_getsid             147
-#define __NR_fdatasync          148
-#define __NR__sysctl            149
-#define __NR_mlock              150
-#define __NR_munlock            151
-#define __NR_mlockall           152
-#define __NR_munlockall         153
-#define __NR_sched_setparam             154
-#define __NR_sched_getparam             155
-#define __NR_sched_setscheduler         156
-#define __NR_sched_getscheduler         157
-#define __NR_sched_yield                158
-#define __NR_sched_get_priority_max     159
-#define __NR_sched_get_priority_min     160
-#define __NR_sched_rr_get_interval      161
-#define __NR_nanosleep          162
-#define __NR_mremap             163
-#define __NR_setresuid          164
-#define __NR_getresuid          165
-#define __NR_getpagesize        166
-#define __NR_query_module       167
-#define __NR_poll               168
-#define __NR_nfsservctl         169
-#define __NR_setresgid          170
-#define __NR_getresgid          171
-#define __NR_prctl              172
-#define __NR_rt_sigreturn       173
-#define __NR_rt_sigaction       174
-#define __NR_rt_sigprocmask     175
-#define __NR_rt_sigpending      176
-#define __NR_rt_sigtimedwait    177
-#define __NR_rt_sigqueueinfo    178
-#define __NR_rt_sigsuspend      179
-#define __NR_pread64            180
-#define __NR_pwrite64           181
-#define __NR_lchown             182
-#define __NR_getcwd             183
-#define __NR_capget             184
-#define __NR_capset             185
-#define __NR_sigaltstack        186
-#define __NR_sendfile           187
-#define __NR_getpmsg            188     /* some people actually want streams */
-#define __NR_putpmsg            189     /* some people actually want streams */
-#define __NR_vfork              190
-#define __NR_ugetrlimit         191
-#define __NR_mmap2              192
-#define __NR_truncate64         193
-#define __NR_ftruncate64        194
-#define __NR_stat64             195
-#define __NR_lstat64            196
-#define __NR_fstat64            197
-#define __NR_chown32            198
-#define __NR_getuid32           199
-#define __NR_getgid32           200
-#define __NR_geteuid32          201
-#define __NR_getegid32          202
-#define __NR_setreuid32         203
-#define __NR_setregid32         204
-#define __NR_getgroups32        205
-#define __NR_setgroups32        206
-#define __NR_fchown32           207
-#define __NR_setresuid32        208
-#define __NR_getresuid32        209
-#define __NR_setresgid32        210
-#define __NR_getresgid32        211
-#define __NR_lchown32           212
-#define __NR_setuid32           213
-#define __NR_setgid32           214
-#define __NR_setfsuid32         215
-#define __NR_setfsgid32         216
-#define __NR_pivot_root         217
-#define __NR_getdents64         220
-#define __NR_gettid             221
-#define __NR_tkill              222
-#define __NR_setxattr           223
-#define __NR_lsetxattr          224
-#define __NR_fsetxattr          225
-#define __NR_getxattr           226
-#define __NR_lgetxattr          227
-#define __NR_fgetxattr          228
-#define __NR_listxattr          229
-#define __NR_llistxattr         230
-#define __NR_flistxattr         231
-#define __NR_removexattr        232
-#define __NR_lremovexattr       233
-#define __NR_fremovexattr       234
-#define __NR_futex              235
-#define __NR_sendfile64         236
-#define __NR_mincore            237
-#define __NR_madvise            238
-#define __NR_fcntl64            239
-#define __NR_readahead          240
-#define __NR_io_setup           241
-#define __NR_io_destroy         242
-#define __NR_io_getevents       243
-#define __NR_io_submit          244
-#define __NR_io_cancel          245
-#define __NR_fadvise64          246
-#define __NR_exit_group         247
-#define __NR_lookup_dcookie     248
-#define __NR_epoll_create       249
-#define __NR_epoll_ctl          250
-#define __NR_epoll_wait         251
-#define __NR_remap_file_pages   252
-#define __NR_set_tid_address    253
-#define __NR_timer_create       254
-#define __NR_timer_settime      255
-#define __NR_timer_gettime      256
-#define __NR_timer_getoverrun   257
-#define __NR_timer_delete       258
-#define __NR_clock_settime      259
-#define __NR_clock_gettime      260
-#define __NR_clock_getres       261
-#define __NR_clock_nanosleep    262
-#define __NR_statfs64           263
-#define __NR_fstatfs64          264
-#define __NR_tgkill             265
-#define __NR_utimes             266
-#define __NR_fadvise64_64       267
-#define __NR_mbind              268
-#define __NR_get_mempolicy      269
-#define __NR_set_mempolicy      270
-#define __NR_mq_open            271
-#define __NR_mq_unlink          272
-#define __NR_mq_timedsend       273
-#define __NR_mq_timedreceive    274
-#define __NR_mq_notify          275
-#define __NR_mq_getsetattr      276
-#define __NR_waitid             277
-#define __NR_vserver            278
-#define __NR_add_key            279
-#define __NR_request_key        280
-#define __NR_keyctl             281
-#define __NR_ioprio_set         282
-#define __NR_ioprio_get         283
-#define __NR_inotify_init       284
-#define __NR_inotify_add_watch  285
-#define __NR_inotify_rm_watch   286
-#define __NR_migrate_pages      287
-#define __NR_openat             288
-#define __NR_mkdirat            289
-#define __NR_mknodat            290
-#define __NR_fchownat           291
-#define __NR_futimesat          292
-#define __NR_fstatat64          293
-#define __NR_unlinkat           294
-#define __NR_renameat           295
-#define __NR_linkat             296
-#define __NR_symlinkat          297
-#define __NR_readlinkat         298
-#define __NR_fchmodat           299
-#define __NR_faccessat          300
-#define __NR_pselect6           301
-#define __NR_ppoll              302
-#define __NR_unshare            303
-#define __NR_set_robust_list    304
-#define __NR_get_robust_list    305
-#define __NR_splice             306
-#define __NR_sync_file_range    307
-#define __NR_tee                308
-#define __NR_vmsplice           309
-#define __NR_move_pages         310
-#define __NR_sched_setaffinity  311
-#define __NR_sched_getaffinity  312
-#define __NR_kexec_load         313
-#define __NR_getcpu             314
-#define __NR_epoll_pwait        315
-#define __NR_utimensat          316
-#define __NR_signalfd           317
-#define __NR_timerfd_create     318
-#define __NR_eventfd            319
-#define __NR_fallocate          320
-#define __NR_timerfd_settime    321
-#define __NR_timerfd_gettime    322
-#define __NR_signalfd4          323
-#define __NR_eventfd2           324
-#define __NR_epoll_create1      325
-#define __NR_dup3               326
-#define __NR_pipe2              327
-#define __NR_inotify_init1      328
-
-#ifdef __KERNEL__
-
-#define NR_syscalls             329
-
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_M68K_UNISTD_H_ */
diff --git a/arch/m68knommu/include/asm/user.h b/arch/m68knommu/include/asm/user.h
deleted file mode 100644
index a5a555b761c4..000000000000
--- a/arch/m68knommu/include/asm/user.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/user.h>