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authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-17 12:52:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-17 12:52:43 -0400
commit66bc4a6f34a950c7aede597c578352c3eba82017 (patch)
treed8005bd9abc0209cff47072d7e48cf19fddc52f5 /arch/m68knommu
parent96c015b75feaaa67c8744229937bd9c35919d16b (diff)
parent2985709d7f3078c7609ae7f16affc0fb478d7d7a (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (53 commits) m68knommu: Make PAGE_SIZE available to assembly files. m68knommu: fix ColdFire definition of CLOCK_TICK_RATE m68knommu: set multi-function pins for ethernet when enabled m68knommu: remove special interrupt handling code for ne2k support m68knommu: relax IO_SPACE_LIMIT setting m68knommu: remove ColdFire direct interrupt register access m68knommu: create a speciailized ColdFire 5272 interrupt controller m68knommu: add support for second interrupt controller of ColdFire 5249 m68knommu: clean up old ColdFire timer irq setup m68knommu: map ColdFire interrupts to correct masking bits m68knommu: clean up ColdFire 532x CPU timer setup m68knommu: simplify ColdFire "timers" clock initialization m68knommu: support code to mask external interrupts on old ColdFire CPU's m68knommu: merge old ColdFire interrupt controller masking macros m68knommu: remove duplicate ColdFire mcf_autovector() code m68knommu: move ColdFire INTC definitions to new include file m68knommu: mask off all interrupts in ColdFire intc-simr controller m68knommu: remove timer device interrupt setup for ColdFire 532x m68knommu: remove interrupt masking from ColdFire pit timer m68knommu: remove unecessary interrupt level setting in ColdFire 520x setup ...
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/Kconfig6
-rw-r--r--arch/m68knommu/kernel/irq.c26
-rw-r--r--arch/m68knommu/kernel/time.c2
-rw-r--r--arch/m68knommu/lib/checksum.c11
-rw-r--r--arch/m68knommu/platform/5206/Makefile2
-rw-r--r--arch/m68knommu/platform/5206/config.c56
-rw-r--r--arch/m68knommu/platform/5206/gpio.c49
-rw-r--r--arch/m68knommu/platform/5206e/Makefile2
-rw-r--r--arch/m68knommu/platform/5206e/config.c58
-rw-r--r--arch/m68knommu/platform/5206e/gpio.c49
-rw-r--r--arch/m68knommu/platform/520x/Makefile2
-rw-r--r--arch/m68knommu/platform/520x/config.c30
-rw-r--r--arch/m68knommu/platform/520x/gpio.c211
-rw-r--r--arch/m68knommu/platform/523x/Makefile2
-rw-r--r--arch/m68knommu/platform/523x/config.c66
-rw-r--r--arch/m68knommu/platform/523x/gpio.c283
-rw-r--r--arch/m68knommu/platform/5249/Makefile2
-rw-r--r--arch/m68knommu/platform/5249/config.c49
-rw-r--r--arch/m68knommu/platform/5249/gpio.c65
-rw-r--r--arch/m68knommu/platform/5249/intc2.c59
-rw-r--r--arch/m68knommu/platform/5272/Makefile2
-rw-r--r--arch/m68knommu/platform/5272/config.c78
-rw-r--r--arch/m68knommu/platform/5272/gpio.c81
-rw-r--r--arch/m68knommu/platform/5272/intc.c138
-rw-r--r--arch/m68knommu/platform/527x/Makefile2
-rw-r--r--arch/m68knommu/platform/527x/config.c49
-rw-r--r--arch/m68knommu/platform/527x/gpio.c607
-rw-r--r--arch/m68knommu/platform/528x/Makefile2
-rw-r--r--arch/m68knommu/platform/528x/config.c51
-rw-r--r--arch/m68knommu/platform/528x/gpio.c438
-rw-r--r--arch/m68knommu/platform/5307/Makefile2
-rw-r--r--arch/m68knommu/platform/5307/config.c65
-rw-r--r--arch/m68knommu/platform/5307/gpio.c49
-rw-r--r--arch/m68knommu/platform/532x/Makefile2
-rw-r--r--arch/m68knommu/platform/532x/config.c53
-rw-r--r--arch/m68knommu/platform/532x/gpio.c337
-rw-r--r--arch/m68knommu/platform/5407/Makefile2
-rw-r--r--arch/m68knommu/platform/5407/config.c68
-rw-r--r--arch/m68knommu/platform/5407/gpio.c49
-rw-r--r--arch/m68knommu/platform/68328/ints.c72
-rw-r--r--arch/m68knommu/platform/68360/ints.c44
-rw-r--r--arch/m68knommu/platform/coldfire/Makefile21
-rw-r--r--arch/m68knommu/platform/coldfire/gpio.c127
-rw-r--r--arch/m68knommu/platform/coldfire/intc-2.c93
-rw-r--r--arch/m68knommu/platform/coldfire/intc-simr.c78
-rw-r--r--arch/m68knommu/platform/coldfire/intc.c153
-rw-r--r--arch/m68knommu/platform/coldfire/pinmux.c28
-rw-r--r--arch/m68knommu/platform/coldfire/pit.c8
-rw-r--r--arch/m68knommu/platform/coldfire/timers.c18
-rw-r--r--arch/m68knommu/platform/coldfire/vectors.c20
50 files changed, 3122 insertions, 645 deletions
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 534376299a99..e2201b90aa22 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -47,6 +47,10 @@ config GENERIC_FIND_NEXT_BIT
47 bool 47 bool
48 default y 48 default y
49 49
50config GENERIC_GPIO
51 bool
52 default n
53
50config GENERIC_HWEIGHT 54config GENERIC_HWEIGHT
51 bool 55 bool
52 default y 56 default y
@@ -182,6 +186,8 @@ config M527x
182config COLDFIRE 186config COLDFIRE
183 bool 187 bool
184 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407) 188 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407)
189 select GENERIC_GPIO
190 select ARCH_REQUIRE_GPIOLIB
185 default y 191 default y
186 192
187config CLOCK_SET 193config CLOCK_SET
diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c
index 56e0f4c55a67..c9cac36d4422 100644
--- a/arch/m68knommu/kernel/irq.c
+++ b/arch/m68knommu/kernel/irq.c
@@ -29,32 +29,6 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
29 set_irq_regs(oldregs); 29 set_irq_regs(oldregs);
30} 30}
31 31
32void ack_bad_irq(unsigned int irq)
33{
34 printk(KERN_ERR "IRQ: unexpected irq=%d\n", irq);
35}
36
37static struct irq_chip m_irq_chip = {
38 .name = "M68K-INTC",
39 .enable = enable_vector,
40 .disable = disable_vector,
41 .ack = ack_vector,
42};
43
44void __init init_IRQ(void)
45{
46 int irq;
47
48 init_vectors();
49
50 for (irq = 0; (irq < NR_IRQS); irq++) {
51 irq_desc[irq].status = IRQ_DISABLED;
52 irq_desc[irq].action = NULL;
53 irq_desc[irq].depth = 1;
54 irq_desc[irq].chip = &m_irq_chip;
55 }
56}
57
58int show_interrupts(struct seq_file *p, void *v) 32int show_interrupts(struct seq_file *p, void *v)
59{ 33{
60 struct irqaction *ap; 34 struct irqaction *ap;
diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c
index d182b2f72211..c2aa717de08a 100644
--- a/arch/m68knommu/kernel/time.c
+++ b/arch/m68knommu/kernel/time.c
@@ -69,7 +69,7 @@ static unsigned long read_rtc_mmss(void)
69 if ((year += 1900) < 1970) 69 if ((year += 1900) < 1970)
70 year += 100; 70 year += 100;
71 71
72 return mktime(year, mon, day, hour, min, sec);; 72 return mktime(year, mon, day, hour, min, sec);
73} 73}
74 74
75unsigned long read_persistent_clock(void) 75unsigned long read_persistent_clock(void)
diff --git a/arch/m68knommu/lib/checksum.c b/arch/m68knommu/lib/checksum.c
index 269d83bfbbe1..eccf25d3d73e 100644
--- a/arch/m68knommu/lib/checksum.c
+++ b/arch/m68knommu/lib/checksum.c
@@ -92,6 +92,7 @@ out:
92 return result; 92 return result;
93} 93}
94 94
95#ifdef CONFIG_COLDFIRE
95/* 96/*
96 * This is a version of ip_compute_csum() optimized for IP headers, 97 * This is a version of ip_compute_csum() optimized for IP headers,
97 * which always checksum on 4 octet boundaries. 98 * which always checksum on 4 octet boundaries.
@@ -100,6 +101,7 @@ __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
100{ 101{
101 return (__force __sum16)~do_csum(iph,ihl*4); 102 return (__force __sum16)~do_csum(iph,ihl*4);
102} 103}
104#endif
103 105
104/* 106/*
105 * computes the checksum of a memory block at buff, length len, 107 * computes the checksum of a memory block at buff, length len,
@@ -127,15 +129,6 @@ __wsum csum_partial(const void *buff, int len, __wsum sum)
127EXPORT_SYMBOL(csum_partial); 129EXPORT_SYMBOL(csum_partial);
128 130
129/* 131/*
130 * this routine is used for miscellaneous IP-like checksums, mainly
131 * in icmp.c
132 */
133__sum16 ip_compute_csum(const void *buff, int len)
134{
135 return (__force __sum16)~do_csum(buff,len);
136}
137
138/*
139 * copy from fs while checksumming, otherwise like csum_partial 132 * copy from fs while checksumming, otherwise like csum_partial
140 */ 133 */
141 134
diff --git a/arch/m68knommu/platform/5206/Makefile b/arch/m68knommu/platform/5206/Makefile
index a439d9ab3f27..113c33390064 100644
--- a/arch/m68knommu/platform/5206/Makefile
+++ b/arch/m68knommu/platform/5206/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68knommu/platform/5206/config.c
index f6f79874e9af..9c335465e66d 100644
--- a/arch/m68knommu/platform/5206/config.c
+++ b/arch/m68knommu/platform/5206/config.c
@@ -49,11 +49,11 @@ static void __init m5206_uart_init_line(int line, int irq)
49 if (line == 0) { 49 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 52 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) { 53 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 56 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 } 57 }
58} 58}
59 59
@@ -68,38 +68,19 @@ static void __init m5206_uarts_init(void)
68 68
69/***************************************************************************/ 69/***************************************************************************/
70 70
71void mcf_autovector(unsigned int vec) 71static void __init m5206_timers_init(void)
72{ 72{
73 volatile unsigned char *mbar; 73 /* Timer1 is always used as system timer */
74 unsigned char icr; 74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 if ((vec >= 25) && (vec <= 31)) { 76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77 vec -= 25; 77
78 mbar = (volatile unsigned char *) MCF_MBAR; 78#ifdef CONFIG_HIGHPROFILE
79 icr = MCFSIM_ICR_AUTOVEC | (vec << 3); 79 /* Timer2 is to be used as a high speed profile timer */
80 *(mbar + MCFSIM_ICR1 + vec) = icr; 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 vec = 0x1 << (vec + 1); 81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 mcf_setimr(mcf_getimr() & ~vec); 82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83 } 83#endif
84}
85
86/***************************************************************************/
87
88void mcf_settimericr(unsigned int timer, unsigned int level)
89{
90 volatile unsigned char *icrp;
91 unsigned int icr, imr;
92
93 if (timer <= 2) {
94 switch (timer) {
95 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
96 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
97 }
98
99 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
100 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
101 mcf_setimr(mcf_getimr() & ~imr);
102 }
103} 84}
104 85
105/***************************************************************************/ 86/***************************************************************************/
@@ -117,15 +98,20 @@ void m5206_cpu_reset(void)
117 98
118void __init config_BSP(char *commandp, int size) 99void __init config_BSP(char *commandp, int size)
119{ 100{
120 mcf_setimr(MCFSIM_IMR_MASKALL);
121 mach_reset = m5206_cpu_reset; 101 mach_reset = m5206_cpu_reset;
102 m5206_timers_init();
103 m5206_uarts_init();
104
105 /* Only support the external interrupts on their primary level */
106 mcf_mapirq2imr(25, MCFINTC_EINT1);
107 mcf_mapirq2imr(28, MCFINTC_EINT4);
108 mcf_mapirq2imr(31, MCFINTC_EINT7);
122} 109}
123 110
124/***************************************************************************/ 111/***************************************************************************/
125 112
126static int __init init_BSP(void) 113static int __init init_BSP(void)
127{ 114{
128 m5206_uarts_init();
129 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices)); 115 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
130 return 0; 116 return 0;
131} 117}
diff --git a/arch/m68knommu/platform/5206/gpio.c b/arch/m68knommu/platform/5206/gpio.c
new file mode 100644
index 000000000000..60f779ce1651
--- /dev/null
+++ b/arch/m68knommu/platform/5206/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5206e/Makefile b/arch/m68knommu/platform/5206e/Makefile
index a439d9ab3f27..113c33390064 100644
--- a/arch/m68knommu/platform/5206e/Makefile
+++ b/arch/m68knommu/platform/5206e/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 65887799db81..0f41ba82a3b5 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -15,6 +15,7 @@
15#include <asm/machdep.h> 15#include <asm/machdep.h>
16#include <asm/coldfire.h> 16#include <asm/coldfire.h>
17#include <asm/mcfsim.h> 17#include <asm/mcfsim.h>
18#include <asm/mcfuart.h>
18#include <asm/mcfdma.h> 19#include <asm/mcfdma.h>
19#include <asm/mcfuart.h> 20#include <asm/mcfuart.h>
20 21
@@ -49,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq)
49 if (line == 0) { 50 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 51 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 52 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 53 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) { 54 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 55 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 56 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 57 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 } 58 }
58} 59}
59 60
@@ -68,38 +69,19 @@ static void __init m5206e_uarts_init(void)
68 69
69/***************************************************************************/ 70/***************************************************************************/
70 71
71void mcf_autovector(unsigned int vec) 72static void __init m5206e_timers_init(void)
72{
73 volatile unsigned char *mbar;
74 unsigned char icr;
75
76 if ((vec >= 25) && (vec <= 31)) {
77 vec -= 25;
78 mbar = (volatile unsigned char *) MCF_MBAR;
79 icr = MCFSIM_ICR_AUTOVEC | (vec << 3);
80 *(mbar + MCFSIM_ICR1 + vec) = icr;
81 vec = 0x1 << (vec + 1);
82 mcf_setimr(mcf_getimr() & ~vec);
83 }
84}
85
86/***************************************************************************/
87
88void mcf_settimericr(unsigned int timer, unsigned int level)
89{ 73{
90 volatile unsigned char *icrp; 74 /* Timer1 is always used as system timer */
91 unsigned int icr, imr; 75 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
92 76 MCF_MBAR + MCFSIM_TIMER1ICR);
93 if (timer <= 2) { 77 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
94 switch (timer) { 78
95 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 79#ifdef CONFIG_HIGHPROFILE
96 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 80 /* Timer2 is to be used as a high speed profile timer */
97 } 81 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
98 82 MCF_MBAR + MCFSIM_TIMER2ICR);
99 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 83 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
100 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 84#endif
101 mcf_setimr(mcf_getimr() & ~imr);
102 }
103} 85}
104 86
105/***************************************************************************/ 87/***************************************************************************/
@@ -117,8 +99,6 @@ void m5206e_cpu_reset(void)
117 99
118void __init config_BSP(char *commandp, int size) 100void __init config_BSP(char *commandp, int size)
119{ 101{
120 mcf_setimr(MCFSIM_IMR_MASKALL);
121
122#if defined(CONFIG_NETtel) 102#if defined(CONFIG_NETtel)
123 /* Copy command line from FLASH to local buffer... */ 103 /* Copy command line from FLASH to local buffer... */
124 memcpy(commandp, (char *) 0xf0004000, size); 104 memcpy(commandp, (char *) 0xf0004000, size);
@@ -126,13 +106,19 @@ void __init config_BSP(char *commandp, int size)
126#endif /* CONFIG_NETtel */ 106#endif /* CONFIG_NETtel */
127 107
128 mach_reset = m5206e_cpu_reset; 108 mach_reset = m5206e_cpu_reset;
109 m5206e_timers_init();
110 m5206e_uarts_init();
111
112 /* Only support the external interrupts on their primary level */
113 mcf_mapirq2imr(25, MCFINTC_EINT1);
114 mcf_mapirq2imr(28, MCFINTC_EINT4);
115 mcf_mapirq2imr(31, MCFINTC_EINT7);
129} 116}
130 117
131/***************************************************************************/ 118/***************************************************************************/
132 119
133static int __init init_BSP(void) 120static int __init init_BSP(void)
134{ 121{
135 m5206e_uarts_init();
136 platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices)); 122 platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices));
137 return 0; 123 return 0;
138} 124}
diff --git a/arch/m68knommu/platform/5206e/gpio.c b/arch/m68knommu/platform/5206e/gpio.c
new file mode 100644
index 000000000000..60f779ce1651
--- /dev/null
+++ b/arch/m68knommu/platform/5206e/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/520x/Makefile b/arch/m68knommu/platform/520x/Makefile
index a50e76acc8fd..435ab3483dc1 100644
--- a/arch/m68knommu/platform/520x/Makefile
+++ b/arch/m68knommu/platform/520x/Makefile
@@ -14,4 +14,4 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c
index 1c43a8aec69b..92614de42cd3 100644
--- a/arch/m68knommu/platform/520x/config.c
+++ b/arch/m68knommu/platform/520x/config.c
@@ -81,20 +81,11 @@ static struct platform_device *m520x_devices[] __initdata = {
81 81
82/***************************************************************************/ 82/***************************************************************************/
83 83
84#define INTC0 (MCF_MBAR + MCFICM_INTC0)
85
86static void __init m520x_uart_init_line(int line, int irq) 84static void __init m520x_uart_init_line(int line, int irq)
87{ 85{
88 u32 imr;
89 u16 par; 86 u16 par;
90 u8 par2; 87 u8 par2;
91 88
92 writeb(0x03, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
93
94 imr = readl(INTC0 + MCFINTC_IMRL);
95 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
96 writel(imr, INTC0 + MCFINTC_IMRL);
97
98 switch (line) { 89 switch (line) {
99 case 0: 90 case 0:
100 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 91 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
@@ -131,18 +122,8 @@ static void __init m520x_uarts_init(void)
131 122
132static void __init m520x_fec_init(void) 123static void __init m520x_fec_init(void)
133{ 124{
134 u32 imr;
135 u8 v; 125 u8 v;
136 126
137 /* Unmask FEC interrupts at ColdFire interrupt controller */
138 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 36);
139 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40);
140 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42);
141
142 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
143 imr &= ~0x0001FFF0;
144 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
145
146 /* Set multi-function pins to ethernet mode */ 127 /* Set multi-function pins to ethernet mode */
147 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC); 128 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
148 writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC); 129 writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
@@ -153,17 +134,6 @@ static void __init m520x_fec_init(void)
153 134
154/***************************************************************************/ 135/***************************************************************************/
155 136
156/*
157 * Program the vector to be an auto-vectored.
158 */
159
160void mcf_autovector(unsigned int vec)
161{
162 /* Everything is auto-vectored on the 520x devices */
163}
164
165/***************************************************************************/
166
167static void m520x_cpu_reset(void) 137static void m520x_cpu_reset(void)
168{ 138{
169 local_irq_disable(); 139 local_irq_disable();
diff --git a/arch/m68knommu/platform/520x/gpio.c b/arch/m68knommu/platform/520x/gpio.c
new file mode 100644
index 000000000000..15b5bb62a698
--- /dev/null
+++ b/arch/m68knommu/platform/520x/gpio.c
@@ -0,0 +1,211 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "BUSCTL",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 4,
50 },
51 .pddr = MCFGPIO_PDDR_BUSCTL,
52 .podr = MCFGPIO_PODR_BUSCTL,
53 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
54 .setr = MCFGPIO_PPDSDR_BUSCTL,
55 .clrr = MCFGPIO_PCLRR_BUSCTL,
56 },
57 {
58 .gpio_chip = {
59 .label = "BE",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 4,
68 },
69 .pddr = MCFGPIO_PDDR_BE,
70 .podr = MCFGPIO_PODR_BE,
71 .ppdr = MCFGPIO_PPDSDR_BE,
72 .setr = MCFGPIO_PPDSDR_BE,
73 .clrr = MCFGPIO_PCLRR_BE,
74 },
75 {
76 .gpio_chip = {
77 .label = "CS",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 25,
85 .ngpio = 3,
86 },
87 .pddr = MCFGPIO_PDDR_CS,
88 .podr = MCFGPIO_PODR_CS,
89 .ppdr = MCFGPIO_PPDSDR_CS,
90 .setr = MCFGPIO_PPDSDR_CS,
91 .clrr = MCFGPIO_PCLRR_CS,
92 },
93 {
94 .gpio_chip = {
95 .label = "FECI2C",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = MCFGPIO_PDDR_FECI2C,
106 .podr = MCFGPIO_PODR_FECI2C,
107 .ppdr = MCFGPIO_PPDSDR_FECI2C,
108 .setr = MCFGPIO_PPDSDR_FECI2C,
109 .clrr = MCFGPIO_PCLRR_FECI2C,
110 },
111 {
112 .gpio_chip = {
113 .label = "QSPI",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = MCFGPIO_PDDR_QSPI,
124 .podr = MCFGPIO_PODR_QSPI,
125 .ppdr = MCFGPIO_PPDSDR_QSPI,
126 .setr = MCFGPIO_PPDSDR_QSPI,
127 .clrr = MCFGPIO_PCLRR_QSPI,
128 },
129 {
130 .gpio_chip = {
131 .label = "TIMER",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 48,
139 .ngpio = 4,
140 },
141 .pddr = MCFGPIO_PDDR_TIMER,
142 .podr = MCFGPIO_PODR_TIMER,
143 .ppdr = MCFGPIO_PPDSDR_TIMER,
144 .setr = MCFGPIO_PPDSDR_TIMER,
145 .clrr = MCFGPIO_PCLRR_TIMER,
146 },
147 {
148 .gpio_chip = {
149 .label = "UART",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 8,
158 },
159 .pddr = MCFGPIO_PDDR_UART,
160 .podr = MCFGPIO_PODR_UART,
161 .ppdr = MCFGPIO_PPDSDR_UART,
162 .setr = MCFGPIO_PPDSDR_UART,
163 .clrr = MCFGPIO_PCLRR_UART,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECH",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 8,
176 },
177 .pddr = MCFGPIO_PDDR_FECH,
178 .podr = MCFGPIO_PODR_FECH,
179 .ppdr = MCFGPIO_PPDSDR_FECH,
180 .setr = MCFGPIO_PPDSDR_FECH,
181 .clrr = MCFGPIO_PCLRR_FECH,
182 },
183 {
184 .gpio_chip = {
185 .label = "FECL",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = MCFGPIO_PDDR_FECL,
196 .podr = MCFGPIO_PODR_FECL,
197 .ppdr = MCFGPIO_PPDSDR_FECL,
198 .setr = MCFGPIO_PPDSDR_FECL,
199 .clrr = MCFGPIO_PCLRR_FECL,
200 },
201};
202
203static int __init mcf_gpio_init(void)
204{
205 unsigned i = 0;
206 while (i < ARRAY_SIZE(mcf_gpio_chips))
207 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
208 return 0;
209}
210
211core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/523x/Makefile b/arch/m68knommu/platform/523x/Makefile
index 5694d593f029..b8f9b45440c2 100644
--- a/arch/m68knommu/platform/523x/Makefile
+++ b/arch/m68knommu/platform/523x/Makefile
@@ -14,4 +14,4 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c
index 961fefebca14..6ba84f2aa397 100644
--- a/arch/m68knommu/platform/523x/config.c
+++ b/arch/m68knommu/platform/523x/config.c
@@ -82,66 +82,20 @@ static struct platform_device *m523x_devices[] __initdata = {
82 82
83/***************************************************************************/ 83/***************************************************************************/
84 84
85#define INTC0 (MCF_MBAR + MCFICM_INTC0)
86
87static void __init m523x_uart_init_line(int line, int irq)
88{
89 u32 imr;
90
91 if ((line < 0) || (line > 2))
92 return;
93
94 writeb(0x30+line, (INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line));
95
96 imr = readl(INTC0 + MCFINTC_IMRL);
97 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
98 writel(imr, INTC0 + MCFINTC_IMRL);
99}
100
101static void __init m523x_uarts_init(void)
102{
103 const int nrlines = ARRAY_SIZE(m523x_uart_platform);
104 int line;
105
106 for (line = 0; (line < nrlines); line++)
107 m523x_uart_init_line(line, m523x_uart_platform[line].irq);
108}
109
110/***************************************************************************/
111
112static void __init m523x_fec_init(void) 85static void __init m523x_fec_init(void)
113{ 86{
114 u32 imr; 87 u16 par;
115 88 u8 v;
116 /* Unmask FEC interrupts at ColdFire interrupt controller */ 89
117 writeb(0x28, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 23); 90 /* Set multi-function pins to ethernet use */
118 writeb(0x27, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 27); 91 par = readw(MCF_IPSBAR + 0x100082);
119 writeb(0x26, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 29); 92 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
120 93 v = readb(MCF_IPSBAR + 0x100078);
121 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH); 94 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
122 imr &= ~0xf;
123 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
124 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
125 imr &= ~0xff800001;
126 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
127}
128
129/***************************************************************************/
130
131void mcf_disableall(void)
132{
133 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
134 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
135} 95}
136 96
137/***************************************************************************/ 97/***************************************************************************/
138 98
139void mcf_autovector(unsigned int vec)
140{
141 /* Everything is auto-vectored on the 523x */
142}
143/***************************************************************************/
144
145static void m523x_cpu_reset(void) 99static void m523x_cpu_reset(void)
146{ 100{
147 local_irq_disable(); 101 local_irq_disable();
@@ -152,16 +106,14 @@ static void m523x_cpu_reset(void)
152 106
153void __init config_BSP(char *commandp, int size) 107void __init config_BSP(char *commandp, int size)
154{ 108{
155 mcf_disableall();
156 mach_reset = m523x_cpu_reset; 109 mach_reset = m523x_cpu_reset;
157 m523x_uarts_init();
158 m523x_fec_init();
159} 110}
160 111
161/***************************************************************************/ 112/***************************************************************************/
162 113
163static int __init init_BSP(void) 114static int __init init_BSP(void)
164{ 115{
116 m523x_fec_init();
165 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices)); 117 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices));
166 return 0; 118 return 0;
167} 119}
diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68knommu/platform/523x/gpio.c
new file mode 100644
index 000000000000..f02840d54d3c
--- /dev/null
+++ b/arch/m68knommu/platform/523x/gpio.c
@@ -0,0 +1,283 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "ADDR",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 13,
49 .ngpio = 3,
50 },
51 .pddr = MCFGPIO_PDDR_ADDR,
52 .podr = MCFGPIO_PODR_ADDR,
53 .ppdr = MCFGPIO_PPDSDR_ADDR,
54 .setr = MCFGPIO_PPDSDR_ADDR,
55 .clrr = MCFGPIO_PCLRR_ADDR,
56 },
57 {
58 .gpio_chip = {
59 .label = "DATAH",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 8,
68 },
69 .pddr = MCFGPIO_PDDR_DATAH,
70 .podr = MCFGPIO_PODR_DATAH,
71 .ppdr = MCFGPIO_PPDSDR_DATAH,
72 .setr = MCFGPIO_PPDSDR_DATAH,
73 .clrr = MCFGPIO_PCLRR_DATAH,
74 },
75 {
76 .gpio_chip = {
77 .label = "DATAL",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 8,
86 },
87 .pddr = MCFGPIO_PDDR_DATAL,
88 .podr = MCFGPIO_PODR_DATAL,
89 .ppdr = MCFGPIO_PPDSDR_DATAL,
90 .setr = MCFGPIO_PPDSDR_DATAL,
91 .clrr = MCFGPIO_PCLRR_DATAL,
92 },
93 {
94 .gpio_chip = {
95 .label = "BUSCTL",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 8,
104 },
105 .pddr = MCFGPIO_PDDR_BUSCTL,
106 .podr = MCFGPIO_PODR_BUSCTL,
107 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
108 .setr = MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = MCFGPIO_PCLRR_BUSCTL,
110 },
111 {
112 .gpio_chip = {
113 .label = "BS",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = MCFGPIO_PDDR_BS,
124 .podr = MCFGPIO_PODR_BS,
125 .ppdr = MCFGPIO_PPDSDR_BS,
126 .setr = MCFGPIO_PPDSDR_BS,
127 .clrr = MCFGPIO_PCLRR_BS,
128 },
129 {
130 .gpio_chip = {
131 .label = "CS",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 49,
139 .ngpio = 7,
140 },
141 .pddr = MCFGPIO_PDDR_CS,
142 .podr = MCFGPIO_PODR_CS,
143 .ppdr = MCFGPIO_PPDSDR_CS,
144 .setr = MCFGPIO_PPDSDR_CS,
145 .clrr = MCFGPIO_PCLRR_CS,
146 },
147 {
148 .gpio_chip = {
149 .label = "SDRAM",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 6,
158 },
159 .pddr = MCFGPIO_PDDR_SDRAM,
160 .podr = MCFGPIO_PODR_SDRAM,
161 .ppdr = MCFGPIO_PPDSDR_SDRAM,
162 .setr = MCFGPIO_PPDSDR_SDRAM,
163 .clrr = MCFGPIO_PCLRR_SDRAM,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECI2C",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 4,
176 },
177 .pddr = MCFGPIO_PDDR_FECI2C,
178 .podr = MCFGPIO_PODR_FECI2C,
179 .ppdr = MCFGPIO_PPDSDR_FECI2C,
180 .setr = MCFGPIO_PPDSDR_FECI2C,
181 .clrr = MCFGPIO_PCLRR_FECI2C,
182 },
183 {
184 .gpio_chip = {
185 .label = "UARTH",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 2,
194 },
195 .pddr = MCFGPIO_PDDR_UARTH,
196 .podr = MCFGPIO_PODR_UARTH,
197 .ppdr = MCFGPIO_PPDSDR_UARTH,
198 .setr = MCFGPIO_PPDSDR_UARTH,
199 .clrr = MCFGPIO_PCLRR_UARTH,
200 },
201 {
202 .gpio_chip = {
203 .label = "UARTL",
204 .request = mcf_gpio_request,
205 .free = mcf_gpio_free,
206 .direction_input = mcf_gpio_direction_input,
207 .direction_output = mcf_gpio_direction_output,
208 .get = mcf_gpio_get_value,
209 .set = mcf_gpio_set_value_fast,
210 .base = 80,
211 .ngpio = 8,
212 },
213 .pddr = MCFGPIO_PDDR_UARTL,
214 .podr = MCFGPIO_PODR_UARTL,
215 .ppdr = MCFGPIO_PPDSDR_UARTL,
216 .setr = MCFGPIO_PPDSDR_UARTL,
217 .clrr = MCFGPIO_PCLRR_UARTL,
218 },
219 {
220 .gpio_chip = {
221 .label = "QSPI",
222 .request = mcf_gpio_request,
223 .free = mcf_gpio_free,
224 .direction_input = mcf_gpio_direction_input,
225 .direction_output = mcf_gpio_direction_output,
226 .get = mcf_gpio_get_value,
227 .set = mcf_gpio_set_value_fast,
228 .base = 88,
229 .ngpio = 5,
230 },
231 .pddr = MCFGPIO_PDDR_QSPI,
232 .podr = MCFGPIO_PODR_QSPI,
233 .ppdr = MCFGPIO_PPDSDR_QSPI,
234 .setr = MCFGPIO_PPDSDR_QSPI,
235 .clrr = MCFGPIO_PCLRR_QSPI,
236 },
237 {
238 .gpio_chip = {
239 .label = "TIMER",
240 .request = mcf_gpio_request,
241 .free = mcf_gpio_free,
242 .direction_input = mcf_gpio_direction_input,
243 .direction_output = mcf_gpio_direction_output,
244 .get = mcf_gpio_get_value,
245 .set = mcf_gpio_set_value_fast,
246 .base = 96,
247 .ngpio = 4,
248 },
249 .pddr = MCFGPIO_PDDR_TIMER,
250 .podr = MCFGPIO_PODR_TIMER,
251 .ppdr = MCFGPIO_PPDSDR_TIMER,
252 .setr = MCFGPIO_PPDSDR_TIMER,
253 .clrr = MCFGPIO_PCLRR_TIMER,
254 },
255 {
256 .gpio_chip = {
257 .label = "ETPU",
258 .request = mcf_gpio_request,
259 .free = mcf_gpio_free,
260 .direction_input = mcf_gpio_direction_input,
261 .direction_output = mcf_gpio_direction_output,
262 .get = mcf_gpio_get_value,
263 .set = mcf_gpio_set_value_fast,
264 .base = 104,
265 .ngpio = 3,
266 },
267 .pddr = MCFGPIO_PDDR_ETPU,
268 .podr = MCFGPIO_PODR_ETPU,
269 .ppdr = MCFGPIO_PPDSDR_ETPU,
270 .setr = MCFGPIO_PPDSDR_ETPU,
271 .clrr = MCFGPIO_PCLRR_ETPU,
272 },
273};
274
275static int __init mcf_gpio_init(void)
276{
277 unsigned i = 0;
278 while (i < ARRAY_SIZE(mcf_gpio_chips))
279 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
280 return 0;
281}
282
283core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68knommu/platform/5249/Makefile
index a439d9ab3f27..f56225d1582f 100644
--- a/arch/m68knommu/platform/5249/Makefile
+++ b/arch/m68knommu/platform/5249/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o intc2.o
18 18
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 93d998825925..646f5ba462fc 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -48,11 +48,11 @@ static void __init m5249_uart_init_line(int line, int irq)
48 if (line == 0) { 48 if (line == 0) {
49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
51 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 51 mcf_mapirq2imr(irq, MCFINTC_UART0);
52 } else if (line == 1) { 52 } else if (line == 1) {
53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
55 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 55 mcf_mapirq2imr(irq, MCFINTC_UART1);
56 } 56 }
57} 57}
58 58
@@ -65,38 +65,21 @@ static void __init m5249_uarts_init(void)
65 m5249_uart_init_line(line, m5249_uart_platform[line].irq); 65 m5249_uart_init_line(line, m5249_uart_platform[line].irq);
66} 66}
67 67
68
69/***************************************************************************/ 68/***************************************************************************/
70 69
71void mcf_autovector(unsigned int vec) 70static void __init m5249_timers_init(void)
72{ 71{
73 volatile unsigned char *mbar; 72 /* Timer1 is always used as system timer */
74 73 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 if ((vec >= 25) && (vec <= 31)) { 74 MCF_MBAR + MCFSIM_TIMER1ICR);
76 mbar = (volatile unsigned char *) MCF_MBAR; 75 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77 vec = 0x1 << (vec - 24); 76
78 *(mbar + MCFSIM_AVR) |= vec; 77#ifdef CONFIG_HIGHPROFILE
79 mcf_setimr(mcf_getimr() & ~vec); 78 /* Timer2 is to be used as a high speed profile timer */
80 } 79 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81} 80 MCF_MBAR + MCFSIM_TIMER2ICR);
82 81 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83/***************************************************************************/ 82#endif
84
85void mcf_settimericr(unsigned int timer, unsigned int level)
86{
87 volatile unsigned char *icrp;
88 unsigned int icr, imr;
89
90 if (timer <= 2) {
91 switch (timer) {
92 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
93 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
94 }
95
96 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
97 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
98 mcf_setimr(mcf_getimr() & ~imr);
99 }
100} 83}
101 84
102/***************************************************************************/ 85/***************************************************************************/
@@ -114,15 +97,15 @@ void m5249_cpu_reset(void)
114 97
115void __init config_BSP(char *commandp, int size) 98void __init config_BSP(char *commandp, int size)
116{ 99{
117 mcf_setimr(MCFSIM_IMR_MASKALL);
118 mach_reset = m5249_cpu_reset; 100 mach_reset = m5249_cpu_reset;
101 m5249_timers_init();
102 m5249_uarts_init();
119} 103}
120 104
121/***************************************************************************/ 105/***************************************************************************/
122 106
123static int __init init_BSP(void) 107static int __init init_BSP(void)
124{ 108{
125 m5249_uarts_init();
126 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); 109 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
127 return 0; 110 return 0;
128} 111}
diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c
new file mode 100644
index 000000000000..c611eab8b3b6
--- /dev/null
+++ b/arch/m68knommu/platform/5249/gpio.c
@@ -0,0 +1,65 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "GPIO0",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 32,
34 },
35 .pddr = MCFSIM2_GPIOENABLE,
36 .podr = MCFSIM2_GPIOWRITE,
37 .ppdr = MCFSIM2_GPIOREAD,
38 },
39 {
40 .gpio_chip = {
41 .label = "GPIO1",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 32,
49 .ngpio = 32,
50 },
51 .pddr = MCFSIM2_GPIO1ENABLE,
52 .podr = MCFSIM2_GPIO1WRITE,
53 .ppdr = MCFSIM2_GPIO1READ,
54 },
55};
56
57static int __init mcf_gpio_init(void)
58{
59 unsigned i = 0;
60 while (i < ARRAY_SIZE(mcf_gpio_chips))
61 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
62 return 0;
63}
64
65core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68knommu/platform/5249/intc2.c
new file mode 100644
index 000000000000..d09d9da04537
--- /dev/null
+++ b/arch/m68knommu/platform/5249/intc2.c
@@ -0,0 +1,59 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 5249
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19
20static void intc2_irq_gpio_mask(unsigned int irq)
21{
22 u32 imr;
23 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (irq - MCFINTC2_GPIOIRQ0));
25 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
26}
27
28static void intc2_irq_gpio_unmask(unsigned int irq)
29{
30 u32 imr;
31 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (irq - MCFINTC2_GPIOIRQ0));
33 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
34}
35
36static void intc2_irq_gpio_ack(unsigned int irq)
37{
38 writel(0x1 << (irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
39}
40
41static struct irq_chip intc2_irq_gpio_chip = {
42 .name = "CF-INTC2",
43 .mask = intc2_irq_gpio_mask,
44 .unmask = intc2_irq_gpio_unmask,
45 .ack = intc2_irq_gpio_ack,
46};
47
48static int __init mcf_intc2_init(void)
49{
50 int irq;
51
52 /* GPIO interrupt sources */
53 for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++)
54 irq_desc[irq].chip = &intc2_irq_gpio_chip;
55
56 return 0;
57}
58
59arch_initcall(mcf_intc2_init);
diff --git a/arch/m68knommu/platform/5272/Makefile b/arch/m68knommu/platform/5272/Makefile
index 26135d92b34d..93673ef8e2c1 100644
--- a/arch/m68knommu/platform/5272/Makefile
+++ b/arch/m68knommu/platform/5272/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o intc.o
18 18
diff --git a/arch/m68knommu/platform/5272/config.c b/arch/m68knommu/platform/5272/config.c
index 5f95fcde05fd..59278c0887d0 100644
--- a/arch/m68knommu/platform/5272/config.c
+++ b/arch/m68knommu/platform/5272/config.c
@@ -20,12 +20,6 @@
20 20
21/***************************************************************************/ 21/***************************************************************************/
22 22
23extern unsigned int mcf_timervector;
24extern unsigned int mcf_profilevector;
25extern unsigned int mcf_timerlevel;
26
27/***************************************************************************/
28
29/* 23/*
30 * Some platforms need software versions of the GPIO data registers. 24 * Some platforms need software versions of the GPIO data registers.
31 */ 25 */
@@ -37,11 +31,11 @@ unsigned char ledbank = 0xff;
37static struct mcf_platform_uart m5272_uart_platform[] = { 31static struct mcf_platform_uart m5272_uart_platform[] = {
38 { 32 {
39 .mapbase = MCF_MBAR + MCFUART_BASE1, 33 .mapbase = MCF_MBAR + MCFUART_BASE1,
40 .irq = 73, 34 .irq = MCF_IRQ_UART1,
41 }, 35 },
42 { 36 {
43 .mapbase = MCF_MBAR + MCFUART_BASE2, 37 .mapbase = MCF_MBAR + MCFUART_BASE2,
44 .irq = 74, 38 .irq = MCF_IRQ_UART2,
45 }, 39 },
46 { }, 40 { },
47}; 41};
@@ -59,18 +53,18 @@ static struct resource m5272_fec_resources[] = {
59 .flags = IORESOURCE_MEM, 53 .flags = IORESOURCE_MEM,
60 }, 54 },
61 { 55 {
62 .start = 86, 56 .start = MCF_IRQ_ERX,
63 .end = 86, 57 .end = MCF_IRQ_ERX,
64 .flags = IORESOURCE_IRQ, 58 .flags = IORESOURCE_IRQ,
65 }, 59 },
66 { 60 {
67 .start = 87, 61 .start = MCF_IRQ_ETX,
68 .end = 87, 62 .end = MCF_IRQ_ETX,
69 .flags = IORESOURCE_IRQ, 63 .flags = IORESOURCE_IRQ,
70 }, 64 },
71 { 65 {
72 .start = 88, 66 .start = MCF_IRQ_ENTC,
73 .end = 88, 67 .end = MCF_IRQ_ENTC,
74 .flags = IORESOURCE_IRQ, 68 .flags = IORESOURCE_IRQ,
75 }, 69 },
76}; 70};
@@ -94,9 +88,6 @@ static void __init m5272_uart_init_line(int line, int irq)
94 u32 v; 88 u32 v;
95 89
96 if ((line >= 0) && (line < 2)) { 90 if ((line >= 0) && (line < 2)) {
97 v = (line) ? 0x0e000000 : 0xe0000000;
98 writel(v, MCF_MBAR + MCFSIM_ICR2);
99
100 /* Enable the output lines for the serial ports */ 91 /* Enable the output lines for the serial ports */
101 v = readl(MCF_MBAR + MCFSIM_PBCNT); 92 v = readl(MCF_MBAR + MCFSIM_PBCNT);
102 v = (v & ~0x000000ff) | 0x00000055; 93 v = (v & ~0x000000ff) | 0x00000055;
@@ -119,54 +110,6 @@ static void __init m5272_uarts_init(void)
119 110
120/***************************************************************************/ 111/***************************************************************************/
121 112
122static void __init m5272_fec_init(void)
123{
124 u32 imr;
125
126 /* Unmask FEC interrupts at ColdFire interrupt controller */
127 imr = readl(MCF_MBAR + MCFSIM_ICR3);
128 imr = (imr & ~0x00000fff) | 0x00000ddd;
129 writel(imr, MCF_MBAR + MCFSIM_ICR3);
130
131 imr = readl(MCF_MBAR + MCFSIM_ICR1);
132 imr = (imr & ~0x0f000000) | 0x0d000000;
133 writel(imr, MCF_MBAR + MCFSIM_ICR1);
134}
135
136/***************************************************************************/
137
138void mcf_disableall(void)
139{
140 volatile unsigned long *icrp;
141
142 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
143 icrp[0] = 0x88888888;
144 icrp[1] = 0x88888888;
145 icrp[2] = 0x88888888;
146 icrp[3] = 0x88888888;
147}
148
149/***************************************************************************/
150
151void mcf_autovector(unsigned int vec)
152{
153 /* Everything is auto-vectored on the 5272 */
154}
155
156/***************************************************************************/
157
158void mcf_settimericr(int timer, int level)
159{
160 volatile unsigned long *icrp;
161
162 if ((timer >= 1 ) && (timer <= 4)) {
163 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
164 *icrp = (0x8 | level) << ((4 - timer) * 4);
165 }
166}
167
168/***************************************************************************/
169
170static void m5272_cpu_reset(void) 113static void m5272_cpu_reset(void)
171{ 114{
172 local_irq_disable(); 115 local_irq_disable();
@@ -190,8 +133,6 @@ void __init config_BSP(char *commandp, int size)
190 *pivrp = 0x40; 133 *pivrp = 0x40;
191#endif 134#endif
192 135
193 mcf_disableall();
194
195#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES) 136#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
196 /* Copy command line from FLASH to local buffer... */ 137 /* Copy command line from FLASH to local buffer... */
197 memcpy(commandp, (char *) 0xf0004000, size); 138 memcpy(commandp, (char *) 0xf0004000, size);
@@ -202,8 +143,6 @@ void __init config_BSP(char *commandp, int size)
202 commandp[size-1] = 0; 143 commandp[size-1] = 0;
203#endif 144#endif
204 145
205 mcf_timervector = 69;
206 mcf_profilevector = 70;
207 mach_reset = m5272_cpu_reset; 146 mach_reset = m5272_cpu_reset;
208} 147}
209 148
@@ -212,7 +151,6 @@ void __init config_BSP(char *commandp, int size)
212static int __init init_BSP(void) 151static int __init init_BSP(void)
213{ 152{
214 m5272_uarts_init(); 153 m5272_uarts_init();
215 m5272_fec_init();
216 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices)); 154 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
217 return 0; 155 return 0;
218} 156}
diff --git a/arch/m68knommu/platform/5272/gpio.c b/arch/m68knommu/platform/5272/gpio.c
new file mode 100644
index 000000000000..459db89a89cc
--- /dev/null
+++ b/arch/m68knommu/platform/5272/gpio.c
@@ -0,0 +1,81 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PA",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39 {
40 .gpio_chip = {
41 .label = "PB",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 16,
49 .ngpio = 16,
50 },
51 .pddr = MCFSIM_PBDDR,
52 .podr = MCFSIM_PBDAT,
53 .ppdr = MCFSIM_PBDAT,
54 },
55 {
56 .gpio_chip = {
57 .label = "PC",
58 .request = mcf_gpio_request,
59 .free = mcf_gpio_free,
60 .direction_input = mcf_gpio_direction_input,
61 .direction_output = mcf_gpio_direction_output,
62 .get = mcf_gpio_get_value,
63 .set = mcf_gpio_set_value,
64 .base = 32,
65 .ngpio = 16,
66 },
67 .pddr = MCFSIM_PCDDR,
68 .podr = MCFSIM_PCDAT,
69 .ppdr = MCFSIM_PCDAT,
70 },
71};
72
73static int __init mcf_gpio_init(void)
74{
75 unsigned i = 0;
76 while (i < ARRAY_SIZE(mcf_gpio_chips))
77 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
78 return 0;
79}
80
81core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c
new file mode 100644
index 000000000000..7081e0a9720e
--- /dev/null
+++ b/arch/m68knommu/platform/5272/intc.c
@@ -0,0 +1,138 @@
1/*
2 * intc.c -- interrupt controller or ColdFire 5272 SoC
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/traps.h>
20
21/*
22 * The 5272 ColdFire interrupt controller is nothing like any other
23 * ColdFire interrupt controller - it truly is completely different.
24 * Given its age it is unlikely to be used on any other ColdFire CPU.
25 */
26
27/*
28 * The masking and priproty setting of interrupts on the 5272 is done
29 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
30 * loose mapping of vector number to register and internal bits, but
31 * a table is the easiest and quickest way to map them.
32 */
33struct irqmap {
34 unsigned char icr;
35 unsigned char index;
36 unsigned char ack;
37};
38
39static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
40 /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
41 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
42 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
43 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
44 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
45 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
46 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
47 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
48 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
49 /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
50 /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
51 /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
52 /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
53 /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
54 /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, },
55 /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, },
56 /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, },
57 /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
58 /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
59 /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
60 /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
61 /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
62 /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
63 /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
64 /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
65 /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
66 /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
67 /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
68 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
69};
70
71static void intc_irq_mask(unsigned int irq)
72{
73 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
74 u32 v;
75 irq -= MCFINT_VECBASE;
76 v = 0x8 << intc_irqmap[irq].index;
77 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
78 }
79}
80
81static void intc_irq_unmask(unsigned int irq)
82{
83 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
84 u32 v;
85 irq -= MCFINT_VECBASE;
86 v = 0xd << intc_irqmap[irq].index;
87 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
88 }
89}
90
91static void intc_irq_ack(unsigned int irq)
92{
93 /* Only external interrupts are acked */
94 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
95 irq -= MCFINT_VECBASE;
96 if (intc_irqmap[irq].ack) {
97 u32 v;
98 v = 0xd << intc_irqmap[irq].index;
99 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
100 }
101 }
102}
103
104static int intc_irq_set_type(unsigned int irq, unsigned int type)
105{
106 /* We can set the edge type here for external interrupts */
107 return 0;
108}
109
110static struct irq_chip intc_irq_chip = {
111 .name = "CF-INTC",
112 .mask = intc_irq_mask,
113 .unmask = intc_irq_unmask,
114 .ack = intc_irq_ack,
115 .set_type = intc_irq_set_type,
116};
117
118void __init init_IRQ(void)
119{
120 int irq;
121
122 init_vectors();
123
124 /* Mask all interrupt sources */
125 writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
126 writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
127 writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
128 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
129
130 for (irq = 0; (irq < NR_IRQS); irq++) {
131 irq_desc[irq].status = IRQ_DISABLED;
132 irq_desc[irq].action = NULL;
133 irq_desc[irq].depth = 1;
134 irq_desc[irq].chip = &intc_irq_chip;
135 intc_irq_set_type(irq, 0);
136 }
137}
138
diff --git a/arch/m68knommu/platform/527x/Makefile b/arch/m68knommu/platform/527x/Makefile
index 26135d92b34d..3d90e6d92459 100644
--- a/arch/m68knommu/platform/527x/Makefile
+++ b/arch/m68knommu/platform/527x/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c
index f746439cfd3e..fa51be172830 100644
--- a/arch/m68knommu/platform/527x/config.c
+++ b/arch/m68knommu/platform/527x/config.c
@@ -116,23 +116,13 @@ static struct platform_device *m527x_devices[] __initdata = {
116 116
117/***************************************************************************/ 117/***************************************************************************/
118 118
119#define INTC0 (MCF_MBAR + MCFICM_INTC0)
120
121static void __init m527x_uart_init_line(int line, int irq) 119static void __init m527x_uart_init_line(int line, int irq)
122{ 120{
123 u16 sepmask; 121 u16 sepmask;
124 u32 imr;
125 122
126 if ((line < 0) || (line > 2)) 123 if ((line < 0) || (line > 2))
127 return; 124 return;
128 125
129 /* level 6, line based priority */
130 writeb(0x30+line, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
131
132 imr = readl(INTC0 + MCFINTC_IMRL);
133 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
134 writel(imr, INTC0 + MCFINTC_IMRL);
135
136 /* 126 /*
137 * External Pin Mask Setting & Enable External Pin for Interface 127 * External Pin Mask Setting & Enable External Pin for Interface
138 */ 128 */
@@ -157,32 +147,11 @@ static void __init m527x_uarts_init(void)
157 147
158/***************************************************************************/ 148/***************************************************************************/
159 149
160static void __init m527x_fec_irq_init(int nr)
161{
162 unsigned long base;
163 u32 imr;
164
165 base = MCF_IPSBAR + (nr ? MCFICM_INTC1 : MCFICM_INTC0);
166
167 writeb(0x28, base + MCFINTC_ICR0 + 23);
168 writeb(0x27, base + MCFINTC_ICR0 + 27);
169 writeb(0x26, base + MCFINTC_ICR0 + 29);
170
171 imr = readl(base + MCFINTC_IMRH);
172 imr &= ~0xf;
173 writel(imr, base + MCFINTC_IMRH);
174 imr = readl(base + MCFINTC_IMRL);
175 imr &= ~0xff800001;
176 writel(imr, base + MCFINTC_IMRL);
177}
178
179static void __init m527x_fec_init(void) 150static void __init m527x_fec_init(void)
180{ 151{
181 u16 par; 152 u16 par;
182 u8 v; 153 u8 v;
183 154
184 m527x_fec_irq_init(0);
185
186 /* Set multi-function pins to ethernet mode for fec0 */ 155 /* Set multi-function pins to ethernet mode for fec0 */
187#if defined(CONFIG_M5271) 156#if defined(CONFIG_M5271)
188 v = readb(MCF_IPSBAR + 0x100047); 157 v = readb(MCF_IPSBAR + 0x100047);
@@ -195,8 +164,6 @@ static void __init m527x_fec_init(void)
195#endif 164#endif
196 165
197#ifdef CONFIG_FEC2 166#ifdef CONFIG_FEC2
198 m527x_fec_irq_init(1);
199
200 /* Set multi-function pins to ethernet mode for fec1 */ 167 /* Set multi-function pins to ethernet mode for fec1 */
201 par = readw(MCF_IPSBAR + 0x100082); 168 par = readw(MCF_IPSBAR + 0x100082);
202 writew(par | 0xa0, MCF_IPSBAR + 0x100082); 169 writew(par | 0xa0, MCF_IPSBAR + 0x100082);
@@ -207,21 +174,6 @@ static void __init m527x_fec_init(void)
207 174
208/***************************************************************************/ 175/***************************************************************************/
209 176
210void mcf_disableall(void)
211{
212 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
213 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
214}
215
216/***************************************************************************/
217
218void mcf_autovector(unsigned int vec)
219{
220 /* Everything is auto-vectored on the 5272 */
221}
222
223/***************************************************************************/
224
225static void m527x_cpu_reset(void) 177static void m527x_cpu_reset(void)
226{ 178{
227 local_irq_disable(); 179 local_irq_disable();
@@ -232,7 +184,6 @@ static void m527x_cpu_reset(void)
232 184
233void __init config_BSP(char *commandp, int size) 185void __init config_BSP(char *commandp, int size)
234{ 186{
235 mcf_disableall();
236 mach_reset = m527x_cpu_reset; 187 mach_reset = m527x_cpu_reset;
237 m527x_uarts_init(); 188 m527x_uarts_init();
238 m527x_fec_init(); 189 m527x_fec_init();
diff --git a/arch/m68knommu/platform/527x/gpio.c b/arch/m68knommu/platform/527x/gpio.c
new file mode 100644
index 000000000000..1028142851ac
--- /dev/null
+++ b/arch/m68knommu/platform/527x/gpio.c
@@ -0,0 +1,607 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24#if defined(CONFIG_M5271)
25 {
26 .gpio_chip = {
27 .label = "PIRQ",
28 .request = mcf_gpio_request,
29 .free = mcf_gpio_free,
30 .direction_input = mcf_gpio_direction_input,
31 .direction_output = mcf_gpio_direction_output,
32 .get = mcf_gpio_get_value,
33 .set = mcf_gpio_set_value,
34 .ngpio = 8,
35 },
36 .pddr = MCFEPORT_EPDDR,
37 .podr = MCFEPORT_EPDR,
38 .ppdr = MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "ADDR",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 13,
50 .ngpio = 3,
51 },
52 .pddr = MCFGPIO_PDDR_ADDR,
53 .podr = MCFGPIO_PODR_ADDR,
54 .ppdr = MCFGPIO_PPDSDR_ADDR,
55 .setr = MCFGPIO_PPDSDR_ADDR,
56 .clrr = MCFGPIO_PCLRR_ADDR,
57 },
58 {
59 .gpio_chip = {
60 .label = "DATAH",
61 .request = mcf_gpio_request,
62 .free = mcf_gpio_free,
63 .direction_input = mcf_gpio_direction_input,
64 .direction_output = mcf_gpio_direction_output,
65 .get = mcf_gpio_get_value,
66 .set = mcf_gpio_set_value_fast,
67 .base = 16,
68 .ngpio = 8,
69 },
70 .pddr = MCFGPIO_PDDR_DATAH,
71 .podr = MCFGPIO_PODR_DATAH,
72 .ppdr = MCFGPIO_PPDSDR_DATAH,
73 .setr = MCFGPIO_PPDSDR_DATAH,
74 .clrr = MCFGPIO_PCLRR_DATAH,
75 },
76 {
77 .gpio_chip = {
78 .label = "DATAL",
79 .request = mcf_gpio_request,
80 .free = mcf_gpio_free,
81 .direction_input = mcf_gpio_direction_input,
82 .direction_output = mcf_gpio_direction_output,
83 .get = mcf_gpio_get_value,
84 .set = mcf_gpio_set_value_fast,
85 .base = 24,
86 .ngpio = 8,
87 },
88 .pddr = MCFGPIO_PDDR_DATAL,
89 .podr = MCFGPIO_PODR_DATAL,
90 .ppdr = MCFGPIO_PPDSDR_DATAL,
91 .setr = MCFGPIO_PPDSDR_DATAL,
92 .clrr = MCFGPIO_PCLRR_DATAL,
93 },
94 {
95 .gpio_chip = {
96 .label = "BUSCTL",
97 .request = mcf_gpio_request,
98 .free = mcf_gpio_free,
99 .direction_input = mcf_gpio_direction_input,
100 .direction_output = mcf_gpio_direction_output,
101 .get = mcf_gpio_get_value,
102 .set = mcf_gpio_set_value_fast,
103 .base = 32,
104 .ngpio = 8,
105 },
106 .pddr = MCFGPIO_PDDR_BUSCTL,
107 .podr = MCFGPIO_PODR_BUSCTL,
108 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
109 .setr = MCFGPIO_PPDSDR_BUSCTL,
110 .clrr = MCFGPIO_PCLRR_BUSCTL,
111 },
112 {
113 .gpio_chip = {
114 .label = "BS",
115 .request = mcf_gpio_request,
116 .free = mcf_gpio_free,
117 .direction_input = mcf_gpio_direction_input,
118 .direction_output = mcf_gpio_direction_output,
119 .get = mcf_gpio_get_value,
120 .set = mcf_gpio_set_value_fast,
121 .base = 40,
122 .ngpio = 4,
123 },
124 .pddr = MCFGPIO_PDDR_BS,
125 .podr = MCFGPIO_PODR_BS,
126 .ppdr = MCFGPIO_PPDSDR_BS,
127 .setr = MCFGPIO_PPDSDR_BS,
128 .clrr = MCFGPIO_PCLRR_BS,
129 },
130 {
131 .gpio_chip = {
132 .label = "CS",
133 .request = mcf_gpio_request,
134 .free = mcf_gpio_free,
135 .direction_input = mcf_gpio_direction_input,
136 .direction_output = mcf_gpio_direction_output,
137 .get = mcf_gpio_get_value,
138 .set = mcf_gpio_set_value_fast,
139 .base = 49,
140 .ngpio = 7,
141 },
142 .pddr = MCFGPIO_PDDR_CS,
143 .podr = MCFGPIO_PODR_CS,
144 .ppdr = MCFGPIO_PPDSDR_CS,
145 .setr = MCFGPIO_PPDSDR_CS,
146 .clrr = MCFGPIO_PCLRR_CS,
147 },
148 {
149 .gpio_chip = {
150 .label = "SDRAM",
151 .request = mcf_gpio_request,
152 .free = mcf_gpio_free,
153 .direction_input = mcf_gpio_direction_input,
154 .direction_output = mcf_gpio_direction_output,
155 .get = mcf_gpio_get_value,
156 .set = mcf_gpio_set_value_fast,
157 .base = 56,
158 .ngpio = 6,
159 },
160 .pddr = MCFGPIO_PDDR_SDRAM,
161 .podr = MCFGPIO_PODR_SDRAM,
162 .ppdr = MCFGPIO_PPDSDR_SDRAM,
163 .setr = MCFGPIO_PPDSDR_SDRAM,
164 .clrr = MCFGPIO_PCLRR_SDRAM,
165 },
166 {
167 .gpio_chip = {
168 .label = "FECI2C",
169 .request = mcf_gpio_request,
170 .free = mcf_gpio_free,
171 .direction_input = mcf_gpio_direction_input,
172 .direction_output = mcf_gpio_direction_output,
173 .get = mcf_gpio_get_value,
174 .set = mcf_gpio_set_value_fast,
175 .base = 64,
176 .ngpio = 4,
177 },
178 .pddr = MCFGPIO_PDDR_FECI2C,
179 .podr = MCFGPIO_PODR_FECI2C,
180 .ppdr = MCFGPIO_PPDSDR_FECI2C,
181 .setr = MCFGPIO_PPDSDR_FECI2C,
182 .clrr = MCFGPIO_PCLRR_FECI2C,
183 },
184 {
185 .gpio_chip = {
186 .label = "UARTH",
187 .request = mcf_gpio_request,
188 .free = mcf_gpio_free,
189 .direction_input = mcf_gpio_direction_input,
190 .direction_output = mcf_gpio_direction_output,
191 .get = mcf_gpio_get_value,
192 .set = mcf_gpio_set_value_fast,
193 .base = 72,
194 .ngpio = 2,
195 },
196 .pddr = MCFGPIO_PDDR_UARTH,
197 .podr = MCFGPIO_PODR_UARTH,
198 .ppdr = MCFGPIO_PPDSDR_UARTH,
199 .setr = MCFGPIO_PPDSDR_UARTH,
200 .clrr = MCFGPIO_PCLRR_UARTH,
201 },
202 {
203 .gpio_chip = {
204 .label = "UARTL",
205 .request = mcf_gpio_request,
206 .free = mcf_gpio_free,
207 .direction_input = mcf_gpio_direction_input,
208 .direction_output = mcf_gpio_direction_output,
209 .get = mcf_gpio_get_value,
210 .set = mcf_gpio_set_value_fast,
211 .base = 80,
212 .ngpio = 8,
213 },
214 .pddr = MCFGPIO_PDDR_UARTL,
215 .podr = MCFGPIO_PODR_UARTL,
216 .ppdr = MCFGPIO_PPDSDR_UARTL,
217 .setr = MCFGPIO_PPDSDR_UARTL,
218 .clrr = MCFGPIO_PCLRR_UARTL,
219 },
220 {
221 .gpio_chip = {
222 .label = "QSPI",
223 .request = mcf_gpio_request,
224 .free = mcf_gpio_free,
225 .direction_input = mcf_gpio_direction_input,
226 .direction_output = mcf_gpio_direction_output,
227 .get = mcf_gpio_get_value,
228 .set = mcf_gpio_set_value_fast,
229 .base = 88,
230 .ngpio = 5,
231 },
232 .pddr = MCFGPIO_PDDR_QSPI,
233 .podr = MCFGPIO_PODR_QSPI,
234 .ppdr = MCFGPIO_PPDSDR_QSPI,
235 .setr = MCFGPIO_PPDSDR_QSPI,
236 .clrr = MCFGPIO_PCLRR_QSPI,
237 },
238 {
239 .gpio_chip = {
240 .label = "TIMER",
241 .request = mcf_gpio_request,
242 .free = mcf_gpio_free,
243 .direction_input = mcf_gpio_direction_input,
244 .direction_output = mcf_gpio_direction_output,
245 .get = mcf_gpio_get_value,
246 .set = mcf_gpio_set_value_fast,
247 .base = 96,
248 .ngpio = 8,
249 },
250 .pddr = MCFGPIO_PDDR_TIMER,
251 .podr = MCFGPIO_PODR_TIMER,
252 .ppdr = MCFGPIO_PPDSDR_TIMER,
253 .setr = MCFGPIO_PPDSDR_TIMER,
254 .clrr = MCFGPIO_PCLRR_TIMER,
255 },
256#elif defined(CONFIG_M5275)
257 {
258 .gpio_chip = {
259 .label = "PIRQ",
260 .request = mcf_gpio_request,
261 .free = mcf_gpio_free,
262 .direction_input = mcf_gpio_direction_input,
263 .direction_output = mcf_gpio_direction_output,
264 .get = mcf_gpio_get_value,
265 .set = mcf_gpio_set_value,
266 .ngpio = 8,
267 },
268 .pddr = MCFEPORT_EPDDR,
269 .podr = MCFEPORT_EPDR,
270 .ppdr = MCFEPORT_EPPDR,
271 },
272 {
273 .gpio_chip = {
274 .label = "BUSCTL",
275 .request = mcf_gpio_request,
276 .free = mcf_gpio_free,
277 .direction_input = mcf_gpio_direction_input,
278 .direction_output = mcf_gpio_direction_output,
279 .get = mcf_gpio_get_value,
280 .set = mcf_gpio_set_value_fast,
281 .base = 8,
282 .ngpio = 8,
283 },
284 .pddr = MCFGPIO_PDDR_BUSCTL,
285 .podr = MCFGPIO_PODR_BUSCTL,
286 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
287 .setr = MCFGPIO_PPDSDR_BUSCTL,
288 .clrr = MCFGPIO_PCLRR_BUSCTL,
289 },
290 {
291 .gpio_chip = {
292 .label = "ADDR",
293 .request = mcf_gpio_request,
294 .free = mcf_gpio_free,
295 .direction_input = mcf_gpio_direction_input,
296 .direction_output = mcf_gpio_direction_output,
297 .get = mcf_gpio_get_value,
298 .set = mcf_gpio_set_value_fast,
299 .base = 21,
300 .ngpio = 3,
301 },
302 .pddr = MCFGPIO_PDDR_ADDR,
303 .podr = MCFGPIO_PODR_ADDR,
304 .ppdr = MCFGPIO_PPDSDR_ADDR,
305 .setr = MCFGPIO_PPDSDR_ADDR,
306 .clrr = MCFGPIO_PCLRR_ADDR,
307 },
308 {
309 .gpio_chip = {
310 .label = "CS",
311 .request = mcf_gpio_request,
312 .free = mcf_gpio_free,
313 .direction_input = mcf_gpio_direction_input,
314 .direction_output = mcf_gpio_direction_output,
315 .get = mcf_gpio_get_value,
316 .set = mcf_gpio_set_value_fast,
317 .base = 25,
318 .ngpio = 7,
319 },
320 .pddr = MCFGPIO_PDDR_CS,
321 .podr = MCFGPIO_PODR_CS,
322 .ppdr = MCFGPIO_PPDSDR_CS,
323 .setr = MCFGPIO_PPDSDR_CS,
324 .clrr = MCFGPIO_PCLRR_CS,
325 },
326 {
327 .gpio_chip = {
328 .label = "FEC0H",
329 .request = mcf_gpio_request,
330 .free = mcf_gpio_free,
331 .direction_input = mcf_gpio_direction_input,
332 .direction_output = mcf_gpio_direction_output,
333 .get = mcf_gpio_get_value,
334 .set = mcf_gpio_set_value_fast,
335 .base = 32,
336 .ngpio = 8,
337 },
338 .pddr = MCFGPIO_PDDR_FEC0H,
339 .podr = MCFGPIO_PODR_FEC0H,
340 .ppdr = MCFGPIO_PPDSDR_FEC0H,
341 .setr = MCFGPIO_PPDSDR_FEC0H,
342 .clrr = MCFGPIO_PCLRR_FEC0H,
343 },
344 {
345 .gpio_chip = {
346 .label = "FEC0L",
347 .request = mcf_gpio_request,
348 .free = mcf_gpio_free,
349 .direction_input = mcf_gpio_direction_input,
350 .direction_output = mcf_gpio_direction_output,
351 .get = mcf_gpio_get_value,
352 .set = mcf_gpio_set_value_fast,
353 .base = 40,
354 .ngpio = 8,
355 },
356 .pddr = MCFGPIO_PDDR_FEC0L,
357 .podr = MCFGPIO_PODR_FEC0L,
358 .ppdr = MCFGPIO_PPDSDR_FEC0L,
359 .setr = MCFGPIO_PPDSDR_FEC0L,
360 .clrr = MCFGPIO_PCLRR_FEC0L,
361 },
362 {
363 .gpio_chip = {
364 .label = "FECI2C",
365 .request = mcf_gpio_request,
366 .free = mcf_gpio_free,
367 .direction_input = mcf_gpio_direction_input,
368 .direction_output = mcf_gpio_direction_output,
369 .get = mcf_gpio_get_value,
370 .set = mcf_gpio_set_value_fast,
371 .base = 48,
372 .ngpio = 6,
373 },
374 .pddr = MCFGPIO_PDDR_FECI2C,
375 .podr = MCFGPIO_PODR_FECI2C,
376 .ppdr = MCFGPIO_PPDSDR_FECI2C,
377 .setr = MCFGPIO_PPDSDR_FECI2C,
378 .clrr = MCFGPIO_PCLRR_FECI2C,
379 },
380 {
381 .gpio_chip = {
382 .label = "QSPI",
383 .request = mcf_gpio_request,
384 .free = mcf_gpio_free,
385 .direction_input = mcf_gpio_direction_input,
386 .direction_output = mcf_gpio_direction_output,
387 .get = mcf_gpio_get_value,
388 .set = mcf_gpio_set_value_fast,
389 .base = 56,
390 .ngpio = 7,
391 },
392 .pddr = MCFGPIO_PDDR_QSPI,
393 .podr = MCFGPIO_PODR_QSPI,
394 .ppdr = MCFGPIO_PPDSDR_QSPI,
395 .setr = MCFGPIO_PPDSDR_QSPI,
396 .clrr = MCFGPIO_PCLRR_QSPI,
397 },
398 {
399 .gpio_chip = {
400 .label = "SDRAM",
401 .request = mcf_gpio_request,
402 .free = mcf_gpio_free,
403 .direction_input = mcf_gpio_direction_input,
404 .direction_output = mcf_gpio_direction_output,
405 .get = mcf_gpio_get_value,
406 .set = mcf_gpio_set_value_fast,
407 .base = 64,
408 .ngpio = 8,
409 },
410 .pddr = MCFGPIO_PDDR_SDRAM,
411 .podr = MCFGPIO_PODR_SDRAM,
412 .ppdr = MCFGPIO_PPDSDR_SDRAM,
413 .setr = MCFGPIO_PPDSDR_SDRAM,
414 .clrr = MCFGPIO_PCLRR_SDRAM,
415 },
416 {
417 .gpio_chip = {
418 .label = "TIMERH",
419 .request = mcf_gpio_request,
420 .free = mcf_gpio_free,
421 .direction_input = mcf_gpio_direction_input,
422 .direction_output = mcf_gpio_direction_output,
423 .get = mcf_gpio_get_value,
424 .set = mcf_gpio_set_value_fast,
425 .base = 72,
426 .ngpio = 4,
427 },
428 .pddr = MCFGPIO_PDDR_TIMERH,
429 .podr = MCFGPIO_PODR_TIMERH,
430 .ppdr = MCFGPIO_PPDSDR_TIMERH,
431 .setr = MCFGPIO_PPDSDR_TIMERH,
432 .clrr = MCFGPIO_PCLRR_TIMERH,
433 },
434 {
435 .gpio_chip = {
436 .label = "TIMERL",
437 .request = mcf_gpio_request,
438 .free = mcf_gpio_free,
439 .direction_input = mcf_gpio_direction_input,
440 .direction_output = mcf_gpio_direction_output,
441 .get = mcf_gpio_get_value,
442 .set = mcf_gpio_set_value_fast,
443 .base = 80,
444 .ngpio = 4,
445 },
446 .pddr = MCFGPIO_PDDR_TIMERL,
447 .podr = MCFGPIO_PODR_TIMERL,
448 .ppdr = MCFGPIO_PPDSDR_TIMERL,
449 .setr = MCFGPIO_PPDSDR_TIMERL,
450 .clrr = MCFGPIO_PCLRR_TIMERL,
451 },
452 {
453 .gpio_chip = {
454 .label = "UARTL",
455 .request = mcf_gpio_request,
456 .free = mcf_gpio_free,
457 .direction_input = mcf_gpio_direction_input,
458 .direction_output = mcf_gpio_direction_output,
459 .get = mcf_gpio_get_value,
460 .set = mcf_gpio_set_value_fast,
461 .base = 88,
462 .ngpio = 8,
463 },
464 .pddr = MCFGPIO_PDDR_UARTL,
465 .podr = MCFGPIO_PODR_UARTL,
466 .ppdr = MCFGPIO_PPDSDR_UARTL,
467 .setr = MCFGPIO_PPDSDR_UARTL,
468 .clrr = MCFGPIO_PCLRR_UARTL,
469 },
470 {
471 .gpio_chip = {
472 .label = "FEC1H",
473 .request = mcf_gpio_request,
474 .free = mcf_gpio_free,
475 .direction_input = mcf_gpio_direction_input,
476 .direction_output = mcf_gpio_direction_output,
477 .get = mcf_gpio_get_value,
478 .set = mcf_gpio_set_value_fast,
479 .base = 96,
480 .ngpio = 8,
481 },
482 .pddr = MCFGPIO_PDDR_FEC1H,
483 .podr = MCFGPIO_PODR_FEC1H,
484 .ppdr = MCFGPIO_PPDSDR_FEC1H,
485 .setr = MCFGPIO_PPDSDR_FEC1H,
486 .clrr = MCFGPIO_PCLRR_FEC1H,
487 },
488 {
489 .gpio_chip = {
490 .label = "FEC1L",
491 .request = mcf_gpio_request,
492 .free = mcf_gpio_free,
493 .direction_input = mcf_gpio_direction_input,
494 .direction_output = mcf_gpio_direction_output,
495 .get = mcf_gpio_get_value,
496 .set = mcf_gpio_set_value_fast,
497 .base = 104,
498 .ngpio = 8,
499 },
500 .pddr = MCFGPIO_PDDR_FEC1L,
501 .podr = MCFGPIO_PODR_FEC1L,
502 .ppdr = MCFGPIO_PPDSDR_FEC1L,
503 .setr = MCFGPIO_PPDSDR_FEC1L,
504 .clrr = MCFGPIO_PCLRR_FEC1L,
505 },
506 {
507 .gpio_chip = {
508 .label = "BS",
509 .request = mcf_gpio_request,
510 .free = mcf_gpio_free,
511 .direction_input = mcf_gpio_direction_input,
512 .direction_output = mcf_gpio_direction_output,
513 .get = mcf_gpio_get_value,
514 .set = mcf_gpio_set_value_fast,
515 .base = 114,
516 .ngpio = 2,
517 },
518 .pddr = MCFGPIO_PDDR_BS,
519 .podr = MCFGPIO_PODR_BS,
520 .ppdr = MCFGPIO_PPDSDR_BS,
521 .setr = MCFGPIO_PPDSDR_BS,
522 .clrr = MCFGPIO_PCLRR_BS,
523 },
524 {
525 .gpio_chip = {
526 .label = "IRQ",
527 .request = mcf_gpio_request,
528 .free = mcf_gpio_free,
529 .direction_input = mcf_gpio_direction_input,
530 .direction_output = mcf_gpio_direction_output,
531 .get = mcf_gpio_get_value,
532 .set = mcf_gpio_set_value_fast,
533 .base = 121,
534 .ngpio = 7,
535 },
536 .pddr = MCFGPIO_PDDR_IRQ,
537 .podr = MCFGPIO_PODR_IRQ,
538 .ppdr = MCFGPIO_PPDSDR_IRQ,
539 .setr = MCFGPIO_PPDSDR_IRQ,
540 .clrr = MCFGPIO_PCLRR_IRQ,
541 },
542 {
543 .gpio_chip = {
544 .label = "USBH",
545 .request = mcf_gpio_request,
546 .free = mcf_gpio_free,
547 .direction_input = mcf_gpio_direction_input,
548 .direction_output = mcf_gpio_direction_output,
549 .get = mcf_gpio_get_value,
550 .set = mcf_gpio_set_value_fast,
551 .base = 128,
552 .ngpio = 1,
553 },
554 .pddr = MCFGPIO_PDDR_USBH,
555 .podr = MCFGPIO_PODR_USBH,
556 .ppdr = MCFGPIO_PPDSDR_USBH,
557 .setr = MCFGPIO_PPDSDR_USBH,
558 .clrr = MCFGPIO_PCLRR_USBH,
559 },
560 {
561 .gpio_chip = {
562 .label = "USBL",
563 .request = mcf_gpio_request,
564 .free = mcf_gpio_free,
565 .direction_input = mcf_gpio_direction_input,
566 .direction_output = mcf_gpio_direction_output,
567 .get = mcf_gpio_get_value,
568 .set = mcf_gpio_set_value_fast,
569 .base = 136,
570 .ngpio = 8,
571 },
572 .pddr = MCFGPIO_PDDR_USBL,
573 .podr = MCFGPIO_PODR_USBL,
574 .ppdr = MCFGPIO_PPDSDR_USBL,
575 .setr = MCFGPIO_PPDSDR_USBL,
576 .clrr = MCFGPIO_PCLRR_USBL,
577 },
578 {
579 .gpio_chip = {
580 .label = "UARTH",
581 .request = mcf_gpio_request,
582 .free = mcf_gpio_free,
583 .direction_input = mcf_gpio_direction_input,
584 .direction_output = mcf_gpio_direction_output,
585 .get = mcf_gpio_get_value,
586 .set = mcf_gpio_set_value_fast,
587 .base = 144,
588 .ngpio = 4,
589 },
590 .pddr = MCFGPIO_PDDR_UARTH,
591 .podr = MCFGPIO_PODR_UARTH,
592 .ppdr = MCFGPIO_PPDSDR_UARTH,
593 .setr = MCFGPIO_PPDSDR_UARTH,
594 .clrr = MCFGPIO_PCLRR_UARTH,
595 },
596#endif
597};
598
599static int __init mcf_gpio_init(void)
600{
601 unsigned i = 0;
602 while (i < ARRAY_SIZE(mcf_gpio_chips))
603 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
604 return 0;
605}
606
607core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/528x/Makefile b/arch/m68knommu/platform/528x/Makefile
index 26135d92b34d..3d90e6d92459 100644
--- a/arch/m68knommu/platform/528x/Makefile
+++ b/arch/m68knommu/platform/528x/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c
index a1d1a61c4fe6..6e608d1836f1 100644
--- a/arch/m68knommu/platform/528x/config.c
+++ b/arch/m68knommu/platform/528x/config.c
@@ -3,8 +3,8 @@
3/* 3/*
4 * linux/arch/m68knommu/platform/528x/config.c 4 * linux/arch/m68knommu/platform/528x/config.c
5 * 5 *
6 * Sub-architcture dependant initialization code for the Motorola 6 * Sub-architcture dependant initialization code for the Freescale
7 * 5280 and 5282 CPUs. 7 * 5280, 5281 and 5282 CPUs.
8 * 8 *
9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) 9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) 10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
@@ -15,20 +15,13 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/platform_device.h> 18#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/flash.h>
22#include <linux/io.h> 19#include <linux/io.h>
23#include <asm/machdep.h> 20#include <asm/machdep.h>
24#include <asm/coldfire.h> 21#include <asm/coldfire.h>
25#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
26#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
27 24
28#ifdef CONFIG_MTD_PARTITIONS
29#include <linux/mtd/partitions.h>
30#endif
31
32/***************************************************************************/ 25/***************************************************************************/
33 26
34static struct mcf_platform_uart m528x_uart_platform[] = { 27static struct mcf_platform_uart m528x_uart_platform[] = {
@@ -91,23 +84,13 @@ static struct platform_device *m528x_devices[] __initdata = {
91 84
92/***************************************************************************/ 85/***************************************************************************/
93 86
94#define INTC0 (MCF_MBAR + MCFICM_INTC0)
95
96static void __init m528x_uart_init_line(int line, int irq) 87static void __init m528x_uart_init_line(int line, int irq)
97{ 88{
98 u8 port; 89 u8 port;
99 u32 imr;
100 90
101 if ((line < 0) || (line > 2)) 91 if ((line < 0) || (line > 2))
102 return; 92 return;
103 93
104 /* level 6, line based priority */
105 writeb(0x30+line, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
106
107 imr = readl(INTC0 + MCFINTC_IMRL);
108 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
109 writel(imr, INTC0 + MCFINTC_IMRL);
110
111 /* make sure PUAPAR is set for UART0 and UART1 */ 94 /* make sure PUAPAR is set for UART0 and UART1 */
112 if (line < 2) { 95 if (line < 2) {
113 port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR); 96 port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR);
@@ -129,21 +112,8 @@ static void __init m528x_uarts_init(void)
129 112
130static void __init m528x_fec_init(void) 113static void __init m528x_fec_init(void)
131{ 114{
132 u32 imr;
133 u16 v16; 115 u16 v16;
134 116
135 /* Unmask FEC interrupts at ColdFire interrupt controller */
136 writeb(0x28, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 23);
137 writeb(0x27, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 27);
138 writeb(0x26, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 29);
139
140 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
141 imr &= ~0xf;
142 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
143 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
144 imr &= ~0xff800001;
145 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
146
147 /* Set multi-function pins to ethernet mode for fec0 */ 117 /* Set multi-function pins to ethernet mode for fec0 */
148 v16 = readw(MCF_IPSBAR + 0x100056); 118 v16 = readw(MCF_IPSBAR + 0x100056);
149 writew(v16 | 0xf00, MCF_IPSBAR + 0x100056); 119 writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
@@ -152,21 +122,6 @@ static void __init m528x_fec_init(void)
152 122
153/***************************************************************************/ 123/***************************************************************************/
154 124
155void mcf_disableall(void)
156{
157 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
158 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
159}
160
161/***************************************************************************/
162
163void mcf_autovector(unsigned int vec)
164{
165 /* Everything is auto-vectored on the 5272 */
166}
167
168/***************************************************************************/
169
170static void m528x_cpu_reset(void) 125static void m528x_cpu_reset(void)
171{ 126{
172 local_irq_disable(); 127 local_irq_disable();
@@ -204,8 +159,6 @@ void wildfiremod_halt(void)
204 159
205void __init config_BSP(char *commandp, int size) 160void __init config_BSP(char *commandp, int size)
206{ 161{
207 mcf_disableall();
208
209#ifdef CONFIG_WILDFIRE 162#ifdef CONFIG_WILDFIRE
210 mach_halt = wildfire_halt; 163 mach_halt = wildfire_halt;
211#endif 164#endif
diff --git a/arch/m68knommu/platform/528x/gpio.c b/arch/m68knommu/platform/528x/gpio.c
new file mode 100644
index 000000000000..ec593950696a
--- /dev/null
+++ b/arch/m68knommu/platform/528x/gpio.c
@@ -0,0 +1,438 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "NQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .base = 1,
34 .ngpio = 8,
35 },
36 .pddr = MCFEPORT_EPDDR,
37 .podr = MCFEPORT_EPDR,
38 .ppdr = MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "TA",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 8,
50 .ngpio = 4,
51 },
52 .pddr = MCFGPTA_GPTDDR,
53 .podr = MCFGPTA_GPTPORT,
54 .ppdr = MCFGPTB_GPTPORT,
55 },
56 {
57 .gpio_chip = {
58 .label = "TB",
59 .request = mcf_gpio_request,
60 .free = mcf_gpio_free,
61 .direction_input = mcf_gpio_direction_input,
62 .direction_output = mcf_gpio_direction_output,
63 .get = mcf_gpio_get_value,
64 .set = mcf_gpio_set_value_fast,
65 .base = 16,
66 .ngpio = 4,
67 },
68 .pddr = MCFGPTB_GPTDDR,
69 .podr = MCFGPTB_GPTPORT,
70 .ppdr = MCFGPTB_GPTPORT,
71 },
72 {
73 .gpio_chip = {
74 .label = "QA",
75 .request = mcf_gpio_request,
76 .free = mcf_gpio_free,
77 .direction_input = mcf_gpio_direction_input,
78 .direction_output = mcf_gpio_direction_output,
79 .get = mcf_gpio_get_value,
80 .set = mcf_gpio_set_value_fast,
81 .base = 24,
82 .ngpio = 4,
83 },
84 .pddr = MCFQADC_DDRQA,
85 .podr = MCFQADC_PORTQA,
86 .ppdr = MCFQADC_PORTQA,
87 },
88 {
89 .gpio_chip = {
90 .label = "QB",
91 .request = mcf_gpio_request,
92 .free = mcf_gpio_free,
93 .direction_input = mcf_gpio_direction_input,
94 .direction_output = mcf_gpio_direction_output,
95 .get = mcf_gpio_get_value,
96 .set = mcf_gpio_set_value_fast,
97 .base = 32,
98 .ngpio = 4,
99 },
100 .pddr = MCFQADC_DDRQB,
101 .podr = MCFQADC_PORTQB,
102 .ppdr = MCFQADC_PORTQB,
103 },
104 {
105 .gpio_chip = {
106 .label = "A",
107 .request = mcf_gpio_request,
108 .free = mcf_gpio_free,
109 .direction_input = mcf_gpio_direction_input,
110 .direction_output = mcf_gpio_direction_output,
111 .get = mcf_gpio_get_value,
112 .set = mcf_gpio_set_value_fast,
113 .base = 40,
114 .ngpio = 8,
115 },
116 .pddr = MCFGPIO_DDRA,
117 .podr = MCFGPIO_PORTA,
118 .ppdr = MCFGPIO_PORTAP,
119 .setr = MCFGPIO_SETA,
120 .clrr = MCFGPIO_CLRA,
121 },
122 {
123 .gpio_chip = {
124 .label = "B",
125 .request = mcf_gpio_request,
126 .free = mcf_gpio_free,
127 .direction_input = mcf_gpio_direction_input,
128 .direction_output = mcf_gpio_direction_output,
129 .get = mcf_gpio_get_value,
130 .set = mcf_gpio_set_value_fast,
131 .base = 48,
132 .ngpio = 8,
133 },
134 .pddr = MCFGPIO_DDRB,
135 .podr = MCFGPIO_PORTB,
136 .ppdr = MCFGPIO_PORTBP,
137 .setr = MCFGPIO_SETB,
138 .clrr = MCFGPIO_CLRB,
139 },
140 {
141 .gpio_chip = {
142 .label = "C",
143 .request = mcf_gpio_request,
144 .free = mcf_gpio_free,
145 .direction_input = mcf_gpio_direction_input,
146 .direction_output = mcf_gpio_direction_output,
147 .get = mcf_gpio_get_value,
148 .set = mcf_gpio_set_value_fast,
149 .base = 56,
150 .ngpio = 8,
151 },
152 .pddr = MCFGPIO_DDRC,
153 .podr = MCFGPIO_PORTC,
154 .ppdr = MCFGPIO_PORTCP,
155 .setr = MCFGPIO_SETC,
156 .clrr = MCFGPIO_CLRC,
157 },
158 {
159 .gpio_chip = {
160 .label = "D",
161 .request = mcf_gpio_request,
162 .free = mcf_gpio_free,
163 .direction_input = mcf_gpio_direction_input,
164 .direction_output = mcf_gpio_direction_output,
165 .get = mcf_gpio_get_value,
166 .set = mcf_gpio_set_value_fast,
167 .base = 64,
168 .ngpio = 8,
169 },
170 .pddr = MCFGPIO_DDRD,
171 .podr = MCFGPIO_PORTD,
172 .ppdr = MCFGPIO_PORTDP,
173 .setr = MCFGPIO_SETD,
174 .clrr = MCFGPIO_CLRD,
175 },
176 {
177 .gpio_chip = {
178 .label = "E",
179 .request = mcf_gpio_request,
180 .free = mcf_gpio_free,
181 .direction_input = mcf_gpio_direction_input,
182 .direction_output = mcf_gpio_direction_output,
183 .get = mcf_gpio_get_value,
184 .set = mcf_gpio_set_value_fast,
185 .base = 72,
186 .ngpio = 8,
187 },
188 .pddr = MCFGPIO_DDRE,
189 .podr = MCFGPIO_PORTE,
190 .ppdr = MCFGPIO_PORTEP,
191 .setr = MCFGPIO_SETE,
192 .clrr = MCFGPIO_CLRE,
193 },
194 {
195 .gpio_chip = {
196 .label = "F",
197 .request = mcf_gpio_request,
198 .free = mcf_gpio_free,
199 .direction_input = mcf_gpio_direction_input,
200 .direction_output = mcf_gpio_direction_output,
201 .get = mcf_gpio_get_value,
202 .set = mcf_gpio_set_value_fast,
203 .base = 80,
204 .ngpio = 8,
205 },
206 .pddr = MCFGPIO_DDRF,
207 .podr = MCFGPIO_PORTF,
208 .ppdr = MCFGPIO_PORTFP,
209 .setr = MCFGPIO_SETF,
210 .clrr = MCFGPIO_CLRF,
211 },
212 {
213 .gpio_chip = {
214 .label = "G",
215 .request = mcf_gpio_request,
216 .free = mcf_gpio_free,
217 .direction_input = mcf_gpio_direction_input,
218 .direction_output = mcf_gpio_direction_output,
219 .get = mcf_gpio_get_value,
220 .set = mcf_gpio_set_value_fast,
221 .base = 88,
222 .ngpio = 8,
223 },
224 .pddr = MCFGPIO_DDRG,
225 .podr = MCFGPIO_PORTG,
226 .ppdr = MCFGPIO_PORTGP,
227 .setr = MCFGPIO_SETG,
228 .clrr = MCFGPIO_CLRG,
229 },
230 {
231 .gpio_chip = {
232 .label = "H",
233 .request = mcf_gpio_request,
234 .free = mcf_gpio_free,
235 .direction_input = mcf_gpio_direction_input,
236 .direction_output = mcf_gpio_direction_output,
237 .get = mcf_gpio_get_value,
238 .set = mcf_gpio_set_value_fast,
239 .base = 96,
240 .ngpio = 8,
241 },
242 .pddr = MCFGPIO_DDRH,
243 .podr = MCFGPIO_PORTH,
244 .ppdr = MCFGPIO_PORTHP,
245 .setr = MCFGPIO_SETH,
246 .clrr = MCFGPIO_CLRH,
247 },
248 {
249 .gpio_chip = {
250 .label = "J",
251 .request = mcf_gpio_request,
252 .free = mcf_gpio_free,
253 .direction_input = mcf_gpio_direction_input,
254 .direction_output = mcf_gpio_direction_output,
255 .get = mcf_gpio_get_value,
256 .set = mcf_gpio_set_value_fast,
257 .base = 104,
258 .ngpio = 8,
259 },
260 .pddr = MCFGPIO_DDRJ,
261 .podr = MCFGPIO_PORTJ,
262 .ppdr = MCFGPIO_PORTJP,
263 .setr = MCFGPIO_SETJ,
264 .clrr = MCFGPIO_CLRJ,
265 },
266 {
267 .gpio_chip = {
268 .label = "DD",
269 .request = mcf_gpio_request,
270 .free = mcf_gpio_free,
271 .direction_input = mcf_gpio_direction_input,
272 .direction_output = mcf_gpio_direction_output,
273 .get = mcf_gpio_get_value,
274 .set = mcf_gpio_set_value_fast,
275 .base = 112,
276 .ngpio = 8,
277 },
278 .pddr = MCFGPIO_DDRDD,
279 .podr = MCFGPIO_PORTDD,
280 .ppdr = MCFGPIO_PORTDDP,
281 .setr = MCFGPIO_SETDD,
282 .clrr = MCFGPIO_CLRDD,
283 },
284 {
285 .gpio_chip = {
286 .label = "EH",
287 .request = mcf_gpio_request,
288 .free = mcf_gpio_free,
289 .direction_input = mcf_gpio_direction_input,
290 .direction_output = mcf_gpio_direction_output,
291 .get = mcf_gpio_get_value,
292 .set = mcf_gpio_set_value_fast,
293 .base = 120,
294 .ngpio = 8,
295 },
296 .pddr = MCFGPIO_DDREH,
297 .podr = MCFGPIO_PORTEH,
298 .ppdr = MCFGPIO_PORTEHP,
299 .setr = MCFGPIO_SETEH,
300 .clrr = MCFGPIO_CLREH,
301 },
302 {
303 .gpio_chip = {
304 .label = "EL",
305 .request = mcf_gpio_request,
306 .free = mcf_gpio_free,
307 .direction_input = mcf_gpio_direction_input,
308 .direction_output = mcf_gpio_direction_output,
309 .get = mcf_gpio_get_value,
310 .set = mcf_gpio_set_value_fast,
311 .base = 128,
312 .ngpio = 8,
313 },
314 .pddr = MCFGPIO_DDREL,
315 .podr = MCFGPIO_PORTEL,
316 .ppdr = MCFGPIO_PORTELP,
317 .setr = MCFGPIO_SETEL,
318 .clrr = MCFGPIO_CLREL,
319 },
320 {
321 .gpio_chip = {
322 .label = "AS",
323 .request = mcf_gpio_request,
324 .free = mcf_gpio_free,
325 .direction_input = mcf_gpio_direction_input,
326 .direction_output = mcf_gpio_direction_output,
327 .get = mcf_gpio_get_value,
328 .set = mcf_gpio_set_value_fast,
329 .base = 136,
330 .ngpio = 6,
331 },
332 .pddr = MCFGPIO_DDRAS,
333 .podr = MCFGPIO_PORTAS,
334 .ppdr = MCFGPIO_PORTASP,
335 .setr = MCFGPIO_SETAS,
336 .clrr = MCFGPIO_CLRAS,
337 },
338 {
339 .gpio_chip = {
340 .label = "QS",
341 .request = mcf_gpio_request,
342 .free = mcf_gpio_free,
343 .direction_input = mcf_gpio_direction_input,
344 .direction_output = mcf_gpio_direction_output,
345 .get = mcf_gpio_get_value,
346 .set = mcf_gpio_set_value_fast,
347 .base = 144,
348 .ngpio = 7,
349 },
350 .pddr = MCFGPIO_DDRQS,
351 .podr = MCFGPIO_PORTQS,
352 .ppdr = MCFGPIO_PORTQSP,
353 .setr = MCFGPIO_SETQS,
354 .clrr = MCFGPIO_CLRQS,
355 },
356 {
357 .gpio_chip = {
358 .label = "SD",
359 .request = mcf_gpio_request,
360 .free = mcf_gpio_free,
361 .direction_input = mcf_gpio_direction_input,
362 .direction_output = mcf_gpio_direction_output,
363 .get = mcf_gpio_get_value,
364 .set = mcf_gpio_set_value_fast,
365 .base = 152,
366 .ngpio = 6,
367 },
368 .pddr = MCFGPIO_DDRSD,
369 .podr = MCFGPIO_PORTSD,
370 .ppdr = MCFGPIO_PORTSDP,
371 .setr = MCFGPIO_SETSD,
372 .clrr = MCFGPIO_CLRSD,
373 },
374 {
375 .gpio_chip = {
376 .label = "TC",
377 .request = mcf_gpio_request,
378 .free = mcf_gpio_free,
379 .direction_input = mcf_gpio_direction_input,
380 .direction_output = mcf_gpio_direction_output,
381 .get = mcf_gpio_get_value,
382 .set = mcf_gpio_set_value_fast,
383 .base = 160,
384 .ngpio = 4,
385 },
386 .pddr = MCFGPIO_DDRTC,
387 .podr = MCFGPIO_PORTTC,
388 .ppdr = MCFGPIO_PORTTCP,
389 .setr = MCFGPIO_SETTC,
390 .clrr = MCFGPIO_CLRTC,
391 },
392 {
393 .gpio_chip = {
394 .label = "TD",
395 .request = mcf_gpio_request,
396 .free = mcf_gpio_free,
397 .direction_input = mcf_gpio_direction_input,
398 .direction_output = mcf_gpio_direction_output,
399 .get = mcf_gpio_get_value,
400 .set = mcf_gpio_set_value_fast,
401 .base = 168,
402 .ngpio = 4,
403 },
404 .pddr = MCFGPIO_DDRTD,
405 .podr = MCFGPIO_PORTTD,
406 .ppdr = MCFGPIO_PORTTDP,
407 .setr = MCFGPIO_SETTD,
408 .clrr = MCFGPIO_CLRTD,
409 },
410 {
411 .gpio_chip = {
412 .label = "UA",
413 .request = mcf_gpio_request,
414 .free = mcf_gpio_free,
415 .direction_input = mcf_gpio_direction_input,
416 .direction_output = mcf_gpio_direction_output,
417 .get = mcf_gpio_get_value,
418 .set = mcf_gpio_set_value_fast,
419 .base = 176,
420 .ngpio = 4,
421 },
422 .pddr = MCFGPIO_DDRUA,
423 .podr = MCFGPIO_PORTUA,
424 .ppdr = MCFGPIO_PORTUAP,
425 .setr = MCFGPIO_SETUA,
426 .clrr = MCFGPIO_CLRUA,
427 },
428};
429
430static int __init mcf_gpio_init(void)
431{
432 unsigned i = 0;
433 while (i < ARRAY_SIZE(mcf_gpio_chips))
434 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
435 return 0;
436}
437
438core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile
index cfd586860fd8..667db6598451 100644
--- a/arch/m68knommu/platform/5307/Makefile
+++ b/arch/m68knommu/platform/5307/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y += config.o 17obj-y += config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68knommu/platform/5307/config.c
index 39da9e9ff674..00900ac06a9c 100644
--- a/arch/m68knommu/platform/5307/config.c
+++ b/arch/m68knommu/platform/5307/config.c
@@ -21,12 +21,6 @@
21 21
22/***************************************************************************/ 22/***************************************************************************/
23 23
24extern unsigned int mcf_timervector;
25extern unsigned int mcf_profilevector;
26extern unsigned int mcf_timerlevel;
27
28/***************************************************************************/
29
30/* 24/*
31 * Some platforms need software versions of the GPIO data registers. 25 * Some platforms need software versions of the GPIO data registers.
32 */ 26 */
@@ -64,11 +58,11 @@ static void __init m5307_uart_init_line(int line, int irq)
64 if (line == 0) { 58 if (line == 0) {
65 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 59 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
66 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 60 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
67 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 61 mcf_mapirq2imr(irq, MCFINTC_UART0);
68 } else if (line == 1) { 62 } else if (line == 1) {
69 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 63 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
70 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 64 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
71 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 65 mcf_mapirq2imr(irq, MCFINTC_UART1);
72 } 66 }
73} 67}
74 68
@@ -83,35 +77,19 @@ static void __init m5307_uarts_init(void)
83 77
84/***************************************************************************/ 78/***************************************************************************/
85 79
86void mcf_autovector(unsigned int vec) 80static void __init m5307_timers_init(void)
87{
88 volatile unsigned char *mbar;
89
90 if ((vec >= 25) && (vec <= 31)) {
91 mbar = (volatile unsigned char *) MCF_MBAR;
92 vec = 0x1 << (vec - 24);
93 *(mbar + MCFSIM_AVR) |= vec;
94 mcf_setimr(mcf_getimr() & ~vec);
95 }
96}
97
98/***************************************************************************/
99
100void mcf_settimericr(unsigned int timer, unsigned int level)
101{ 81{
102 volatile unsigned char *icrp; 82 /* Timer1 is always used as system timer */
103 unsigned int icr, imr; 83 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
104 84 MCF_MBAR + MCFSIM_TIMER1ICR);
105 if (timer <= 2) { 85 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
106 switch (timer) { 86
107 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 87#ifdef CONFIG_HIGHPROFILE
108 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 88 /* Timer2 is to be used as a high speed profile timer */
109 } 89 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
110 90 MCF_MBAR + MCFSIM_TIMER2ICR);
111 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 91 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
112 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 92#endif
113 mcf_setimr(mcf_getimr() & ~imr);
114 }
115} 93}
116 94
117/***************************************************************************/ 95/***************************************************************************/
@@ -129,20 +107,22 @@ void m5307_cpu_reset(void)
129 107
130void __init config_BSP(char *commandp, int size) 108void __init config_BSP(char *commandp, int size)
131{ 109{
132 mcf_setimr(MCFSIM_IMR_MASKALL);
133
134#if defined(CONFIG_NETtel) || \ 110#if defined(CONFIG_NETtel) || \
135 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) 111 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
136 /* Copy command line from FLASH to local buffer... */ 112 /* Copy command line from FLASH to local buffer... */
137 memcpy(commandp, (char *) 0xf0004000, size); 113 memcpy(commandp, (char *) 0xf0004000, size);
138 commandp[size-1] = 0; 114 commandp[size-1] = 0;
139 /* Different timer setup - to prevent device clash */
140 mcf_timervector = 30;
141 mcf_profilevector = 31;
142 mcf_timerlevel = 6;
143#endif 115#endif
144 116
145 mach_reset = m5307_cpu_reset; 117 mach_reset = m5307_cpu_reset;
118 m5307_timers_init();
119 m5307_uarts_init();
120
121 /* Only support the external interrupts on their primary level */
122 mcf_mapirq2imr(25, MCFINTC_EINT1);
123 mcf_mapirq2imr(27, MCFINTC_EINT3);
124 mcf_mapirq2imr(29, MCFINTC_EINT5);
125 mcf_mapirq2imr(31, MCFINTC_EINT7);
146 126
147#ifdef CONFIG_BDM_DISABLE 127#ifdef CONFIG_BDM_DISABLE
148 /* 128 /*
@@ -158,7 +138,6 @@ void __init config_BSP(char *commandp, int size)
158 138
159static int __init init_BSP(void) 139static int __init init_BSP(void)
160{ 140{
161 m5307_uarts_init();
162 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices)); 141 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
163 return 0; 142 return 0;
164} 143}
diff --git a/arch/m68knommu/platform/5307/gpio.c b/arch/m68knommu/platform/5307/gpio.c
new file mode 100644
index 000000000000..8da5880e4066
--- /dev/null
+++ b/arch/m68knommu/platform/5307/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/532x/Makefile b/arch/m68knommu/platform/532x/Makefile
index e431912f5628..4cc23245bcd1 100644
--- a/arch/m68knommu/platform/532x/Makefile
+++ b/arch/m68knommu/platform/532x/Makefile
@@ -15,4 +15,4 @@
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17#obj-y := config.o usb-mcf532x.o spi-mcf532x.o 17#obj-y := config.o usb-mcf532x.o spi-mcf532x.o
18obj-y := config.o 18obj-y := config.o gpio.o
diff --git a/arch/m68knommu/platform/532x/config.c b/arch/m68knommu/platform/532x/config.c
index cdb761971f7a..d632948e64e5 100644
--- a/arch/m68knommu/platform/532x/config.c
+++ b/arch/m68knommu/platform/532x/config.c
@@ -20,7 +20,6 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/param.h> 21#include <linux/param.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h> 23#include <linux/io.h>
25#include <asm/machdep.h> 24#include <asm/machdep.h>
26#include <asm/coldfire.h> 25#include <asm/coldfire.h>
@@ -31,12 +30,6 @@
31 30
32/***************************************************************************/ 31/***************************************************************************/
33 32
34extern unsigned int mcf_timervector;
35extern unsigned int mcf_profilevector;
36extern unsigned int mcf_timerlevel;
37
38/***************************************************************************/
39
40static struct mcf_platform_uart m532x_uart_platform[] = { 33static struct mcf_platform_uart m532x_uart_platform[] = {
41 { 34 {
42 .mapbase = MCFUART_BASE1, 35 .mapbase = MCFUART_BASE1,
@@ -88,6 +81,7 @@ static struct platform_device m532x_fec = {
88 .num_resources = ARRAY_SIZE(m532x_fec_resources), 81 .num_resources = ARRAY_SIZE(m532x_fec_resources),
89 .resource = m532x_fec_resources, 82 .resource = m532x_fec_resources,
90}; 83};
84
91static struct platform_device *m532x_devices[] __initdata = { 85static struct platform_device *m532x_devices[] __initdata = {
92 &m532x_uart, 86 &m532x_uart,
93 &m532x_fec, 87 &m532x_fec,
@@ -98,18 +92,11 @@ static struct platform_device *m532x_devices[] __initdata = {
98static void __init m532x_uart_init_line(int line, int irq) 92static void __init m532x_uart_init_line(int line, int irq)
99{ 93{
100 if (line == 0) { 94 if (line == 0) {
101 MCF_INTC0_ICR26 = 0x3;
102 MCF_INTC0_CIMR = 26;
103 /* GPIO initialization */ 95 /* GPIO initialization */
104 MCF_GPIO_PAR_UART |= 0x000F; 96 MCF_GPIO_PAR_UART |= 0x000F;
105 } else if (line == 1) { 97 } else if (line == 1) {
106 MCF_INTC0_ICR27 = 0x3;
107 MCF_INTC0_CIMR = 27;
108 /* GPIO initialization */ 98 /* GPIO initialization */
109 MCF_GPIO_PAR_UART |= 0x0FF0; 99 MCF_GPIO_PAR_UART |= 0x0FF0;
110 } else if (line == 2) {
111 MCF_INTC0_ICR28 = 0x3;
112 MCF_INTC0_CIMR = 28;
113 } 100 }
114} 101}
115 102
@@ -125,14 +112,6 @@ static void __init m532x_uarts_init(void)
125 112
126static void __init m532x_fec_init(void) 113static void __init m532x_fec_init(void)
127{ 114{
128 /* Unmask FEC interrupts at ColdFire interrupt controller */
129 MCF_INTC0_ICR36 = 0x2;
130 MCF_INTC0_ICR40 = 0x2;
131 MCF_INTC0_ICR42 = 0x2;
132
133 MCF_INTC0_IMRH &= ~(MCF_INTC_IMRH_INT_MASK36 |
134 MCF_INTC_IMRH_INT_MASK40 | MCF_INTC_IMRH_INT_MASK42);
135
136 /* Set multi-function pins to ethernet mode for fec0 */ 115 /* Set multi-function pins to ethernet mode for fec0 */
137 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | 116 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
138 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); 117 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
@@ -142,26 +121,6 @@ static void __init m532x_fec_init(void)
142 121
143/***************************************************************************/ 122/***************************************************************************/
144 123
145void mcf_settimericr(unsigned int timer, unsigned int level)
146{
147 volatile unsigned char *icrp;
148 unsigned int icr;
149 unsigned char irq;
150
151 if (timer <= 2) {
152 switch (timer) {
153 case 2: irq = 33; icr = MCFSIM_ICR_TIMER2; break;
154 default: irq = 32; icr = MCFSIM_ICR_TIMER1; break;
155 }
156
157 icrp = (volatile unsigned char *) (icr);
158 *icrp = level;
159 mcf_enable_irq0(irq);
160 }
161}
162
163/***************************************************************************/
164
165static void m532x_cpu_reset(void) 124static void m532x_cpu_reset(void)
166{ 125{
167 local_irq_disable(); 126 local_irq_disable();
@@ -172,8 +131,6 @@ static void m532x_cpu_reset(void)
172 131
173void __init config_BSP(char *commandp, int size) 132void __init config_BSP(char *commandp, int size)
174{ 133{
175 mcf_setimr(MCFSIM_IMR_MASKALL);
176
177#if !defined(CONFIG_BOOTPARAM) 134#if !defined(CONFIG_BOOTPARAM)
178 /* Copy command line from FLASH to local buffer... */ 135 /* Copy command line from FLASH to local buffer... */
179 memcpy(commandp, (char *) 0x4000, 4); 136 memcpy(commandp, (char *) 0x4000, 4);
@@ -185,10 +142,6 @@ void __init config_BSP(char *commandp, int size)
185 } 142 }
186#endif 143#endif
187 144
188 mcf_timervector = 64+32;
189 mcf_profilevector = 64+33;
190 mach_reset = m532x_cpu_reset;
191
192#ifdef CONFIG_BDM_DISABLE 145#ifdef CONFIG_BDM_DISABLE
193 /* 146 /*
194 * Disable the BDM clocking. This also turns off most of the rest of 147 * Disable the BDM clocking. This also turns off most of the rest of
@@ -438,8 +391,8 @@ void gpio_init(void)
438 /* Initialize TIN3 as a GPIO output to enable the write 391 /* Initialize TIN3 as a GPIO output to enable the write
439 half of the latch */ 392 half of the latch */
440 MCF_GPIO_PAR_TIMER = 0x00; 393 MCF_GPIO_PAR_TIMER = 0x00;
441 MCF_GPIO_PDDR_TIMER = 0x08; 394 __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
442 MCF_GPIO_PCLRR_TIMER = 0x0; 395 __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
443 396
444} 397}
445 398
diff --git a/arch/m68knommu/platform/532x/gpio.c b/arch/m68knommu/platform/532x/gpio.c
new file mode 100644
index 000000000000..184b77382c3d
--- /dev/null
+++ b/arch/m68knommu/platform/532x/gpio.c
@@ -0,0 +1,337 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "FECH",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 8,
50 },
51 .pddr = MCFGPIO_PDDR_FECH,
52 .podr = MCFGPIO_PODR_FECH,
53 .ppdr = MCFGPIO_PPDSDR_FECH,
54 .setr = MCFGPIO_PPDSDR_FECH,
55 .clrr = MCFGPIO_PCLRR_FECH,
56 },
57 {
58 .gpio_chip = {
59 .label = "FECL",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 8,
68 },
69 .pddr = MCFGPIO_PDDR_FECL,
70 .podr = MCFGPIO_PODR_FECL,
71 .ppdr = MCFGPIO_PPDSDR_FECL,
72 .setr = MCFGPIO_PPDSDR_FECL,
73 .clrr = MCFGPIO_PCLRR_FECL,
74 },
75 {
76 .gpio_chip = {
77 .label = "SSI",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 5,
86 },
87 .pddr = MCFGPIO_PDDR_SSI,
88 .podr = MCFGPIO_PODR_SSI,
89 .ppdr = MCFGPIO_PPDSDR_SSI,
90 .setr = MCFGPIO_PPDSDR_SSI,
91 .clrr = MCFGPIO_PCLRR_SSI,
92 },
93 {
94 .gpio_chip = {
95 .label = "BUSCTL",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = MCFGPIO_PDDR_BUSCTL,
106 .podr = MCFGPIO_PODR_BUSCTL,
107 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
108 .setr = MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = MCFGPIO_PCLRR_BUSCTL,
110 },
111 {
112 .gpio_chip = {
113 .label = "BE",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = MCFGPIO_PDDR_BE,
124 .podr = MCFGPIO_PODR_BE,
125 .ppdr = MCFGPIO_PPDSDR_BE,
126 .setr = MCFGPIO_PPDSDR_BE,
127 .clrr = MCFGPIO_PCLRR_BE,
128 },
129 {
130 .gpio_chip = {
131 .label = "CS",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 49,
139 .ngpio = 5,
140 },
141 .pddr = MCFGPIO_PDDR_CS,
142 .podr = MCFGPIO_PODR_CS,
143 .ppdr = MCFGPIO_PPDSDR_CS,
144 .setr = MCFGPIO_PPDSDR_CS,
145 .clrr = MCFGPIO_PCLRR_CS,
146 },
147 {
148 .gpio_chip = {
149 .label = "PWM",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 58,
157 .ngpio = 4,
158 },
159 .pddr = MCFGPIO_PDDR_PWM,
160 .podr = MCFGPIO_PODR_PWM,
161 .ppdr = MCFGPIO_PPDSDR_PWM,
162 .setr = MCFGPIO_PPDSDR_PWM,
163 .clrr = MCFGPIO_PCLRR_PWM,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECI2C",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 4,
176 },
177 .pddr = MCFGPIO_PDDR_FECI2C,
178 .podr = MCFGPIO_PODR_FECI2C,
179 .ppdr = MCFGPIO_PPDSDR_FECI2C,
180 .setr = MCFGPIO_PPDSDR_FECI2C,
181 .clrr = MCFGPIO_PCLRR_FECI2C,
182 },
183 {
184 .gpio_chip = {
185 .label = "UART",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = MCFGPIO_PDDR_UART,
196 .podr = MCFGPIO_PODR_UART,
197 .ppdr = MCFGPIO_PPDSDR_UART,
198 .setr = MCFGPIO_PPDSDR_UART,
199 .clrr = MCFGPIO_PCLRR_UART,
200 },
201 {
202 .gpio_chip = {
203 .label = "QSPI",
204 .request = mcf_gpio_request,
205 .free = mcf_gpio_free,
206 .direction_input = mcf_gpio_direction_input,
207 .direction_output = mcf_gpio_direction_output,
208 .get = mcf_gpio_get_value,
209 .set = mcf_gpio_set_value_fast,
210 .base = 80,
211 .ngpio = 6,
212 },
213 .pddr = MCFGPIO_PDDR_QSPI,
214 .podr = MCFGPIO_PODR_QSPI,
215 .ppdr = MCFGPIO_PPDSDR_QSPI,
216 .setr = MCFGPIO_PPDSDR_QSPI,
217 .clrr = MCFGPIO_PCLRR_QSPI,
218 },
219 {
220 .gpio_chip = {
221 .label = "TIMER",
222 .request = mcf_gpio_request,
223 .free = mcf_gpio_free,
224 .direction_input = mcf_gpio_direction_input,
225 .direction_output = mcf_gpio_direction_output,
226 .get = mcf_gpio_get_value,
227 .set = mcf_gpio_set_value_fast,
228 .base = 88,
229 .ngpio = 4,
230 },
231 .pddr = MCFGPIO_PDDR_TIMER,
232 .podr = MCFGPIO_PODR_TIMER,
233 .ppdr = MCFGPIO_PPDSDR_TIMER,
234 .setr = MCFGPIO_PPDSDR_TIMER,
235 .clrr = MCFGPIO_PCLRR_TIMER,
236 },
237 {
238 .gpio_chip = {
239 .label = "LCDDATAH",
240 .request = mcf_gpio_request,
241 .free = mcf_gpio_free,
242 .direction_input = mcf_gpio_direction_input,
243 .direction_output = mcf_gpio_direction_output,
244 .get = mcf_gpio_get_value,
245 .set = mcf_gpio_set_value_fast,
246 .base = 96,
247 .ngpio = 2,
248 },
249 .pddr = MCFGPIO_PDDR_LCDDATAH,
250 .podr = MCFGPIO_PODR_LCDDATAH,
251 .ppdr = MCFGPIO_PPDSDR_LCDDATAH,
252 .setr = MCFGPIO_PPDSDR_LCDDATAH,
253 .clrr = MCFGPIO_PCLRR_LCDDATAH,
254 },
255 {
256 .gpio_chip = {
257 .label = "LCDDATAM",
258 .request = mcf_gpio_request,
259 .free = mcf_gpio_free,
260 .direction_input = mcf_gpio_direction_input,
261 .direction_output = mcf_gpio_direction_output,
262 .get = mcf_gpio_get_value,
263 .set = mcf_gpio_set_value_fast,
264 .base = 104,
265 .ngpio = 8,
266 },
267 .pddr = MCFGPIO_PDDR_LCDDATAM,
268 .podr = MCFGPIO_PODR_LCDDATAM,
269 .ppdr = MCFGPIO_PPDSDR_LCDDATAM,
270 .setr = MCFGPIO_PPDSDR_LCDDATAM,
271 .clrr = MCFGPIO_PCLRR_LCDDATAM,
272 },
273 {
274 .gpio_chip = {
275 .label = "LCDDATAL",
276 .request = mcf_gpio_request,
277 .free = mcf_gpio_free,
278 .direction_input = mcf_gpio_direction_input,
279 .direction_output = mcf_gpio_direction_output,
280 .get = mcf_gpio_get_value,
281 .set = mcf_gpio_set_value_fast,
282 .base = 112,
283 .ngpio = 8,
284 },
285 .pddr = MCFGPIO_PDDR_LCDDATAL,
286 .podr = MCFGPIO_PODR_LCDDATAL,
287 .ppdr = MCFGPIO_PPDSDR_LCDDATAL,
288 .setr = MCFGPIO_PPDSDR_LCDDATAL,
289 .clrr = MCFGPIO_PCLRR_LCDDATAL,
290 },
291 {
292 .gpio_chip = {
293 .label = "LCDCTLH",
294 .request = mcf_gpio_request,
295 .free = mcf_gpio_free,
296 .direction_input = mcf_gpio_direction_input,
297 .direction_output = mcf_gpio_direction_output,
298 .get = mcf_gpio_get_value,
299 .set = mcf_gpio_set_value_fast,
300 .base = 120,
301 .ngpio = 1,
302 },
303 .pddr = MCFGPIO_PDDR_LCDCTLH,
304 .podr = MCFGPIO_PODR_LCDCTLH,
305 .ppdr = MCFGPIO_PPDSDR_LCDCTLH,
306 .setr = MCFGPIO_PPDSDR_LCDCTLH,
307 .clrr = MCFGPIO_PCLRR_LCDCTLH,
308 },
309 {
310 .gpio_chip = {
311 .label = "LCDCTLL",
312 .request = mcf_gpio_request,
313 .free = mcf_gpio_free,
314 .direction_input = mcf_gpio_direction_input,
315 .direction_output = mcf_gpio_direction_output,
316 .get = mcf_gpio_get_value,
317 .set = mcf_gpio_set_value_fast,
318 .base = 128,
319 .ngpio = 8,
320 },
321 .pddr = MCFGPIO_PDDR_LCDCTLL,
322 .podr = MCFGPIO_PODR_LCDCTLL,
323 .ppdr = MCFGPIO_PPDSDR_LCDCTLL,
324 .setr = MCFGPIO_PPDSDR_LCDCTLL,
325 .clrr = MCFGPIO_PCLRR_LCDCTLL,
326 },
327};
328
329static int __init mcf_gpio_init(void)
330{
331 unsigned i = 0;
332 while (i < ARRAY_SIZE(mcf_gpio_chips))
333 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
334 return 0;
335}
336
337core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5407/Makefile b/arch/m68knommu/platform/5407/Makefile
index e6035e7a2d3f..dee62c5dbaa6 100644
--- a/arch/m68knommu/platform/5407/Makefile
+++ b/arch/m68knommu/platform/5407/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index b41d942bf8d0..70ea789a400c 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -20,12 +20,6 @@
20 20
21/***************************************************************************/ 21/***************************************************************************/
22 22
23extern unsigned int mcf_timervector;
24extern unsigned int mcf_profilevector;
25extern unsigned int mcf_timerlevel;
26
27/***************************************************************************/
28
29static struct mcf_platform_uart m5407_uart_platform[] = { 23static struct mcf_platform_uart m5407_uart_platform[] = {
30 { 24 {
31 .mapbase = MCF_MBAR + MCFUART_BASE1, 25 .mapbase = MCF_MBAR + MCFUART_BASE1,
@@ -55,11 +49,11 @@ static void __init m5407_uart_init_line(int line, int irq)
55 if (line == 0) { 49 if (line == 0) {
56 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 50 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
57 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 51 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
58 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 52 mcf_mapirq2imr(irq, MCFINTC_UART0);
59 } else if (line == 1) { 53 } else if (line == 1) {
60 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 54 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
61 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 55 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
62 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 56 mcf_mapirq2imr(irq, MCFINTC_UART1);
63 } 57 }
64} 58}
65 59
@@ -74,35 +68,19 @@ static void __init m5407_uarts_init(void)
74 68
75/***************************************************************************/ 69/***************************************************************************/
76 70
77void mcf_autovector(unsigned int vec) 71static void __init m5407_timers_init(void)
78{
79 volatile unsigned char *mbar;
80
81 if ((vec >= 25) && (vec <= 31)) {
82 mbar = (volatile unsigned char *) MCF_MBAR;
83 vec = 0x1 << (vec - 24);
84 *(mbar + MCFSIM_AVR) |= vec;
85 mcf_setimr(mcf_getimr() & ~vec);
86 }
87}
88
89/***************************************************************************/
90
91void mcf_settimericr(unsigned int timer, unsigned int level)
92{ 72{
93 volatile unsigned char *icrp; 73 /* Timer1 is always used as system timer */
94 unsigned int icr, imr; 74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
95 75 MCF_MBAR + MCFSIM_TIMER1ICR);
96 if (timer <= 2) { 76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
97 switch (timer) { 77
98 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 78#ifdef CONFIG_HIGHPROFILE
99 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 79 /* Timer2 is to be used as a high speed profile timer */
100 } 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
101 81 MCF_MBAR + MCFSIM_TIMER2ICR);
102 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
103 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 83#endif
104 mcf_setimr(mcf_getimr() & ~imr);
105 }
106} 84}
107 85
108/***************************************************************************/ 86/***************************************************************************/
@@ -120,23 +98,21 @@ void m5407_cpu_reset(void)
120 98
121void __init config_BSP(char *commandp, int size) 99void __init config_BSP(char *commandp, int size)
122{ 100{
123 mcf_setimr(MCFSIM_IMR_MASKALL);
124
125#if defined(CONFIG_CLEOPATRA)
126 /* Different timer setup - to prevent device clash */
127 mcf_timervector = 30;
128 mcf_profilevector = 31;
129 mcf_timerlevel = 6;
130#endif
131
132 mach_reset = m5407_cpu_reset; 101 mach_reset = m5407_cpu_reset;
102 m5407_timers_init();
103 m5407_uarts_init();
104
105 /* Only support the external interrupts on their primary level */
106 mcf_mapirq2imr(25, MCFINTC_EINT1);
107 mcf_mapirq2imr(27, MCFINTC_EINT3);
108 mcf_mapirq2imr(29, MCFINTC_EINT5);
109 mcf_mapirq2imr(31, MCFINTC_EINT7);
133} 110}
134 111
135/***************************************************************************/ 112/***************************************************************************/
136 113
137static int __init init_BSP(void) 114static int __init init_BSP(void)
138{ 115{
139 m5407_uarts_init();
140 platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices)); 116 platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
141 return 0; 117 return 0;
142} 118}
diff --git a/arch/m68knommu/platform/5407/gpio.c b/arch/m68knommu/platform/5407/gpio.c
new file mode 100644
index 000000000000..8da5880e4066
--- /dev/null
+++ b/arch/m68knommu/platform/5407/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c
index 72e56d554f4f..b91ee85d4b5d 100644
--- a/arch/m68knommu/platform/68328/ints.c
+++ b/arch/m68knommu/platform/68328/ints.c
@@ -73,34 +73,6 @@ extern e_vector *_ramvec;
73/* The number of spurious interrupts */ 73/* The number of spurious interrupts */
74volatile unsigned int num_spurious; 74volatile unsigned int num_spurious;
75 75
76/*
77 * This function should be called during kernel startup to initialize
78 * the machine vector table.
79 */
80void __init init_vectors(void)
81{
82 int i;
83
84 /* set up the vectors */
85 for (i = 72; i < 256; ++i)
86 _ramvec[i] = (e_vector) bad_interrupt;
87
88 _ramvec[32] = system_call;
89
90 _ramvec[65] = (e_vector) inthandler1;
91 _ramvec[66] = (e_vector) inthandler2;
92 _ramvec[67] = (e_vector) inthandler3;
93 _ramvec[68] = (e_vector) inthandler4;
94 _ramvec[69] = (e_vector) inthandler5;
95 _ramvec[70] = (e_vector) inthandler6;
96 _ramvec[71] = (e_vector) inthandler7;
97
98 IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
99
100 /* turn off all interrupts */
101 IMR = ~0;
102}
103
104/* The 68k family did not have a good way to determine the source 76/* The 68k family did not have a good way to determine the source
105 * of interrupts until later in the family. The EC000 core does 77 * of interrupts until later in the family. The EC000 core does
106 * not provide the vector number on the stack, we vector everything 78 * not provide the vector number on the stack, we vector everything
@@ -163,18 +135,54 @@ void process_int(int vec, struct pt_regs *fp)
163 } 135 }
164} 136}
165 137
166void enable_vector(unsigned int irq) 138static void intc_irq_unmask(unsigned int irq)
167{ 139{
168 IMR &= ~(1<<irq); 140 IMR &= ~(1<<irq);
169} 141}
170 142
171void disable_vector(unsigned int irq) 143static void intc_irq_mask(unsigned int irq)
172{ 144{
173 IMR |= (1<<irq); 145 IMR |= (1<<irq);
174} 146}
175 147
176void ack_vector(unsigned int irq) 148static struct irq_chip intc_irq_chip = {
149 .name = "M68K-INTC",
150 .mask = intc_irq_mask,
151 .unmask = intc_irq_unmask,
152};
153
154/*
155 * This function should be called during kernel startup to initialize
156 * the machine vector table.
157 */
158void __init init_IRQ(void)
177{ 159{
178 /* Nothing needed */ 160 int i;
161
162 /* set up the vectors */
163 for (i = 72; i < 256; ++i)
164 _ramvec[i] = (e_vector) bad_interrupt;
165
166 _ramvec[32] = system_call;
167
168 _ramvec[65] = (e_vector) inthandler1;
169 _ramvec[66] = (e_vector) inthandler2;
170 _ramvec[67] = (e_vector) inthandler3;
171 _ramvec[68] = (e_vector) inthandler4;
172 _ramvec[69] = (e_vector) inthandler5;
173 _ramvec[70] = (e_vector) inthandler6;
174 _ramvec[71] = (e_vector) inthandler7;
175
176 IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
177
178 /* turn off all interrupts */
179 IMR = ~0;
180
181 for (i = 0; (i < NR_IRQS); i++) {
182 irq_desc[i].status = IRQ_DISABLED;
183 irq_desc[i].action = NULL;
184 irq_desc[i].depth = 1;
185 irq_desc[i].chip = &intc_irq_chip;
186 }
179} 187}
180 188
diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c
index c36781157e09..1143f77caca4 100644
--- a/arch/m68knommu/platform/68360/ints.c
+++ b/arch/m68knommu/platform/68360/ints.c
@@ -37,11 +37,33 @@ extern void *_ramvec[];
37/* The number of spurious interrupts */ 37/* The number of spurious interrupts */
38volatile unsigned int num_spurious; 38volatile unsigned int num_spurious;
39 39
40static void intc_irq_unmask(unsigned int irq)
41{
42 pquicc->intr_cimr |= (1 << irq);
43}
44
45static void intc_irq_mask(unsigned int irq)
46{
47 pquicc->intr_cimr &= ~(1 << irq);
48}
49
50static void intc_irq_ack(unsigned int irq)
51{
52 pquicc->intr_cisr = (1 << irq);
53}
54
55static struct irq_chip intc_irq_chip = {
56 .name = "M68K-INTC",
57 .mask = intc_irq_mask,
58 .unmask = intc_irq_unmask,
59 .ack = intc_irq_ack,
60};
61
40/* 62/*
41 * This function should be called during kernel startup to initialize 63 * This function should be called during kernel startup to initialize
42 * the vector table. 64 * the vector table.
43 */ 65 */
44void init_vectors(void) 66void init_IRQ(void)
45{ 67{
46 int i; 68 int i;
47 int vba = (CPM_VECTOR_BASE<<4); 69 int vba = (CPM_VECTOR_BASE<<4);
@@ -109,20 +131,12 @@ void init_vectors(void)
109 131
110 /* turn off all CPM interrupts */ 132 /* turn off all CPM interrupts */
111 pquicc->intr_cimr = 0x00000000; 133 pquicc->intr_cimr = 0x00000000;
112}
113
114void enable_vector(unsigned int irq)
115{
116 pquicc->intr_cimr |= (1 << irq);
117}
118 134
119void disable_vector(unsigned int irq) 135 for (i = 0; (i < NR_IRQS); i++) {
120{ 136 irq_desc[i].status = IRQ_DISABLED;
121 pquicc->intr_cimr &= ~(1 << irq); 137 irq_desc[i].action = NULL;
122} 138 irq_desc[i].depth = 1;
123 139 irq_desc[i].chip = &intc_irq_chip;
124void ack_vector(unsigned int irq) 140 }
125{
126 pquicc->intr_cisr = (1 << irq);
127} 141}
128 142
diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index 1bcb9372353f..f72a0e5d9996 100644
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -15,16 +15,17 @@
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o 17obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o
18obj-$(CONFIG_M5206) += timers.o 18obj-$(CONFIG_M5206) += timers.o intc.o
19obj-$(CONFIG_M5206e) += timers.o 19obj-$(CONFIG_M5206e) += timers.o intc.o
20obj-$(CONFIG_M520x) += pit.o 20obj-$(CONFIG_M520x) += pit.o intc-simr.o
21obj-$(CONFIG_M523x) += pit.o dma_timer.o 21obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o
22obj-$(CONFIG_M5249) += timers.o 22obj-$(CONFIG_M5249) += timers.o intc.o
23obj-$(CONFIG_M527x) += pit.o 23obj-$(CONFIG_M527x) += pit.o intc-2.o
24obj-$(CONFIG_M5272) += timers.o 24obj-$(CONFIG_M5272) += timers.o
25obj-$(CONFIG_M528x) += pit.o 25obj-$(CONFIG_M528x) += pit.o intc-2.o
26obj-$(CONFIG_M5307) += timers.o 26obj-$(CONFIG_M5307) += timers.o intc.o
27obj-$(CONFIG_M532x) += timers.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o
28obj-$(CONFIG_M5407) += timers.o 28obj-$(CONFIG_M5407) += timers.o intc.o
29 29
30obj-y += pinmux.o gpio.o
30extra-y := head.o 31extra-y := head.o
diff --git a/arch/m68knommu/platform/coldfire/gpio.c b/arch/m68knommu/platform/coldfire/gpio.c
new file mode 100644
index 000000000000..ff0045793450
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/gpio.c
@@ -0,0 +1,127 @@
1/*
2 * Coldfire generic GPIO support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/sysdev.h>
19
20#include <asm/gpio.h>
21#include <asm/pinmux.h>
22#include <asm/mcfgpio.h>
23
24#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip)
25
26int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
27{
28 unsigned long flags;
29 MCFGPIO_PORTTYPE dir;
30 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
31
32 local_irq_save(flags);
33 dir = mcfgpio_read(mcf_chip->pddr);
34 dir &= ~mcfgpio_bit(chip->base + offset);
35 mcfgpio_write(dir, mcf_chip->pddr);
36 local_irq_restore(flags);
37
38 return 0;
39}
40
41int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset)
42{
43 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
44
45 return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset);
46}
47
48int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
49 int value)
50{
51 unsigned long flags;
52 MCFGPIO_PORTTYPE data;
53 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
54
55 local_irq_save(flags);
56 /* write the value to the output latch */
57 data = mcfgpio_read(mcf_chip->podr);
58 if (value)
59 data |= mcfgpio_bit(chip->base + offset);
60 else
61 data &= ~mcfgpio_bit(chip->base + offset);
62 mcfgpio_write(data, mcf_chip->podr);
63
64 /* now set the direction to output */
65 data = mcfgpio_read(mcf_chip->pddr);
66 data |= mcfgpio_bit(chip->base + offset);
67 mcfgpio_write(data, mcf_chip->pddr);
68 local_irq_restore(flags);
69
70 return 0;
71}
72
73void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
74{
75 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
76
77 unsigned long flags;
78 MCFGPIO_PORTTYPE data;
79
80 local_irq_save(flags);
81 data = mcfgpio_read(mcf_chip->podr);
82 if (value)
83 data |= mcfgpio_bit(chip->base + offset);
84 else
85 data &= ~mcfgpio_bit(chip->base + offset);
86 mcfgpio_write(data, mcf_chip->podr);
87 local_irq_restore(flags);
88}
89
90void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value)
91{
92 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
93
94 if (value)
95 mcfgpio_write(mcfgpio_bit(chip->base + offset), mcf_chip->setr);
96 else
97 mcfgpio_write(~mcfgpio_bit(chip->base + offset), mcf_chip->clrr);
98}
99
100int mcf_gpio_request(struct gpio_chip *chip, unsigned offset)
101{
102 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
103
104 return mcf_chip->gpio_to_pinmux ?
105 mcf_pinmux_request(mcf_chip->gpio_to_pinmux[offset], 0) : 0;
106}
107
108void mcf_gpio_free(struct gpio_chip *chip, unsigned offset)
109{
110 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
111
112 mcf_gpio_direction_input(chip, offset);
113
114 if (mcf_chip->gpio_to_pinmux)
115 mcf_pinmux_release(mcf_chip->gpio_to_pinmux[offset], 0);
116}
117
118struct sysdev_class mcf_gpio_sysclass = {
119 .name = "gpio",
120};
121
122static int __init mcf_gpio_sysinit(void)
123{
124 return sysdev_class_register(&mcf_gpio_sysclass);
125}
126
127core_initcall(mcf_gpio_sysinit);
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
new file mode 100644
index 000000000000..5598c8b8661f
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -0,0 +1,93 @@
1/*
2 * intc-1.c
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/traps.h>
20
21/*
22 * Each vector needs a unique priority and level asscoiated with it.
23 * We don't really care so much what they are, we don't rely on the
24 * tranditional priority interrupt scheme of the m68k/ColdFire.
25 */
26static u8 intc_intpri = 0x36;
27
28static void intc_irq_mask(unsigned int irq)
29{
30 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
31 unsigned long imraddr;
32 u32 val, imrbit;
33
34 irq -= MCFINT_VECBASE;
35 imraddr = MCF_IPSBAR;
36 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
37 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
38 imrbit = 0x1 << (irq & 0x1f);
39
40 val = __raw_readl(imraddr);
41 __raw_writel(val | imrbit, imraddr);
42 }
43}
44
45static void intc_irq_unmask(unsigned int irq)
46{
47 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
48 unsigned long intaddr, imraddr, icraddr;
49 u32 val, imrbit;
50
51 irq -= MCFINT_VECBASE;
52 intaddr = MCF_IPSBAR;
53 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
54 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
55 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
56 imrbit = 0x1 << (irq & 0x1f);
57
58 /* Don't set the "maskall" bit! */
59 if ((irq & 0x20) == 0)
60 imrbit |= 0x1;
61
62 if (__raw_readb(icraddr) == 0)
63 __raw_writeb(intc_intpri--, icraddr);
64
65 val = __raw_readl(imraddr);
66 __raw_writel(val & ~imrbit, imraddr);
67 }
68}
69
70static struct irq_chip intc_irq_chip = {
71 .name = "CF-INTC",
72 .mask = intc_irq_mask,
73 .unmask = intc_irq_unmask,
74};
75
76void __init init_IRQ(void)
77{
78 int irq;
79
80 init_vectors();
81
82 /* Mask all interrupt sources */
83 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
84 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
85
86 for (irq = 0; (irq < NR_IRQS); irq++) {
87 irq_desc[irq].status = IRQ_DISABLED;
88 irq_desc[irq].action = NULL;
89 irq_desc[irq].depth = 1;
90 irq_desc[irq].chip = &intc_irq_chip;
91 }
92}
93
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
new file mode 100644
index 000000000000..1b01e79c2f63
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -0,0 +1,78 @@
1/*
2 * intc-simr.c
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/traps.h>
20
21static void intc_irq_mask(unsigned int irq)
22{
23 if (irq >= MCFINT_VECBASE) {
24 if (irq < MCFINT_VECBASE + 64)
25 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
26 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
27 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
28 }
29}
30
31static void intc_irq_unmask(unsigned int irq)
32{
33 if (irq >= MCFINT_VECBASE) {
34 if (irq < MCFINT_VECBASE + 64)
35 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
36 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
37 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
38 }
39}
40
41static int intc_irq_set_type(unsigned int irq, unsigned int type)
42{
43 if (irq >= MCFINT_VECBASE) {
44 if (irq < MCFINT_VECBASE + 64)
45 __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
46 else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
47 __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
48 }
49 return 0;
50}
51
52static struct irq_chip intc_irq_chip = {
53 .name = "CF-INTC",
54 .mask = intc_irq_mask,
55 .unmask = intc_irq_unmask,
56 .set_type = intc_irq_set_type,
57};
58
59void __init init_IRQ(void)
60{
61 int irq;
62
63 init_vectors();
64
65 /* Mask all interrupt sources */
66 __raw_writeb(0xff, MCFINTC0_SIMR);
67 if (MCFINTC1_SIMR)
68 __raw_writeb(0xff, MCFINTC1_SIMR);
69
70 for (irq = 0; (irq < NR_IRQS); irq++) {
71 irq_desc[irq].status = IRQ_DISABLED;
72 irq_desc[irq].action = NULL;
73 irq_desc[irq].depth = 1;
74 irq_desc[irq].chip = &intc_irq_chip;
75 intc_irq_set_type(irq, 0);
76 }
77}
78
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
new file mode 100644
index 000000000000..a4560c86db71
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -0,0 +1,153 @@
1/*
2 * intc.c -- support for the old ColdFire interrupt controller
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/traps.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21/*
22 * The mapping of irq number to a mask register bit is not one-to-one.
23 * The irq numbers are either based on "level" of interrupt or fixed
24 * for an autovector-able interrupt. So we keep a local data structure
25 * that maps from irq to mask register. Not all interrupts will have
26 * an IMR bit.
27 */
28unsigned char mcf_irq2imr[NR_IRQS];
29
30/*
31 * Define the miniumun and maximum external interrupt numbers.
32 * This is also used as the "level" interrupt numbers.
33 */
34#define EIRQ1 25
35#define EIRQ7 31
36
37/*
38 * In the early version 2 core ColdFire parts the IMR register was 16 bits
39 * in size. Version 3 (and later version 2) core parts have a 32 bit
40 * sized IMR register. Provide some size independant methods to access the
41 * IMR register.
42 */
43#ifdef MCFSIM_IMR_IS_16BITS
44
45void mcf_setimr(int index)
46{
47 u16 imr;
48 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
49 __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
50}
51
52void mcf_clrimr(int index)
53{
54 u16 imr;
55 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
56 __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
57}
58
59void mcf_maskimr(unsigned int mask)
60{
61 u16 imr;
62 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
63 imr |= mask;
64 __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
65}
66
67#else
68
69void mcf_setimr(int index)
70{
71 u32 imr;
72 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
73 __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
74}
75
76void mcf_clrimr(int index)
77{
78 u32 imr;
79 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
80 __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
81}
82
83void mcf_maskimr(unsigned int mask)
84{
85 u32 imr;
86 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
87 imr |= mask;
88 __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
89}
90
91#endif
92
93/*
94 * Interrupts can be "vectored" on the ColdFire cores that support this old
95 * interrupt controller. That is, the device raising the interrupt can also
96 * supply the vector number to interrupt through. The AVR register of the
97 * interrupt controller enables or disables this for each external interrupt,
98 * so provide generic support for this. Setting this up is out-of-band for
99 * the interrupt system API's, and needs to be done by the driver that
100 * supports this device. Very few devices actually use this.
101 */
102void mcf_autovector(int irq)
103{
104#ifdef MCFSIM_AVR
105 if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
106 u8 avec;
107 avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
108 avec |= (0x1 << (irq - EIRQ1 + 1));
109 __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
110 }
111#endif
112}
113
114static void intc_irq_mask(unsigned int irq)
115{
116 if (mcf_irq2imr[irq])
117 mcf_setimr(mcf_irq2imr[irq]);
118}
119
120static void intc_irq_unmask(unsigned int irq)
121{
122 if (mcf_irq2imr[irq])
123 mcf_clrimr(mcf_irq2imr[irq]);
124}
125
126static int intc_irq_set_type(unsigned int irq, unsigned int type)
127{
128 return 0;
129}
130
131static struct irq_chip intc_irq_chip = {
132 .name = "CF-INTC",
133 .mask = intc_irq_mask,
134 .unmask = intc_irq_unmask,
135 .set_type = intc_irq_set_type,
136};
137
138void __init init_IRQ(void)
139{
140 int irq;
141
142 init_vectors();
143 mcf_maskimr(0xffffffff);
144
145 for (irq = 0; (irq < NR_IRQS); irq++) {
146 irq_desc[irq].status = IRQ_DISABLED;
147 irq_desc[irq].action = NULL;
148 irq_desc[irq].depth = 1;
149 irq_desc[irq].chip = &intc_irq_chip;
150 intc_irq_set_type(irq, 0);
151 }
152}
153
diff --git a/arch/m68knommu/platform/coldfire/pinmux.c b/arch/m68knommu/platform/coldfire/pinmux.c
new file mode 100644
index 000000000000..8c62b825939f
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/pinmux.c
@@ -0,0 +1,28 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/pinmux.h>
20
21int mcf_pinmux_request(unsigned pinmux, unsigned func)
22{
23 return 0;
24}
25
26void mcf_pinmux_release(unsigned pinmux, unsigned func)
27{
28}
diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c
index 61b96211f8ff..d8720ee34510 100644
--- a/arch/m68knommu/platform/coldfire/pit.c
+++ b/arch/m68knommu/platform/coldfire/pit.c
@@ -32,7 +32,6 @@
32 */ 32 */
33#define FREQ ((MCF_CLK / 2) / 64) 33#define FREQ ((MCF_CLK / 2) / 64)
34#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) 34#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
35#define INTC0 (MCF_IPSBAR + MCFICM_INTC0)
36#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) 35#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
37 36
38static u32 pit_cnt; 37static u32 pit_cnt;
@@ -154,8 +153,6 @@ static struct clocksource pit_clk = {
154 153
155void hw_timer_init(void) 154void hw_timer_init(void)
156{ 155{
157 u32 imr;
158
159 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); 156 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
160 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); 157 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
161 cf_pit_clockevent.max_delta_ns = 158 cf_pit_clockevent.max_delta_ns =
@@ -166,11 +163,6 @@ void hw_timer_init(void)
166 163
167 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); 164 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
168 165
169 __raw_writeb(ICR_INTRCONF, INTC0 + MCFINTC_ICR0 + MCFINT_PIT1);
170 imr = __raw_readl(INTC0 + MCFPIT_IMR);
171 imr &= ~MCFPIT_IMR_IBIT;
172 __raw_writel(imr, INTC0 + MCFPIT_IMR);
173
174 pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift); 166 pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
175 clocksource_register(&pit_clk); 167 clocksource_register(&pit_clk);
176} 168}
diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c
index 1ba8a3731653..2304d736c701 100644
--- a/arch/m68knommu/platform/coldfire/timers.c
+++ b/arch/m68knommu/platform/coldfire/timers.c
@@ -31,19 +31,9 @@
31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a)) 31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
32 32
33/* 33/*
34 * Default the timer and vector to use for ColdFire. Some ColdFire
35 * CPU's and some boards may want different. Their sub-architecture
36 * startup code (in config.c) can change these if they want.
37 */
38unsigned int mcf_timervector = 29;
39unsigned int mcf_profilevector = 31;
40unsigned int mcf_timerlevel = 5;
41
42/*
43 * These provide the underlying interrupt vector support. 34 * These provide the underlying interrupt vector support.
44 * Unfortunately it is a little different on each ColdFire. 35 * Unfortunately it is a little different on each ColdFire.
45 */ 36 */
46extern void mcf_settimericr(int timer, int level);
47void coldfire_profile_init(void); 37void coldfire_profile_init(void);
48 38
49#if defined(CONFIG_M532x) 39#if defined(CONFIG_M532x)
@@ -107,8 +97,6 @@ static struct clocksource mcftmr_clk = {
107 97
108void hw_timer_init(void) 98void hw_timer_init(void)
109{ 99{
110 setup_irq(mcf_timervector, &mcftmr_timer_irq);
111
112 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); 100 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
113 mcftmr_cycles_per_jiffy = FREQ / HZ; 101 mcftmr_cycles_per_jiffy = FREQ / HZ;
114 /* 102 /*
@@ -124,7 +112,7 @@ void hw_timer_init(void)
124 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift); 112 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
125 clocksource_register(&mcftmr_clk); 113 clocksource_register(&mcftmr_clk);
126 114
127 mcf_settimericr(1, mcf_timerlevel); 115 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
128 116
129#ifdef CONFIG_HIGHPROFILE 117#ifdef CONFIG_HIGHPROFILE
130 coldfire_profile_init(); 118 coldfire_profile_init();
@@ -171,8 +159,6 @@ void coldfire_profile_init(void)
171 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", 159 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
172 PROFILEHZ); 160 PROFILEHZ);
173 161
174 setup_irq(mcf_profilevector, &coldfire_profile_irq);
175
176 /* Set up TIMER 2 as high speed profile clock */ 162 /* Set up TIMER 2 as high speed profile clock */
177 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); 163 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
178 164
@@ -180,7 +166,7 @@ void coldfire_profile_init(void)
180 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | 166 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
181 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); 167 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
182 168
183 mcf_settimericr(2, 7); 169 setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq);
184} 170}
185 171
186/***************************************************************************/ 172/***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/vectors.c b/arch/m68knommu/platform/coldfire/vectors.c
index bdca0297fa9a..a21d3f870b7a 100644
--- a/arch/m68knommu/platform/coldfire/vectors.c
+++ b/arch/m68knommu/platform/coldfire/vectors.c
@@ -1,7 +1,7 @@
1/***************************************************************************/ 1/***************************************************************************/
2 2
3/* 3/*
4 * linux/arch/m68knommu/platform/5307/vectors.c 4 * linux/arch/m68knommu/platform/coldfire/vectors.c
5 * 5 *
6 * Copyright (C) 1999-2007, Greg Ungerer <gerg@snapgear.com> 6 * Copyright (C) 1999-2007, Greg Ungerer <gerg@snapgear.com>
7 */ 7 */
@@ -15,7 +15,6 @@
15#include <asm/machdep.h> 15#include <asm/machdep.h>
16#include <asm/coldfire.h> 16#include <asm/coldfire.h>
17#include <asm/mcfsim.h> 17#include <asm/mcfsim.h>
18#include <asm/mcfdma.h>
19#include <asm/mcfwdebug.h> 18#include <asm/mcfwdebug.h>
20 19
21/***************************************************************************/ 20/***************************************************************************/
@@ -79,20 +78,3 @@ void __init init_vectors(void)
79} 78}
80 79
81/***************************************************************************/ 80/***************************************************************************/
82
83void enable_vector(unsigned int irq)
84{
85 /* Currently no action on ColdFire */
86}
87
88void disable_vector(unsigned int irq)
89{
90 /* Currently no action on ColdFire */
91}
92
93void ack_vector(unsigned int irq)
94{
95 /* Currently no action on ColdFire */
96}
97
98/***************************************************************************/
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 12:20:12 -0500