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authorGreg Ungerer <gerg@uclinux.org>2011-03-05 07:17:17 -0500
committerGreg Ungerer <gerg@uclinux.org>2011-03-15 07:01:53 -0400
commit254eef7464f0704290af4b91021f512eb4c98d59 (patch)
tree4bc61d36dbb146eed72b166f7f75c06d7384adea /arch/m68knommu
parentf2ba710d17ae221e21a7cccddbbf5257fd93e9fa (diff)
m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx
The ColdFire 54xx family shares the same interrupt controller used on the 523x, 527x and 528x ColdFire parts, but it isn't offset relative to the IPSBAR register. The 54xx doesn't have an IPSBAR register. By including the base address of the peripheral registers in the register definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid having to define a fake IPSBAR for the 54xx. And this makes the register address definitions of these more consistent, the majority of the other register address defines include the peripheral base address already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/platform/coldfire/intc-2.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 71e07fb69302..ec869c8e8890 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -52,11 +52,10 @@ static void intc_irq_mask(struct irq_data *d)
52 u32 val, imrbit; 52 u32 val, imrbit;
53 53
54 irq -= MCFINT_VECBASE; 54 irq -= MCFINT_VECBASE;
55 imraddr = MCF_IPSBAR;
56#ifdef MCFICM_INTC1 55#ifdef MCFICM_INTC1
57 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 56 imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
58#else 57#else
59 imraddr += MCFICM_INTC0; 58 imraddr = MCFICM_INTC0;
60#endif 59#endif
61 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; 60 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
62 imrbit = 0x1 << (irq & 0x1f); 61 imrbit = 0x1 << (irq & 0x1f);
@@ -75,11 +74,10 @@ static void intc_irq_unmask(struct irq_data *d)
75 u32 val, imrbit; 74 u32 val, imrbit;
76 75
77 irq -= MCFINT_VECBASE; 76 irq -= MCFINT_VECBASE;
78 intaddr = MCF_IPSBAR;
79#ifdef MCFICM_INTC1 77#ifdef MCFICM_INTC1
80 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 78 intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
81#else 79#else
82 intaddr += MCFICM_INTC0; 80 intaddr = MCFICM_INTC0;
83#endif 81#endif
84 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); 82 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
85 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); 83 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
@@ -116,9 +114,9 @@ void __init init_IRQ(void)
116 init_vectors(); 114 init_vectors();
117 115
118 /* Mask all interrupt sources */ 116 /* Mask all interrupt sources */
119 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); 117 __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
120#ifdef MCFICM_INTC1 118#ifdef MCFICM_INTC1
121 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); 119 __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
122#endif 120#endif
123 121
124 for (irq = 0; (irq < NR_IRQS); irq++) { 122 for (irq = 0; (irq < NR_IRQS); irq++) {