diff options
author | Greg Ungerer <gerg@snapgear.com> | 2006-12-05 20:36:59 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-06 10:41:26 -0500 |
commit | deb77c8501f47ab228bf7cc7fd649e50603ed2cd (patch) | |
tree | 9a55c608f3eb4783c109da1401f707546e85423a /arch/m68knommu | |
parent | dd93e857fca0f6dedb8b0ffe61bf5096029963bb (diff) |
[PATCH] m68knommu: fix timer register access on 523x ColdFire platforms
The 523x timer TRR register is a full 32bits, the older register (on
other ColdFire parts) was only 16 bits. Use the right type of
__raw_read when accessing it.
Problem found by Yaroslav Vinogradov <yaroslav.vinogradov@freescale.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r-- | arch/m68knommu/platform/5307/timers.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/m68knommu/platform/5307/timers.c b/arch/m68knommu/platform/5307/timers.c index 24781f009337..e5668af19789 100644 --- a/arch/m68knommu/platform/5307/timers.c +++ b/arch/m68knommu/platform/5307/timers.c | |||
@@ -3,7 +3,7 @@ | |||
3 | /* | 3 | /* |
4 | * timers.c -- generic ColdFire hardware timer support. | 4 | * timers.c -- generic ColdFire hardware timer support. |
5 | * | 5 | * |
6 | * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) | 6 | * Copyright (C) 1999-2006, Greg Ungerer (gerg@snapgear.com) |
7 | */ | 7 | */ |
8 | 8 | ||
9 | /***************************************************************************/ | 9 | /***************************************************************************/ |
@@ -44,6 +44,14 @@ unsigned int mcf_timerlevel = 5; | |||
44 | extern void mcf_settimericr(int timer, int level); | 44 | extern void mcf_settimericr(int timer, int level); |
45 | extern int mcf_timerirqpending(int timer); | 45 | extern int mcf_timerirqpending(int timer); |
46 | 46 | ||
47 | #if defined(CONFIG_M532x) | ||
48 | #define __raw_readtrr __raw_readl | ||
49 | #define __raw_writetrr __raw_writel | ||
50 | #else | ||
51 | #define __raw_readtrr __raw_readw | ||
52 | #define __raw_writetrr __raw_writew | ||
53 | #endif | ||
54 | |||
47 | /***************************************************************************/ | 55 | /***************************************************************************/ |
48 | 56 | ||
49 | void coldfire_tick(void) | 57 | void coldfire_tick(void) |
@@ -57,7 +65,7 @@ void coldfire_tick(void) | |||
57 | void coldfire_timer_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)) | 65 | void coldfire_timer_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)) |
58 | { | 66 | { |
59 | __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); | 67 | __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); |
60 | __raw_writew(((MCF_BUSCLK / 16) / HZ), TA(MCFTIMER_TRR)); | 68 | __raw_writetrr(((MCF_BUSCLK / 16) / HZ), TA(MCFTIMER_TRR)); |
61 | __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | | 69 | __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | |
62 | MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); | 70 | MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); |
63 | 71 | ||
@@ -76,7 +84,7 @@ unsigned long coldfire_timer_offset(void) | |||
76 | unsigned long trr, tcn, offset; | 84 | unsigned long trr, tcn, offset; |
77 | 85 | ||
78 | tcn = __raw_readw(TA(MCFTIMER_TCN)); | 86 | tcn = __raw_readw(TA(MCFTIMER_TCN)); |
79 | trr = __raw_readw(TA(MCFTIMER_TRR)); | 87 | trr = __raw_readtrr(TA(MCFTIMER_TRR)); |
80 | offset = (tcn * (1000000 / HZ)) / trr; | 88 | offset = (tcn * (1000000 / HZ)) / trr; |
81 | 89 | ||
82 | /* Check if we just wrapped the counters and maybe missed a tick */ | 90 | /* Check if we just wrapped the counters and maybe missed a tick */ |
@@ -120,7 +128,7 @@ void coldfire_profile_init(void) | |||
120 | /* Set up TIMER 2 as high speed profile clock */ | 128 | /* Set up TIMER 2 as high speed profile clock */ |
121 | __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); | 129 | __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); |
122 | 130 | ||
123 | __raw_writew(((MCF_CLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR)); | 131 | __raw_writetrr(((MCF_CLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR)); |
124 | __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | | 132 | __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | |
125 | MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); | 133 | MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); |
126 | 134 | ||