diff options
author | Greg Ungerer <gerg@uclinux.org> | 2009-05-21 23:33:35 -0400 |
---|---|---|
committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-15 19:43:52 -0400 |
commit | 39f0fb6a3448cfc316e0d5295ed1b121db50037e (patch) | |
tree | 657db8073835e8d499708a898a36f1d3a1e39a32 /arch/m68knommu/platform/5407 | |
parent | f6a66276f5fdc018d2a9378c71de3bae13c588d7 (diff) |
m68knommu: map ColdFire interrupts to correct masking bits
The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/5407')
-rw-r--r-- | arch/m68knommu/platform/5407/config.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c index cc80029a4a00..70ea789a400c 100644 --- a/arch/m68knommu/platform/5407/config.c +++ b/arch/m68knommu/platform/5407/config.c | |||
@@ -49,12 +49,11 @@ static void __init m5407_uart_init_line(int line, int irq) | |||
49 | if (line == 0) { | 49 | if (line == 0) { |
50 | writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); | 50 | writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); |
51 | writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); | 51 | writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); |
52 | mcf_clrimr(MCFINTC_UART0); | 52 | mcf_mapirq2imr(irq, MCFINTC_UART0); |
53 | } else if (line == 1) { | 53 | } else if (line == 1) { |
54 | writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); | 54 | writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); |
55 | writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); | 55 | writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); |
56 | mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); | 56 | mcf_mapirq2imr(irq, MCFINTC_UART1); |
57 | mcf_clrimr(MCFINTC_UART1); | ||
58 | } | 57 | } |
59 | } | 58 | } |
60 | 59 | ||
@@ -74,11 +73,13 @@ static void __init m5407_timers_init(void) | |||
74 | /* Timer1 is always used as system timer */ | 73 | /* Timer1 is always used as system timer */ |
75 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, | 74 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, |
76 | MCF_MBAR + MCFSIM_TIMER1ICR); | 75 | MCF_MBAR + MCFSIM_TIMER1ICR); |
76 | mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); | ||
77 | 77 | ||
78 | #ifdef CONFIG_HIGHPROFILE | 78 | #ifdef CONFIG_HIGHPROFILE |
79 | /* Timer2 is to be used as a high speed profile timer */ | 79 | /* Timer2 is to be used as a high speed profile timer */ |
80 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, | 80 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, |
81 | MCF_MBAR + MCFSIM_TIMER2ICR); | 81 | MCF_MBAR + MCFSIM_TIMER2ICR); |
82 | mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); | ||
82 | #endif | 83 | #endif |
83 | } | 84 | } |
84 | 85 | ||
@@ -99,13 +100,19 @@ void __init config_BSP(char *commandp, int size) | |||
99 | { | 100 | { |
100 | mach_reset = m5407_cpu_reset; | 101 | mach_reset = m5407_cpu_reset; |
101 | m5407_timers_init(); | 102 | m5407_timers_init(); |
103 | m5407_uarts_init(); | ||
104 | |||
105 | /* Only support the external interrupts on their primary level */ | ||
106 | mcf_mapirq2imr(25, MCFINTC_EINT1); | ||
107 | mcf_mapirq2imr(27, MCFINTC_EINT3); | ||
108 | mcf_mapirq2imr(29, MCFINTC_EINT5); | ||
109 | mcf_mapirq2imr(31, MCFINTC_EINT7); | ||
102 | } | 110 | } |
103 | 111 | ||
104 | /***************************************************************************/ | 112 | /***************************************************************************/ |
105 | 113 | ||
106 | static int __init init_BSP(void) | 114 | static int __init init_BSP(void) |
107 | { | 115 | { |
108 | m5407_uarts_init(); | ||
109 | platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices)); | 116 | platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices)); |
110 | return 0; | 117 | return 0; |
111 | } | 118 | } |