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authorGreg Ungerer <gerg@snapgear.com>2008-02-01 02:37:36 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2008-02-01 04:58:10 -0500
commit703d01255e650b2f1ff6b2df5345bd481fd094e6 (patch)
tree7837de34ee0d45a06dd0783e74de918fc6d0bbcc /arch/m68knommu/platform/5307
parentad80335a989ddace0969b180d4c417b56f26a254 (diff)
m68knommu: move ColdFire pit.c to its own coldfire directory
Move common ColdFire CPU pit.c to common coldfire platform directory. Currently the common ColdFire CPU family code sits in the arch/m68knommu/platform/5307 directory. This is confusing, the files containing this common code are in no way specific to the 5307 ColdFire. Create an arch/m68knommu/platform/coldfire directory to contain this common code. Other m68knommu CPU varients do not need use this code though, so it doesn't make sense to move it to arch/m68knommu/kernel. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/m68knommu/platform/5307')
-rw-r--r--arch/m68knommu/platform/5307/pit.c97
1 files changed, 0 insertions, 97 deletions
diff --git a/arch/m68knommu/platform/5307/pit.c b/arch/m68knommu/platform/5307/pit.c
deleted file mode 100644
index 173b754d1cda..000000000000
--- a/arch/m68knommu/platform/5307/pit.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/***************************************************************************/
2
3/*
4 * pit.c -- Freescale ColdFire PIT timer. Currently this type of
5 * hardware timer only exists in the Freescale ColdFire
6 * 5270/5271, 5282 and other CPUs.
7 *
8 * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
9 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
10 */
11
12/***************************************************************************/
13
14#include <linux/kernel.h>
15#include <linux/sched.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <asm/machdep.h>
21#include <asm/io.h>
22#include <asm/coldfire.h>
23#include <asm/mcfpit.h>
24#include <asm/mcfsim.h>
25
26/***************************************************************************/
27
28/*
29 * By default use timer1 as the system clock timer.
30 */
31#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
32
33/***************************************************************************/
34
35static irqreturn_t hw_tick(int irq, void *dummy)
36{
37 unsigned short pcsr;
38
39 /* Reset the ColdFire timer */
40 pcsr = __raw_readw(TA(MCFPIT_PCSR));
41 __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
42
43 return arch_timer_interrupt(irq, dummy);
44}
45
46/***************************************************************************/
47
48static struct irqaction coldfire_pit_irq = {
49 .name = "timer",
50 .flags = IRQF_DISABLED | IRQF_TIMER,
51 .handler = hw_tick,
52};
53
54void hw_timer_init(void)
55{
56 volatile unsigned char *icrp;
57 volatile unsigned long *imrp;
58
59 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &coldfire_pit_irq);
60
61 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
62 MCFINTC_ICR0 + MCFINT_PIT1);
63 *icrp = ICR_INTRCONF;
64
65 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
66 *imrp &= ~MCFPIT_IMR_IBIT;
67
68 /* Set up PIT timer 1 as poll clock */
69 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
70 __raw_writew(((MCF_CLK / 2) / 64) / HZ, TA(MCFPIT_PMR));
71 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
72 MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
73}
74
75/***************************************************************************/
76
77unsigned long hw_timer_offset(void)
78{
79 volatile unsigned long *ipr;
80 unsigned long pmr, pcntr, offset;
81
82 ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
83
84 pmr = __raw_readw(TA(MCFPIT_PMR));
85 pcntr = __raw_readw(TA(MCFPIT_PCNTR));
86
87 /*
88 * If we are still in the first half of the upcount and a
89 * timer interrupt is pending, then add on a ticks worth of time.
90 */
91 offset = ((pmr - pcntr) * (1000000 / HZ)) / pmr;
92 if ((offset < (1000000 / HZ / 2)) && (*ipr & MCFPIT_IMR_IBIT))
93 offset += 1000000 / HZ;
94 return offset;
95}
96
97/***************************************************************************/