fec: add FEC platform support to ColdFire CPU's setup code

m68knommu: add FEC platform support to ColdFire CPU's setup code Move the per-CPU FEC driver setup code into the actual platform setup code for each ColdFire CPU varient. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: David S. Miller <davem@davemloft.net>
author: Greg Ungerer <gerg@uclinux.org> 2009-02-27 01:40:38 -0500
committer: David S. Miller <davem@davemloft.net> 2009-02-27 01:40:38 -0500
commit: ffba3f48bcd2d8af0570e7d4ce9b86fc4de9b10d (patch)
tree: d10a834586c8e66b496589aa55966368f9c08889 /arch/m68knommu/platform/527x
parent: 211174ea8dca4502e20008de7ff2ad389db023a5 (diff)
1 files changed, 112 insertions, 1 deletions
diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c
index 73cd1aef4a90..49343fb157b0 100644
--- a/arch/m68knommu/platform/527x/config.c
+++ b/arch/m68knommu/platform/527x/config.c
@@ -50,8 +50,73 @@ static struct platform_device m527x_uart = {
        .dev.platform_data      = m527x_uart_platform,
 };
+static struct resource m527x_fec0_resources[] = {
+        {
+                .start          = MCF_MBAR + 0x1000,
+                .end            = MCF_MBAR + 0x1000 + 0x7ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 64 + 23,
+                .end            = 64 + 23,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 27,
+                .end            = 64 + 27,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 29,
+                .end            = 64 + 29,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct resource m527x_fec1_resources[] = {
+        {
+                .start          = MCF_MBAR + 0x1800,
+                .end            = MCF_MBAR + 0x1800 + 0x7ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 128 + 23,
+                .end            = 128 + 23,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 128 + 27,
+                .end            = 128 + 27,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 128 + 29,
+                .end            = 128 + 29,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device m527x_fec[] = {
+        {
+                .name           = "fec",
+                .id             = 0,
+                .num_resources  = ARRAY_SIZE(m527x_fec0_resources),
+                .resource       = m527x_fec0_resources,
+        },
+        {
+                .name           = "fec",
+                .id             = 1,
+                .num_resources  = ARRAY_SIZE(m527x_fec1_resources),
+                .resource       = m527x_fec1_resources,
+        },
+};
 static struct platform_device *m527x_devices[] __initdata = {
        &m527x_uart,
+        &m527x_fec[0],
+#ifdef CONFIG_FEC2
+        &m527x_fec[1],
+#endif
 };
 /***************************************************************************/
@@ -97,6 +162,51 @@ static void __init m527x_uarts_init(void)
 /***************************************************************************/
+static void __init m527x_fec_irq_init(int nr)
+{
+        unsigned long base;
+        u32 imr;
+        base = MCF_IPSBAR + (nr ? MCFICM_INTC1 : MCFICM_INTC0);
+        writeb(0x28, base + MCFINTC_ICR0 + 23);
+        writeb(0x27, base + MCFINTC_ICR0 + 27);
+        writeb(0x26, base + MCFINTC_ICR0 + 29);
+        imr = readl(base + MCFINTC_IMRH);
+        imr &= ~0xf;
+        writel(imr, base + MCFINTC_IMRH);
+        imr = readl(base + MCFINTC_IMRL);
+        imr &= ~0xff800001;
+        writel(imr, base + MCFINTC_IMRL);
+}
+static void __init m527x_fec_init(void)
+{
+        u16 par;
+        u8 v;
+        m527x_fec_irq_init(0);
+        /* Set multi-function pins to ethernet mode for fec0 */
+        par = readw(MCF_IPSBAR + 0x100082);
+        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
+        v = readb(MCF_IPSBAR + 0x100078);
+        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+#ifdef CONFIG_FEC2
+        m527x_fec_irq_init(1);
+        /* Set multi-function pins to ethernet mode for fec1 */
+        par = readw(MCF_IPSBAR + 0x100082);
+        writew(par | 0xa0, MCF_IPSBAR + 0x100082);
+        v = readb(MCF_IPSBAR + 0x100079);
+        writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+#endif
+}
+/***************************************************************************/
 void mcf_disableall(void)
 {
        *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
@@ -116,13 +226,14 @@ void __init config_BSP(char *commandp, int size)
 {
        mcf_disableall();
        mach_reset = coldfire_reset;
+        m527x_uarts_init();
+        m527x_fec_init();
 }
 /***************************************************************************/
 static int __init init_BSP(void)
 {
-        m527x_uarts_init();
        platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
        return 0;
 }
author	Greg Ungerer <gerg@uclinux.org>	2009-02-27 01:40:38 -0500
committer	David S. Miller <davem@davemloft.net>	2009-02-27 01:40:38 -0500
commit	ffba3f48bcd2d8af0570e7d4ce9b86fc4de9b10d (patch)
tree	d10a834586c8e66b496589aa55966368f9c08889 /arch/m68knommu/platform/527x
parent	211174ea8dca4502e20008de7ff2ad389db023a5 (diff)

diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c index 73cd1aef4a90..49343fb157b0 100644 --- a/arch/m68knommu/platform/527x/config.c +++ b/arch/m68knommu/platform/527x/config.c
@@ -50,8 +50,73 @@ static struct platform_device m527x_uart = {
50	.dev.platform_data = m527x_uart_platform,	50	.dev.platform_data = m527x_uart_platform,
51	};	51	};
52		52
		53	static struct resource m527x_fec0_resources[] = {
		54	{
		55	.start = MCF_MBAR + 0x1000,
		56	.end = MCF_MBAR + 0x1000 + 0x7ff,
		57	.flags = IORESOURCE_MEM,
		58	},
		59	{
		60	.start = 64 + 23,
		61	.end = 64 + 23,
		62	.flags = IORESOURCE_IRQ,
		63	},
		64	{
		65	.start = 64 + 27,
		66	.end = 64 + 27,
		67	.flags = IORESOURCE_IRQ,
		68	},
		69	{
		70	.start = 64 + 29,
		71	.end = 64 + 29,
		72	.flags = IORESOURCE_IRQ,
		73	},
		74	};
		75
		76	static struct resource m527x_fec1_resources[] = {
		77	{
		78	.start = MCF_MBAR + 0x1800,
		79	.end = MCF_MBAR + 0x1800 + 0x7ff,
		80	.flags = IORESOURCE_MEM,
		81	},
		82	{
		83	.start = 128 + 23,
		84	.end = 128 + 23,
		85	.flags = IORESOURCE_IRQ,
		86	},
		87	{
		88	.start = 128 + 27,
		89	.end = 128 + 27,
		90	.flags = IORESOURCE_IRQ,
		91	},
		92	{
		93	.start = 128 + 29,
		94	.end = 128 + 29,
		95	.flags = IORESOURCE_IRQ,
		96	},
		97	};
		98
		99	static struct platform_device m527x_fec[] = {
		100	{
		101	.name = "fec",
		102	.id = 0,
		103	.num_resources = ARRAY_SIZE(m527x_fec0_resources),
		104	.resource = m527x_fec0_resources,
		105	},
		106	{
		107	.name = "fec",
		108	.id = 1,
		109	.num_resources = ARRAY_SIZE(m527x_fec1_resources),
		110	.resource = m527x_fec1_resources,
		111	},
		112	};
		113
53	static struct platform_device *m527x_devices[] __initdata = {	114	static struct platform_device *m527x_devices[] __initdata = {
54	&m527x_uart,	115	&m527x_uart,
		116	&m527x_fec[0],
		117	#ifdef CONFIG_FEC2
		118	&m527x_fec[1],
		119	#endif
55	};	120	};
56		121
57	/***************************************************************************/	122	/***************************************************************************/
@@ -97,6 +162,51 @@ static void __init m527x_uarts_init(void)
97		162
98	/***************************************************************************/	163	/***************************************************************************/
99		164
		165	static void __init m527x_fec_irq_init(int nr)
		166	{
		167	unsigned long base;
		168	u32 imr;
		169
		170	base = MCF_IPSBAR + (nr ? MCFICM_INTC1 : MCFICM_INTC0);
		171
		172	writeb(0x28, base + MCFINTC_ICR0 + 23);
		173	writeb(0x27, base + MCFINTC_ICR0 + 27);
		174	writeb(0x26, base + MCFINTC_ICR0 + 29);
		175
		176	imr = readl(base + MCFINTC_IMRH);
		177	imr &= ~0xf;
		178	writel(imr, base + MCFINTC_IMRH);
		179	imr = readl(base + MCFINTC_IMRL);
		180	imr &= ~0xff800001;
		181	writel(imr, base + MCFINTC_IMRL);
		182	}
		183
		184	static void __init m527x_fec_init(void)
		185	{
		186	u16 par;
		187	u8 v;
		188
		189	m527x_fec_irq_init(0);
		190
		191	/* Set multi-function pins to ethernet mode for fec0 */
		192	par = readw(MCF_IPSBAR + 0x100082);
		193	writew(par \| 0xf00, MCF_IPSBAR + 0x100082);
		194	v = readb(MCF_IPSBAR + 0x100078);
		195	writeb(v \| 0xc0, MCF_IPSBAR + 0x100078);
		196
		197	#ifdef CONFIG_FEC2
		198	m527x_fec_irq_init(1);
		199
		200	/* Set multi-function pins to ethernet mode for fec1 */
		201	par = readw(MCF_IPSBAR + 0x100082);
		202	writew(par \| 0xa0, MCF_IPSBAR + 0x100082);
		203	v = readb(MCF_IPSBAR + 0x100079);
		204	writeb(v \| 0xc0, MCF_IPSBAR + 0x100079);
		205	#endif
		206	}
		207
		208	/***************************************************************************/
		209
100	void mcf_disableall(void)	210	void mcf_disableall(void)
101	{	211	{
102	((volatile unsigned long ) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;	212	((volatile unsigned long ) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
@@ -116,13 +226,14 @@ void __init config_BSP(char *commandp, int size)
116	{	226	{
117	mcf_disableall();	227	mcf_disableall();
118	mach_reset = coldfire_reset;	228	mach_reset = coldfire_reset;
		229	m527x_uarts_init();
		230	m527x_fec_init();
119	}	231	}
120		232
121	/***************************************************************************/	233	/***************************************************************************/
122		234
123	static int __init init_BSP(void)	235	static int __init init_BSP(void)
124	{	236	{
125	m527x_uarts_init();
126	platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));	237	platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
127	return 0;	238	return 0;
128	}	239	}