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authorGreg Ungerer <gerg@uclinux.org>2011-03-21 23:39:27 -0400
committerGreg Ungerer <gerg@uclinux.org>2011-03-25 00:05:13 -0400
commit66d857b08b8c3ed5c72c361f863cce77d2a978d7 (patch)
tree47222d86f4d78dc0da31baf64188bd2e4b38ac1e /arch/m68knommu/platform/5249
parentd39dd11c3e6a7af5c20bfac40594db36cf270f42 (diff)
m68k: merge m68k and m68knommu arch directories
There is a lot of common code that could be shared between the m68k and m68knommu arch branches. It makes sense to merge the two branches into a single directory structure so that we can more easily share that common code. This is a brute force merge, based on a script from Stephen King <sfking@fdwdc.com>, which was originally written by Arnd Bergmann <arnd@arndb.de>. > The script was inspired by the script Sam Ravnborg used to merge the > includes from m68knommu. For those files common to both arches but > differing in content, the m68k version of the file is renamed to > <file>_mm.<ext> and the m68knommu version of the file is moved into the > corresponding m68k directory and renamed <file>_no.<ext> and a small > wrapper file <file>.<ext> is used to select between the two version. Files > that are common to both but don't differ are removed from the m68knommu > tree and files and directories that are unique to the m68knommu tree are > moved to the m68k tree. Finally, the arch/m68knommu tree is removed. > > To select between the the versions of the files, the wrapper uses > > #ifdef CONFIG_MMU > #include <file>_mm.<ext> > #else > #include <file>_no.<ext> > #endif On top of this file merge I have done a simplistic merge of m68k and m68knommu Kconfig, which primarily attempts to keep existing options and menus in place. Other than a handful of options being moved it produces identical .config outputs on m68k and m68knommu targets I tested it on. With this in place there is now quite a bit of scope for merge cleanups in future patches. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/5249')
-rw-r--r--arch/m68knommu/platform/5249/Makefile18
-rw-r--r--arch/m68knommu/platform/5249/config.c330
-rw-r--r--arch/m68knommu/platform/5249/gpio.c65
-rw-r--r--arch/m68knommu/platform/5249/intc2.c61
4 files changed, 0 insertions, 474 deletions
diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68knommu/platform/5249/Makefile
deleted file mode 100644
index 4bed30fd0073..000000000000
--- a/arch/m68knommu/platform/5249/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o intc2.o
18
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
deleted file mode 100644
index ceb31e5744a6..000000000000
--- a/arch/m68knommu/platform/5249/config.c
+++ /dev/null
@@ -1,330 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5249/config.c
5 *
6 * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/spi/spi.h>
16#include <linux/gpio.h>
17#include <asm/machdep.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/mcfuart.h>
21#include <asm/mcfqspi.h>
22
23/***************************************************************************/
24
25static struct mcf_platform_uart m5249_uart_platform[] = {
26 {
27 .mapbase = MCF_MBAR + MCFUART_BASE1,
28 .irq = 73,
29 },
30 {
31 .mapbase = MCF_MBAR + MCFUART_BASE2,
32 .irq = 74,
33 },
34 { },
35};
36
37static struct platform_device m5249_uart = {
38 .name = "mcfuart",
39 .id = 0,
40 .dev.platform_data = m5249_uart_platform,
41};
42
43#ifdef CONFIG_M5249C3
44
45static struct resource m5249_smc91x_resources[] = {
46 {
47 .start = 0xe0000300,
48 .end = 0xe0000300 + 0x100,
49 .flags = IORESOURCE_MEM,
50 },
51 {
52 .start = MCFINTC2_GPIOIRQ6,
53 .end = MCFINTC2_GPIOIRQ6,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct platform_device m5249_smc91x = {
59 .name = "smc91x",
60 .id = 0,
61 .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
62 .resource = m5249_smc91x_resources,
63};
64
65#endif /* CONFIG_M5249C3 */
66
67#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
68static struct resource m5249_qspi_resources[] = {
69 {
70 .start = MCFQSPI_IOBASE,
71 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .start = MCF_IRQ_QSPI,
76 .end = MCF_IRQ_QSPI,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81#define MCFQSPI_CS0 29
82#define MCFQSPI_CS1 24
83#define MCFQSPI_CS2 21
84#define MCFQSPI_CS3 22
85
86static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control)
87{
88 int status;
89
90 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
91 if (status) {
92 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
93 goto fail0;
94 }
95 status = gpio_direction_output(MCFQSPI_CS0, 1);
96 if (status) {
97 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
98 goto fail1;
99 }
100
101 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
102 if (status) {
103 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
104 goto fail1;
105 }
106 status = gpio_direction_output(MCFQSPI_CS1, 1);
107 if (status) {
108 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
109 goto fail2;
110 }
111
112 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
113 if (status) {
114 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
115 goto fail2;
116 }
117 status = gpio_direction_output(MCFQSPI_CS2, 1);
118 if (status) {
119 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
120 goto fail3;
121 }
122
123 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
124 if (status) {
125 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
126 goto fail3;
127 }
128 status = gpio_direction_output(MCFQSPI_CS3, 1);
129 if (status) {
130 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
131 goto fail4;
132 }
133
134 return 0;
135
136fail4:
137 gpio_free(MCFQSPI_CS3);
138fail3:
139 gpio_free(MCFQSPI_CS2);
140fail2:
141 gpio_free(MCFQSPI_CS1);
142fail1:
143 gpio_free(MCFQSPI_CS0);
144fail0:
145 return status;
146}
147
148static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control)
149{
150 gpio_free(MCFQSPI_CS3);
151 gpio_free(MCFQSPI_CS2);
152 gpio_free(MCFQSPI_CS1);
153 gpio_free(MCFQSPI_CS0);
154}
155
156static void m5249_cs_select(struct mcfqspi_cs_control *cs_control,
157 u8 chip_select, bool cs_high)
158{
159 switch (chip_select) {
160 case 0:
161 gpio_set_value(MCFQSPI_CS0, cs_high);
162 break;
163 case 1:
164 gpio_set_value(MCFQSPI_CS1, cs_high);
165 break;
166 case 2:
167 gpio_set_value(MCFQSPI_CS2, cs_high);
168 break;
169 case 3:
170 gpio_set_value(MCFQSPI_CS3, cs_high);
171 break;
172 }
173}
174
175static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control,
176 u8 chip_select, bool cs_high)
177{
178 switch (chip_select) {
179 case 0:
180 gpio_set_value(MCFQSPI_CS0, !cs_high);
181 break;
182 case 1:
183 gpio_set_value(MCFQSPI_CS1, !cs_high);
184 break;
185 case 2:
186 gpio_set_value(MCFQSPI_CS2, !cs_high);
187 break;
188 case 3:
189 gpio_set_value(MCFQSPI_CS3, !cs_high);
190 break;
191 }
192}
193
194static struct mcfqspi_cs_control m5249_cs_control = {
195 .setup = m5249_cs_setup,
196 .teardown = m5249_cs_teardown,
197 .select = m5249_cs_select,
198 .deselect = m5249_cs_deselect,
199};
200
201static struct mcfqspi_platform_data m5249_qspi_data = {
202 .bus_num = 0,
203 .num_chipselect = 4,
204 .cs_control = &m5249_cs_control,
205};
206
207static struct platform_device m5249_qspi = {
208 .name = "mcfqspi",
209 .id = 0,
210 .num_resources = ARRAY_SIZE(m5249_qspi_resources),
211 .resource = m5249_qspi_resources,
212 .dev.platform_data = &m5249_qspi_data,
213};
214
215static void __init m5249_qspi_init(void)
216{
217 /* QSPI irq setup */
218 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
219 MCF_MBAR + MCFSIM_QSPIICR);
220 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
221}
222#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
223
224
225static struct platform_device *m5249_devices[] __initdata = {
226 &m5249_uart,
227#ifdef CONFIG_M5249C3
228 &m5249_smc91x,
229#endif
230#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
231 &m5249_qspi,
232#endif
233};
234
235/***************************************************************************/
236
237static void __init m5249_uart_init_line(int line, int irq)
238{
239 if (line == 0) {
240 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
241 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
242 mcf_mapirq2imr(irq, MCFINTC_UART0);
243 } else if (line == 1) {
244 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
245 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
246 mcf_mapirq2imr(irq, MCFINTC_UART1);
247 }
248}
249
250static void __init m5249_uarts_init(void)
251{
252 const int nrlines = ARRAY_SIZE(m5249_uart_platform);
253 int line;
254
255 for (line = 0; (line < nrlines); line++)
256 m5249_uart_init_line(line, m5249_uart_platform[line].irq);
257}
258
259/***************************************************************************/
260
261#ifdef CONFIG_M5249C3
262
263static void __init m5249_smc91x_init(void)
264{
265 u32 gpio;
266
267 /* Set the GPIO line as interrupt source for smc91x device */
268 gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
269 writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
270
271 gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
272 writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
273}
274
275#endif /* CONFIG_M5249C3 */
276
277/***************************************************************************/
278
279static void __init m5249_timers_init(void)
280{
281 /* Timer1 is always used as system timer */
282 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
283 MCF_MBAR + MCFSIM_TIMER1ICR);
284 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
285
286#ifdef CONFIG_HIGHPROFILE
287 /* Timer2 is to be used as a high speed profile timer */
288 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
289 MCF_MBAR + MCFSIM_TIMER2ICR);
290 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
291#endif
292}
293
294/***************************************************************************/
295
296void m5249_cpu_reset(void)
297{
298 local_irq_disable();
299 /* Set watchdog to soft reset, and enabled */
300 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
301 for (;;)
302 /* wait for watchdog to timeout */;
303}
304
305/***************************************************************************/
306
307void __init config_BSP(char *commandp, int size)
308{
309 mach_reset = m5249_cpu_reset;
310 m5249_timers_init();
311 m5249_uarts_init();
312#ifdef CONFIG_M5249C3
313 m5249_smc91x_init();
314#endif
315#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
316 m5249_qspi_init();
317#endif
318}
319
320/***************************************************************************/
321
322static int __init init_BSP(void)
323{
324 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
325 return 0;
326}
327
328arch_initcall(init_BSP);
329
330/***************************************************************************/
diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c
deleted file mode 100644
index 2b56c6ef65bf..000000000000
--- a/arch/m68knommu/platform/5249/gpio.c
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "GPIO0",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 32,
34 },
35 .pddr = (void __iomem *) MCFSIM2_GPIOENABLE,
36 .podr = (void __iomem *) MCFSIM2_GPIOWRITE,
37 .ppdr = (void __iomem *) MCFSIM2_GPIOREAD,
38 },
39 {
40 .gpio_chip = {
41 .label = "GPIO1",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 32,
49 .ngpio = 32,
50 },
51 .pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE,
52 .podr = (void __iomem *) MCFSIM2_GPIO1WRITE,
53 .ppdr = (void __iomem *) MCFSIM2_GPIO1READ,
54 },
55};
56
57static int __init mcf_gpio_init(void)
58{
59 unsigned i = 0;
60 while (i < ARRAY_SIZE(mcf_gpio_chips))
61 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
62 return 0;
63}
64
65core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68knommu/platform/5249/intc2.c
deleted file mode 100644
index 8f4b63e17366..000000000000
--- a/arch/m68knommu/platform/5249/intc2.c
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 5249
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19
20static void intc2_irq_gpio_mask(struct irq_data *d)
21{
22 u32 imr;
23 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
25 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
26}
27
28static void intc2_irq_gpio_unmask(struct irq_data *d)
29{
30 u32 imr;
31 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
33 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
34}
35
36static void intc2_irq_gpio_ack(struct irq_data *d)
37{
38 writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
39}
40
41static struct irq_chip intc2_irq_gpio_chip = {
42 .name = "CF-INTC2",
43 .irq_mask = intc2_irq_gpio_mask,
44 .irq_unmask = intc2_irq_gpio_unmask,
45 .irq_ack = intc2_irq_gpio_ack,
46};
47
48static int __init mcf_intc2_init(void)
49{
50 int irq;
51
52 /* GPIO interrupt sources */
53 for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
54 set_irq_chip(irq, &intc2_irq_gpio_chip);
55 set_irq_handler(irq, handle_edge_irq);
56 }
57
58 return 0;
59}
60
61arch_initcall(mcf_intc2_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 22:39:29 -0500