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authorGreg Ungerer <gerg@uclinux.org>2009-05-21 23:33:35 -0400
committerGreg Ungerer <gerg@uclinux.org>2009-09-15 19:43:52 -0400
commit39f0fb6a3448cfc316e0d5295ed1b121db50037e (patch)
tree657db8073835e8d499708a898a36f1d3a1e39a32 /arch/m68knommu/platform/5249
parentf6a66276f5fdc018d2a9378c71de3bae13c588d7 (diff)
m68knommu: map ColdFire interrupts to correct masking bits
The older simple ColdFire interrupt controller has no one-to-one mapping of interrupt numbers to bits in the interrupt mask register. Create a mapping array that each ColdFire CPU type can populate with its available interrupts and the bits that each use in the interrupt mask register. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/5249')
-rw-r--r--arch/m68knommu/platform/5249/config.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 51202b1096cc..646f5ba462fc 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -48,11 +48,11 @@ static void __init m5249_uart_init_line(int line, int irq)
48 if (line == 0) { 48 if (line == 0) {
49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
51 mcf_clrimr(MCFINTC_UART0); 51 mcf_mapirq2imr(irq, MCFINTC_UART0);
52 } else if (line == 1) { 52 } else if (line == 1) {
53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
55 mcf_clrimr(MCFINTC_UART1); 55 mcf_mapirq2imr(irq, MCFINTC_UART1);
56 } 56 }
57} 57}
58 58
@@ -72,11 +72,13 @@ static void __init m5249_timers_init(void)
72 /* Timer1 is always used as system timer */ 72 /* Timer1 is always used as system timer */
73 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, 73 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
74 MCF_MBAR + MCFSIM_TIMER1ICR); 74 MCF_MBAR + MCFSIM_TIMER1ICR);
75 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
75 76
76#ifdef CONFIG_HIGHPROFILE 77#ifdef CONFIG_HIGHPROFILE
77 /* Timer2 is to be used as a high speed profile timer */ 78 /* Timer2 is to be used as a high speed profile timer */
78 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, 79 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
79 MCF_MBAR + MCFSIM_TIMER2ICR); 80 MCF_MBAR + MCFSIM_TIMER2ICR);
81 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
80#endif 82#endif
81} 83}
82 84
@@ -97,13 +99,13 @@ void __init config_BSP(char *commandp, int size)
97{ 99{
98 mach_reset = m5249_cpu_reset; 100 mach_reset = m5249_cpu_reset;
99 m5249_timers_init(); 101 m5249_timers_init();
102 m5249_uarts_init();
100} 103}
101 104
102/***************************************************************************/ 105/***************************************************************************/
103 106
104static int __init init_BSP(void) 107static int __init init_BSP(void)
105{ 108{
106 m5249_uarts_init();
107 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); 109 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
108 return 0; 110 return 0;
109} 111}