m68knommu: merge old ColdFire interrupt controller masking macros

Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 5 insertions, 6 deletions

diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 365fb6c52700..7261a3d28adc 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -48,11 +48,11 @@ static void __init m5249_uart_init_line(int line, int irq)
         if (line == 0) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
+                mcf_clrimr(MCFINTC_UART0);
         } else if (line == 1) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
+                mcf_clrimr(MCFINTC_UART1);
         }
 }
 
@@ -75,13 +75,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
 
         if (timer <= 2) {
                 switch (timer) {
-                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
-                default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
+                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
+                default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
                 }
 
                 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
                 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
-                mcf_setimr(mcf_getimr() & ~imr);
+                mcf_clrimr(imr);
         }
 }
 
@@ -100,7 +100,6 @@ void m5249_cpu_reset(void)
 
 void __init config_BSP(char *commandp, int size)
 {
-        mcf_setimr(MCFSIM_IMR_MASKALL);
         mach_reset = m5249_cpu_reset;
 }