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authorGreg Ungerer <gerg@uclinux.org>2009-05-19 00:38:08 -0400
committerGreg Ungerer <gerg@uclinux.org>2009-09-15 19:43:50 -0400
commitf2154bef817ac3d0ea67b52526fd8e88898b66f9 (patch)
tree3ffa5cf5c3ec82a59f75728a580bd9332a32ebee /arch/m68knommu/platform/5206e
parent5187995f0a9253e915dfee83684eae7b692213e6 (diff)
m68knommu: merge old ColdFire interrupt controller masking macros
Currently the code that supports setting the old style ColdFire interrupt controller mask registers is macros in the include files of each of the CPU types. Merge all these into a set of real masking functions in the old Coldfire interrupt controller code proper. All the macros are basically the same (excepting a register size difference on really early parts). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/5206e')
-rw-r--r--arch/m68knommu/platform/5206e/config.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 29e565a44431..08ef7e268989 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -50,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq)
50 if (line == 0) { 50 if (line == 0) {
51 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 51 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
52 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 52 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
53 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 53 mcf_clrimr(MCFINTC_UART0);
54 } else if (line == 1) { 54 } else if (line == 1) {
55 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 55 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
56 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 56 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
57 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 57 mcf_clrimr(MCFINTC_UART1);
58 } 58 }
59} 59}
60 60
@@ -76,13 +76,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
76 76
77 if (timer <= 2) { 77 if (timer <= 2) {
78 switch (timer) { 78 switch (timer) {
79 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 79 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
80 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 80 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
81 } 81 }
82 82
83 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 83 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
84 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 84 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
85 mcf_setimr(mcf_getimr() & ~imr); 85 mcf_clrimr(imr);
86 } 86 }
87} 87}
88 88
@@ -101,8 +101,6 @@ void m5206e_cpu_reset(void)
101 101
102void __init config_BSP(char *commandp, int size) 102void __init config_BSP(char *commandp, int size)
103{ 103{
104 mcf_setimr(MCFSIM_IMR_MASKALL);
105
106#if defined(CONFIG_NETtel) 104#if defined(CONFIG_NETtel)
107 /* Copy command line from FLASH to local buffer... */ 105 /* Copy command line from FLASH to local buffer... */
108 memcpy(commandp, (char *) 0xf0004000, size); 106 memcpy(commandp, (char *) 0xf0004000, size);