m68knommu: map ColdFire interrupts to correct masking bits

The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 10 insertions, 3 deletions

diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 363296af2ee5..0f41ba82a3b5 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -50,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq)
         if (line == 0) {
                 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
                 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_clrimr(MCFINTC_UART0);
+                mcf_mapirq2imr(irq, MCFINTC_UART0);
         } else if (line == 1) {
                 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
                 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_clrimr(MCFINTC_UART1);
+                mcf_mapirq2imr(irq, MCFINTC_UART1);
         }
 }
 
@@ -74,11 +74,13 @@ static void __init m5206e_timers_init(void)
         /* Timer1 is always used as system timer */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
                 MCF_MBAR + MCFSIM_TIMER1ICR);
+        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
 
 #ifdef CONFIG_HIGHPROFILE
         /* Timer2 is to be used as a high speed profile timer  */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
                 MCF_MBAR + MCFSIM_TIMER2ICR);
+        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
 #endif
 }
 
@@ -105,13 +107,18 @@ void __init config_BSP(char *commandp, int size)
 
         mach_reset = m5206e_cpu_reset;
         m5206e_timers_init();
+        m5206e_uarts_init();
+
+        /* Only support the external interrupts on their primary level */
+        mcf_mapirq2imr(25, MCFINTC_EINT1);
+        mcf_mapirq2imr(28, MCFINTC_EINT4);
+        mcf_mapirq2imr(31, MCFINTC_EINT7);
 }
 
 /***************************************************************************/
 
 static int __init init_BSP(void)
 {
-        m5206e_uarts_init();
         platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices));
         return 0;
 }