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authorGreg Ungerer <gerg@uclinux.org>2008-07-31 00:38:07 -0400
committerGreg Ungerer <gerg@uclinux.org>2008-08-07 01:36:16 -0400
commit58750139001bae11a1f9b074f3a9c774fecf5ba8 (patch)
treeecdafd4d8c3d2ef2cee7e512b7310552863a617c /arch/m68knommu/include
parent685d87f7ccc649ab92b55e18e507a65d0e694eb9 (diff)
Move all of include/asm-m68knommu to arch/m68knommu/include/asm.
With the current kbuild infrastructure in place no other changes are required for this to work. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/include')
-rw-r--r--arch/m68knommu/include/asm/Kbuild1
-rw-r--r--arch/m68knommu/include/asm/MC68328.h1266
-rw-r--r--arch/m68knommu/include/asm/MC68332.h152
-rw-r--r--arch/m68knommu/include/asm/MC68EZ328.h1253
-rw-r--r--arch/m68knommu/include/asm/MC68VZ328.h1349
-rw-r--r--arch/m68knommu/include/asm/a.out.h1
-rw-r--r--arch/m68knommu/include/asm/anchor.h112
-rw-r--r--arch/m68knommu/include/asm/atomic.h155
-rw-r--r--arch/m68knommu/include/asm/auxvec.h4
-rw-r--r--arch/m68knommu/include/asm/bitops.h336
-rw-r--r--arch/m68knommu/include/asm/bootinfo.h2
-rw-r--r--arch/m68knommu/include/asm/bootstd.h132
-rw-r--r--arch/m68knommu/include/asm/bug.h4
-rw-r--r--arch/m68knommu/include/asm/bugs.h16
-rw-r--r--arch/m68knommu/include/asm/byteorder.h27
-rw-r--r--arch/m68knommu/include/asm/cache.h12
-rw-r--r--arch/m68knommu/include/asm/cachectl.h1
-rw-r--r--arch/m68knommu/include/asm/cacheflush.h84
-rw-r--r--arch/m68knommu/include/asm/checksum.h132
-rw-r--r--arch/m68knommu/include/asm/coldfire.h51
-rw-r--r--arch/m68knommu/include/asm/commproc.h703
-rw-r--r--arch/m68knommu/include/asm/cputime.h6
-rw-r--r--arch/m68knommu/include/asm/current.h24
-rw-r--r--arch/m68knommu/include/asm/dbg.h6
-rw-r--r--arch/m68knommu/include/asm/delay.h76
-rw-r--r--arch/m68knommu/include/asm/device.h7
-rw-r--r--arch/m68knommu/include/asm/div64.h1
-rw-r--r--arch/m68knommu/include/asm/dma-mapping.h10
-rw-r--r--arch/m68knommu/include/asm/dma.h494
-rw-r--r--arch/m68knommu/include/asm/elf.h110
-rw-r--r--arch/m68knommu/include/asm/elia.h41
-rw-r--r--arch/m68knommu/include/asm/emergency-restart.h6
-rw-r--r--arch/m68knommu/include/asm/entry.h182
-rw-r--r--arch/m68knommu/include/asm/errno.h1
-rw-r--r--arch/m68knommu/include/asm/fb.h12
-rw-r--r--arch/m68knommu/include/asm/fcntl.h1
-rw-r--r--arch/m68knommu/include/asm/flat.h17
-rw-r--r--arch/m68knommu/include/asm/fpu.h21
-rw-r--r--arch/m68knommu/include/asm/futex.h6
-rw-r--r--arch/m68knommu/include/asm/hardirq.h27
-rw-r--r--arch/m68knommu/include/asm/hw_irq.h4
-rw-r--r--arch/m68knommu/include/asm/hwtest.h1
-rw-r--r--arch/m68knommu/include/asm/io.h194
-rw-r--r--arch/m68knommu/include/asm/ioctl.h1
-rw-r--r--arch/m68knommu/include/asm/ioctls.h1
-rw-r--r--arch/m68knommu/include/asm/ipcbuf.h1
-rw-r--r--arch/m68knommu/include/asm/irq.h26
-rw-r--r--arch/m68knommu/include/asm/irq_regs.h1
-rw-r--r--arch/m68knommu/include/asm/kdebug.h1
-rw-r--r--arch/m68knommu/include/asm/kmap_types.h21
-rw-r--r--arch/m68knommu/include/asm/linkage.h1
-rw-r--r--arch/m68knommu/include/asm/local.h6
-rw-r--r--arch/m68knommu/include/asm/m5206sim.h131
-rw-r--r--arch/m68knommu/include/asm/m520xsim.h63
-rw-r--r--arch/m68knommu/include/asm/m523xsim.h45
-rw-r--r--arch/m68knommu/include/asm/m5249sim.h209
-rw-r--r--arch/m68knommu/include/asm/m5272sim.h78
-rw-r--r--arch/m68knommu/include/asm/m527xsim.h74
-rw-r--r--arch/m68knommu/include/asm/m528xsim.h159
-rw-r--r--arch/m68knommu/include/asm/m5307sim.h181
-rw-r--r--arch/m68knommu/include/asm/m532xsim.h2238
-rw-r--r--arch/m68knommu/include/asm/m5407sim.h157
-rw-r--r--arch/m68knommu/include/asm/m68360.h13
-rw-r--r--arch/m68knommu/include/asm/m68360_enet.h177
-rw-r--r--arch/m68knommu/include/asm/m68360_pram.h431
-rw-r--r--arch/m68knommu/include/asm/m68360_quicc.h362
-rw-r--r--arch/m68knommu/include/asm/m68360_regs.h408
-rw-r--r--arch/m68knommu/include/asm/machdep.h26
-rw-r--r--arch/m68knommu/include/asm/math-emu.h1
-rw-r--r--arch/m68knommu/include/asm/mc146818rtc.h9
-rw-r--r--arch/m68knommu/include/asm/mcfcache.h150
-rw-r--r--arch/m68knommu/include/asm/mcfdma.h144
-rw-r--r--arch/m68knommu/include/asm/mcfmbus.h77
-rw-r--r--arch/m68knommu/include/asm/mcfne.h325
-rw-r--r--arch/m68knommu/include/asm/mcfpci.h119
-rw-r--r--arch/m68knommu/include/asm/mcfpit.h64
-rw-r--r--arch/m68knommu/include/asm/mcfsim.h126
-rw-r--r--arch/m68knommu/include/asm/mcfsmc.h187
-rw-r--r--arch/m68knommu/include/asm/mcftimer.h80
-rw-r--r--arch/m68knommu/include/asm/mcfuart.h216
-rw-r--r--arch/m68knommu/include/asm/mcfwdebug.h118
-rw-r--r--arch/m68knommu/include/asm/md.h1
-rw-r--r--arch/m68knommu/include/asm/mman.h1
-rw-r--r--arch/m68knommu/include/asm/mmu.h11
-rw-r--r--arch/m68knommu/include/asm/mmu_context.h33
-rw-r--r--arch/m68knommu/include/asm/module.h11
-rw-r--r--arch/m68knommu/include/asm/movs.h1
-rw-r--r--arch/m68knommu/include/asm/msgbuf.h1
-rw-r--r--arch/m68knommu/include/asm/mutex.h9
-rw-r--r--arch/m68knommu/include/asm/nettel.h108
-rw-r--r--arch/m68knommu/include/asm/openprom.h1
-rw-r--r--arch/m68knommu/include/asm/oplib.h1
-rw-r--r--arch/m68knommu/include/asm/page.h77
-rw-r--r--arch/m68knommu/include/asm/page_offset.h5
-rw-r--r--arch/m68knommu/include/asm/param.h22
-rw-r--r--arch/m68knommu/include/asm/pci.h29
-rw-r--r--arch/m68knommu/include/asm/percpu.h6
-rw-r--r--arch/m68knommu/include/asm/pgalloc.h8
-rw-r--r--arch/m68knommu/include/asm/pgtable.h70
-rw-r--r--arch/m68knommu/include/asm/poll.h1
-rw-r--r--arch/m68knommu/include/asm/posix_types.h1
-rw-r--r--arch/m68knommu/include/asm/processor.h143
-rw-r--r--arch/m68knommu/include/asm/ptrace.h87
-rw-r--r--arch/m68knommu/include/asm/quicc_simple.h52
-rw-r--r--arch/m68knommu/include/asm/resource.h1
-rw-r--r--arch/m68knommu/include/asm/rtc.h1
-rw-r--r--arch/m68knommu/include/asm/scatterlist.h22
-rw-r--r--arch/m68knommu/include/asm/sections.h7
-rw-r--r--arch/m68knommu/include/asm/segment.h51
-rw-r--r--arch/m68knommu/include/asm/sembuf.h1
-rw-r--r--arch/m68knommu/include/asm/setup.h10
-rw-r--r--arch/m68knommu/include/asm/shm.h1
-rw-r--r--arch/m68knommu/include/asm/shmbuf.h1
-rw-r--r--arch/m68knommu/include/asm/shmparam.h1
-rw-r--r--arch/m68knommu/include/asm/sigcontext.h17
-rw-r--r--arch/m68knommu/include/asm/siginfo.h6
-rw-r--r--arch/m68knommu/include/asm/signal.h159
-rw-r--r--arch/m68knommu/include/asm/smp.h1
-rw-r--r--arch/m68knommu/include/asm/socket.h1
-rw-r--r--arch/m68knommu/include/asm/sockios.h1
-rw-r--r--arch/m68knommu/include/asm/spinlock.h1
-rw-r--r--arch/m68knommu/include/asm/stat.h1
-rw-r--r--arch/m68knommu/include/asm/statfs.h1
-rw-r--r--arch/m68knommu/include/asm/string.h126
-rw-r--r--arch/m68knommu/include/asm/system.h324
-rw-r--r--arch/m68knommu/include/asm/termbits.h1
-rw-r--r--arch/m68knommu/include/asm/termios.h1
-rw-r--r--arch/m68knommu/include/asm/thread_info.h98
-rw-r--r--arch/m68knommu/include/asm/timex.h23
-rw-r--r--arch/m68knommu/include/asm/tlb.h1
-rw-r--r--arch/m68knommu/include/asm/tlbflush.h55
-rw-r--r--arch/m68knommu/include/asm/topology.h6
-rw-r--r--arch/m68knommu/include/asm/traps.h154
-rw-r--r--arch/m68knommu/include/asm/types.h1
-rw-r--r--arch/m68knommu/include/asm/uaccess.h181
-rw-r--r--arch/m68knommu/include/asm/ucontext.h32
-rw-r--r--arch/m68knommu/include/asm/unaligned.h25
-rw-r--r--arch/m68knommu/include/asm/unistd.h366
-rw-r--r--arch/m68knommu/include/asm/user.h1
139 files changed, 15825 insertions, 0 deletions
diff --git a/arch/m68knommu/include/asm/Kbuild b/arch/m68knommu/include/asm/Kbuild
new file mode 100644
index 000000000000..c68e1680da01
--- /dev/null
+++ b/arch/m68knommu/include/asm/Kbuild
@@ -0,0 +1 @@
include include/asm-generic/Kbuild.asm
diff --git a/arch/m68knommu/include/asm/MC68328.h b/arch/m68knommu/include/asm/MC68328.h
new file mode 100644
index 000000000000..a337e56d09bf
--- /dev/null
+++ b/arch/m68knommu/include/asm/MC68328.h
@@ -0,0 +1,1266 @@
1
2/* include/asm-m68knommu/MC68328.h: '328 control registers
3 *
4 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
5 * Bear & Hare Software, Inc.
6 *
7 * Based on include/asm-m68knommu/MC68332.h
8 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
9 *
10 */
11
12#ifndef _MC68328_H_
13#define _MC68328_H_
14
15#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
16#define WORD_REF(addr) (*((volatile unsigned short*)addr))
17#define LONG_REF(addr) (*((volatile unsigned long*)addr))
18
19#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
20#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
21
22/**********
23 *
24 * 0xFFFFF0xx -- System Control
25 *
26 **********/
27
28/*
29 * System Control Register (SCR)
30 */
31#define SCR_ADDR 0xfffff000
32#define SCR BYTE_REF(SCR_ADDR)
33
34#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
35#define SCR_DMAP 0x04 /* Double Map */
36#define SCR_SO 0x08 /* Supervisor Only */
37#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
38#define SCR_PRV 0x20 /* Privilege Violation */
39#define SCR_WPV 0x40 /* Write Protect Violation */
40#define SCR_BETO 0x80 /* Bus-Error TimeOut */
41
42/*
43 * Mask Revision Register
44 */
45#define MRR_ADDR 0xfffff004
46#define MRR LONG_REF(MRR_ADDR)
47
48/**********
49 *
50 * 0xFFFFF1xx -- Chip-Select logic
51 *
52 **********/
53
54/**********
55 *
56 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
57 *
58 **********/
59
60/*
61 * Group Base Address Registers
62 */
63#define GRPBASEA_ADDR 0xfffff100
64#define GRPBASEB_ADDR 0xfffff102
65#define GRPBASEC_ADDR 0xfffff104
66#define GRPBASED_ADDR 0xfffff106
67
68#define GRPBASEA WORD_REF(GRPBASEA_ADDR)
69#define GRPBASEB WORD_REF(GRPBASEB_ADDR)
70#define GRPBASEC WORD_REF(GRPBASEC_ADDR)
71#define GRPBASED WORD_REF(GRPBASED_ADDR)
72
73#define GRPBASE_V 0x0001 /* Valid */
74#define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
75
76/*
77 * Group Base Address Mask Registers
78 */
79#define GRPMASKA_ADDR 0xfffff108
80#define GRPMASKB_ADDR 0xfffff10a
81#define GRPMASKC_ADDR 0xfffff10c
82#define GRPMASKD_ADDR 0xfffff10e
83
84#define GRPMASKA WORD_REF(GRPMASKA_ADDR)
85#define GRPMASKB WORD_REF(GRPMASKB_ADDR)
86#define GRPMASKC WORD_REF(GRPMASKC_ADDR)
87#define GRPMASKD WORD_REF(GRPMASKD_ADDR)
88
89#define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
90
91/*
92 * Chip-Select Option Registers (group A)
93 */
94#define CSA0_ADDR 0xfffff110
95#define CSA1_ADDR 0xfffff114
96#define CSA2_ADDR 0xfffff118
97#define CSA3_ADDR 0xfffff11c
98
99#define CSA0 LONG_REF(CSA0_ADDR)
100#define CSA1 LONG_REF(CSA1_ADDR)
101#define CSA2 LONG_REF(CSA2_ADDR)
102#define CSA3 LONG_REF(CSA3_ADDR)
103
104#define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */
105#define CSA_WAIT_SHIFT 0
106#define CSA_RO 0x00000008 /* Read-Only */
107#define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
108#define CSA_AM_SHIFT 8
109#define CSA_BUSW 0x00010000 /* Bus Width Select */
110#define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
111#define CSA_AC_SHIFT 24
112
113/*
114 * Chip-Select Option Registers (group B)
115 */
116#define CSB0_ADDR 0xfffff120
117#define CSB1_ADDR 0xfffff124
118#define CSB2_ADDR 0xfffff128
119#define CSB3_ADDR 0xfffff12c
120
121#define CSB0 LONG_REF(CSB0_ADDR)
122#define CSB1 LONG_REF(CSB1_ADDR)
123#define CSB2 LONG_REF(CSB2_ADDR)
124#define CSB3 LONG_REF(CSB3_ADDR)
125
126#define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */
127#define CSB_WAIT_SHIFT 0
128#define CSB_RO 0x00000008 /* Read-Only */
129#define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
130#define CSB_AM_SHIFT 8
131#define CSB_BUSW 0x00010000 /* Bus Width Select */
132#define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
133#define CSB_AC_SHIFT 24
134
135/*
136 * Chip-Select Option Registers (group C)
137 */
138#define CSC0_ADDR 0xfffff130
139#define CSC1_ADDR 0xfffff134
140#define CSC2_ADDR 0xfffff138
141#define CSC3_ADDR 0xfffff13c
142
143#define CSC0 LONG_REF(CSC0_ADDR)
144#define CSC1 LONG_REF(CSC1_ADDR)
145#define CSC2 LONG_REF(CSC2_ADDR)
146#define CSC3 LONG_REF(CSC3_ADDR)
147
148#define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */
149#define CSC_WAIT_SHIFT 0
150#define CSC_RO 0x00000008 /* Read-Only */
151#define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
152#define CSC_AM_SHIFT 4
153#define CSC_BUSW 0x00010000 /* Bus Width Select */
154#define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
155#define CSC_AC_SHIFT 20
156
157/*
158 * Chip-Select Option Registers (group D)
159 */
160#define CSD0_ADDR 0xfffff140
161#define CSD1_ADDR 0xfffff144
162#define CSD2_ADDR 0xfffff148
163#define CSD3_ADDR 0xfffff14c
164
165#define CSD0 LONG_REF(CSD0_ADDR)
166#define CSD1 LONG_REF(CSD1_ADDR)
167#define CSD2 LONG_REF(CSD2_ADDR)
168#define CSD3 LONG_REF(CSD3_ADDR)
169
170#define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */
171#define CSD_WAIT_SHIFT 0
172#define CSD_RO 0x00000008 /* Read-Only */
173#define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
174#define CSD_AM_SHIFT 4
175#define CSD_BUSW 0x00010000 /* Bus Width Select */
176#define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
177#define CSD_AC_SHIFT 20
178
179/**********
180 *
181 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
182 *
183 **********/
184
185/*
186 * PLL Control Register
187 */
188#define PLLCR_ADDR 0xfffff200
189#define PLLCR WORD_REF(PLLCR_ADDR)
190
191#define PLLCR_DISPLL 0x0008 /* Disable PLL */
192#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
193#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
194#define PLLCR_SYSCLK_SEL_SHIFT 8
195#define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
196#define PLLCR_PIXCLK_SEL_SHIFT 11
197
198/* 'EZ328-compatible definitions */
199#define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK
200#define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT
201
202/*
203 * PLL Frequency Select Register
204 */
205#define PLLFSR_ADDR 0xfffff202
206#define PLLFSR WORD_REF(PLLFSR_ADDR)
207
208#define PLLFSR_PC_MASK 0x00ff /* P Count */
209#define PLLFSR_PC_SHIFT 0
210#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
211#define PLLFSR_QC_SHIFT 8
212#define PLLFSR_PROT 0x4000 /* Protect P & Q */
213#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
214
215/*
216 * Power Control Register
217 */
218#define PCTRL_ADDR 0xfffff207
219#define PCTRL BYTE_REF(PCTRL_ADDR)
220
221#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
222#define PCTRL_WIDTH_SHIFT 0
223#define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
224#define PCTRL_PCEN 0x80 /* Power Control Enable */
225
226/**********
227 *
228 * 0xFFFFF3xx -- Interrupt Controller
229 *
230 **********/
231
232/*
233 * Interrupt Vector Register
234 */
235#define IVR_ADDR 0xfffff300
236#define IVR BYTE_REF(IVR_ADDR)
237
238#define IVR_VECTOR_MASK 0xF8
239
240/*
241 * Interrupt control Register
242 */
243#define ICR_ADRR 0xfffff302
244#define ICR WORD_REF(ICR_ADDR)
245
246#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
247#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
248#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
249#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
250#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
251#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
252#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
253#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
254
255/*
256 * Interrupt Mask Register
257 */
258#define IMR_ADDR 0xfffff304
259#define IMR LONG_REF(IMR_ADDR)
260
261/*
262 * Define the names for bit positions first. This is useful for
263 * request_irq
264 */
265#define SPIM_IRQ_NUM 0 /* SPI Master interrupt */
266#define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */
267#define UART_IRQ_NUM 2 /* UART interrupt */
268#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
269#define RTC_IRQ_NUM 4 /* RTC interrupt */
270#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
271#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
272#define INT0_IRQ_NUM 8 /* External INT0 */
273#define INT1_IRQ_NUM 9 /* External INT1 */
274#define INT2_IRQ_NUM 10 /* External INT2 */
275#define INT3_IRQ_NUM 11 /* External INT3 */
276#define INT4_IRQ_NUM 12 /* External INT4 */
277#define INT5_IRQ_NUM 13 /* External INT5 */
278#define INT6_IRQ_NUM 14 /* External INT6 */
279#define INT7_IRQ_NUM 15 /* External INT7 */
280#define IRQ1_IRQ_NUM 16 /* IRQ1 */
281#define IRQ2_IRQ_NUM 17 /* IRQ2 */
282#define IRQ3_IRQ_NUM 18 /* IRQ3 */
283#define IRQ6_IRQ_NUM 19 /* IRQ6 */
284#define PEN_IRQ_NUM 20 /* Pen Interrupt */
285#define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */
286#define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */
287#define IRQ7_IRQ_NUM 23 /* IRQ7 */
288
289/* '328-compatible definitions */
290#define SPI_IRQ_NUM SPIM_IRQ_NUM
291#define TMR_IRQ_NUM TMR1_IRQ_NUM
292
293/*
294 * Here go the bitmasks themselves
295 */
296#define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */
297#define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
298#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
299#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
300#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
301#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
302#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
303#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
304#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
305#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
306#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
307#define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */
308#define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */
309#define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */
310#define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */
311#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
312#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
313#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
314#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
315#define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
316#define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
317#define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
318#define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
319
320/* 'EZ328-compatible definitions */
321#define IMR_MSPI IMR_MSPIM
322#define IMR_MTMR IMR_MTMR1
323
324/*
325 * Interrupt Wake-Up Enable Register
326 */
327#define IWR_ADDR 0xfffff308
328#define IWR LONG_REF(IWR_ADDR)
329
330#define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
331#define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
332#define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
333#define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
334#define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
335#define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
336#define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
337#define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
338#define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
339#define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
340#define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
341#define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
342#define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
343#define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
344#define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
345#define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
346#define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
347#define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
348#define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
349#define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
350#define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
351#define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
352#define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
353
354/*
355 * Interrupt Status Register
356 */
357#define ISR_ADDR 0xfffff30c
358#define ISR LONG_REF(ISR_ADDR)
359
360#define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
361#define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
362#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
363#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
364#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
365#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
366#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
367#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
368#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
369#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
370#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
371#define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
372#define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
373#define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
374#define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
375#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
376#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
377#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
378#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
379#define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
380#define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
381#define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
382#define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
383
384/* 'EZ328-compatible definitions */
385#define ISR_SPI ISR_SPIM
386#define ISR_TMR ISR_TMR1
387
388/*
389 * Interrupt Pending Register
390 */
391#define IPR_ADDR 0xfffff310
392#define IPR LONG_REF(IPR_ADDR)
393
394#define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
395#define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
396#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
397#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
398#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
399#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
400#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
401#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
402#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
403#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
404#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
405#define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
406#define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
407#define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
408#define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
409#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
410#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
411#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
412#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
413#define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
414#define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
415#define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
416#define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
417
418/* 'EZ328-compatible definitions */
419#define IPR_SPI IPR_SPIM
420#define IPR_TMR IPR_TMR1
421
422/**********
423 *
424 * 0xFFFFF4xx -- Parallel Ports
425 *
426 **********/
427
428/*
429 * Port A
430 */
431#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
432#define PADATA_ADDR 0xfffff401 /* Port A data register */
433#define PASEL_ADDR 0xfffff403 /* Port A Select register */
434
435#define PADIR BYTE_REF(PADIR_ADDR)
436#define PADATA BYTE_REF(PADATA_ADDR)
437#define PASEL BYTE_REF(PASEL_ADDR)
438
439#define PA(x) (1 << (x))
440#define PA_A(x) PA((x) - 16) /* This is specific to PA only! */
441
442#define PA_A16 PA(0) /* Use A16 as PA(0) */
443#define PA_A17 PA(1) /* Use A17 as PA(1) */
444#define PA_A18 PA(2) /* Use A18 as PA(2) */
445#define PA_A19 PA(3) /* Use A19 as PA(3) */
446#define PA_A20 PA(4) /* Use A20 as PA(4) */
447#define PA_A21 PA(5) /* Use A21 as PA(5) */
448#define PA_A22 PA(6) /* Use A22 as PA(6) */
449#define PA_A23 PA(7) /* Use A23 as PA(7) */
450
451/*
452 * Port B
453 */
454#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
455#define PBDATA_ADDR 0xfffff409 /* Port B data register */
456#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
457
458#define PBDIR BYTE_REF(PBDIR_ADDR)
459#define PBDATA BYTE_REF(PBDATA_ADDR)
460#define PBSEL BYTE_REF(PBSEL_ADDR)
461
462#define PB(x) (1 << (x))
463#define PB_D(x) PB(x) /* This is specific to port B only */
464
465#define PB_D0 PB(0) /* Use D0 as PB(0) */
466#define PB_D1 PB(1) /* Use D1 as PB(1) */
467#define PB_D2 PB(2) /* Use D2 as PB(2) */
468#define PB_D3 PB(3) /* Use D3 as PB(3) */
469#define PB_D4 PB(4) /* Use D4 as PB(4) */
470#define PB_D5 PB(5) /* Use D5 as PB(5) */
471#define PB_D6 PB(6) /* Use D6 as PB(6) */
472#define PB_D7 PB(7) /* Use D7 as PB(7) */
473
474/*
475 * Port C
476 */
477#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
478#define PCDATA_ADDR 0xfffff411 /* Port C data register */
479#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
480
481#define PCDIR BYTE_REF(PCDIR_ADDR)
482#define PCDATA BYTE_REF(PCDATA_ADDR)
483#define PCSEL BYTE_REF(PCSEL_ADDR)
484
485#define PC(x) (1 << (x))
486
487#define PC_WE PC(6) /* Use WE as PC(6) */
488#define PC_DTACK PC(5) /* Use DTACK as PC(5) */
489#define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */
490#define PC_LDS PC(2) /* Use LDS as PC(2) */
491#define PC_UDS PC(1) /* Use UDS as PC(1) */
492#define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */
493
494/*
495 * Port D
496 */
497#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
498#define PDDATA_ADDR 0xfffff419 /* Port D data register */
499#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
500#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
501#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
502#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
503
504#define PDDIR BYTE_REF(PDDIR_ADDR)
505#define PDDATA BYTE_REF(PDDATA_ADDR)
506#define PDPUEN BYTE_REF(PDPUEN_ADDR)
507#define PDPOL BYTE_REF(PDPOL_ADDR)
508#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
509#define PDIQEG BYTE_REF(PDIQEG_ADDR)
510
511#define PD(x) (1 << (x))
512#define PD_KB(x) PD(x) /* This is specific for Port D only */
513
514#define PD_KB0 PD(0) /* Use KB0 as PD(0) */
515#define PD_KB1 PD(1) /* Use KB1 as PD(1) */
516#define PD_KB2 PD(2) /* Use KB2 as PD(2) */
517#define PD_KB3 PD(3) /* Use KB3 as PD(3) */
518#define PD_KB4 PD(4) /* Use KB4 as PD(4) */
519#define PD_KB5 PD(5) /* Use KB5 as PD(5) */
520#define PD_KB6 PD(6) /* Use KB6 as PD(6) */
521#define PD_KB7 PD(7) /* Use KB7 as PD(7) */
522
523/*
524 * Port E
525 */
526#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
527#define PEDATA_ADDR 0xfffff421 /* Port E data register */
528#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
529#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
530
531#define PEDIR BYTE_REF(PEDIR_ADDR)
532#define PEDATA BYTE_REF(PEDATA_ADDR)
533#define PEPUEN BYTE_REF(PEPUEN_ADDR)
534#define PESEL BYTE_REF(PESEL_ADDR)
535
536#define PE(x) (1 << (x))
537
538#define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */
539#define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */
540#define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */
541#define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */
542#define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */
543#define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */
544#define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */
545
546/*
547 * Port F
548 */
549#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
550#define PFDATA_ADDR 0xfffff429 /* Port F data register */
551#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
552#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
553
554#define PFDIR BYTE_REF(PFDIR_ADDR)
555#define PFDATA BYTE_REF(PFDATA_ADDR)
556#define PFPUEN BYTE_REF(PFPUEN_ADDR)
557#define PFSEL BYTE_REF(PFSEL_ADDR)
558
559#define PF(x) (1 << (x))
560#define PF_A(x) PF((x) - 24) /* This is Port F specific only */
561
562#define PF_A24 PF(0) /* Use A24 as PF(0) */
563#define PF_A25 PF(1) /* Use A25 as PF(1) */
564#define PF_A26 PF(2) /* Use A26 as PF(2) */
565#define PF_A27 PF(3) /* Use A27 as PF(3) */
566#define PF_A28 PF(4) /* Use A28 as PF(4) */
567#define PF_A29 PF(5) /* Use A29 as PF(5) */
568#define PF_A30 PF(6) /* Use A30 as PF(6) */
569#define PF_A31 PF(7) /* Use A31 as PF(7) */
570
571/*
572 * Port G
573 */
574#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
575#define PGDATA_ADDR 0xfffff431 /* Port G data register */
576#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
577#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
578
579#define PGDIR BYTE_REF(PGDIR_ADDR)
580#define PGDATA BYTE_REF(PGDATA_ADDR)
581#define PGPUEN BYTE_REF(PGPUEN_ADDR)
582#define PGSEL BYTE_REF(PGSEL_ADDR)
583
584#define PG(x) (1 << (x))
585
586#define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */
587#define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */
588#define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */
589#define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */
590#define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */
591#define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */
592#define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */
593#define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */
594
595/*
596 * Port J
597 */
598#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
599#define PJDATA_ADDR 0xfffff439 /* Port J data register */
600#define PJSEL_ADDR 0xfffff43b /* Port J Select Register */
601
602#define PJDIR BYTE_REF(PJDIR_ADDR)
603#define PJDATA BYTE_REF(PJDATA_ADDR)
604#define PJSEL BYTE_REF(PJSEL_ADDR)
605
606#define PJ(x) (1 << (x))
607
608#define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */
609
610/*
611 * Port K
612 */
613#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
614#define PKDATA_ADDR 0xfffff441 /* Port K data register */
615#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
616#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
617
618#define PKDIR BYTE_REF(PKDIR_ADDR)
619#define PKDATA BYTE_REF(PKDATA_ADDR)
620#define PKPUEN BYTE_REF(PKPUEN_ADDR)
621#define PKSEL BYTE_REF(PKSEL_ADDR)
622
623#define PK(x) (1 << (x))
624
625/*
626 * Port M
627 */
628#define PMDIR_ADDR 0xfffff438 /* Port M direction reg */
629#define PMDATA_ADDR 0xfffff439 /* Port M data register */
630#define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
631#define PMSEL_ADDR 0xfffff43b /* Port M Select Register */
632
633#define PMDIR BYTE_REF(PMDIR_ADDR)
634#define PMDATA BYTE_REF(PMDATA_ADDR)
635#define PMPUEN BYTE_REF(PMPUEN_ADDR)
636#define PMSEL BYTE_REF(PMSEL_ADDR)
637
638#define PM(x) (1 << (x))
639
640/**********
641 *
642 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
643 *
644 **********/
645
646/*
647 * PWM Control Register
648 */
649#define PWMC_ADDR 0xfffff500
650#define PWMC WORD_REF(PWMC_ADDR)
651
652#define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
653#define PWMC_CLKSEL_SHIFT 0
654#define PWMC_PWMEN 0x0010 /* Enable PWM */
655#define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
656#define PWMC_PIN 0x0080 /* Current PWM output pin status */
657#define PWMC_LOAD 0x0100 /* Force a new period */
658#define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
659#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
660
661/* 'EZ328-compatible definitions */
662#define PWMC_EN PWMC_PWMEN
663
664/*
665 * PWM Period Register
666 */
667#define PWMP_ADDR 0xfffff502
668#define PWMP WORD_REF(PWMP_ADDR)
669
670/*
671 * PWM Width Register
672 */
673#define PWMW_ADDR 0xfffff504
674#define PWMW WORD_REF(PWMW_ADDR)
675
676/*
677 * PWM Counter Register
678 */
679#define PWMCNT_ADDR 0xfffff506
680#define PWMCNT WORD_REF(PWMCNT_ADDR)
681
682/**********
683 *
684 * 0xFFFFF6xx -- General-Purpose Timers
685 *
686 **********/
687
688/*
689 * Timer Unit 1 and 2 Control Registers
690 */
691#define TCTL1_ADDR 0xfffff600
692#define TCTL1 WORD_REF(TCTL1_ADDR)
693#define TCTL2_ADDR 0xfffff60c
694#define TCTL2 WORD_REF(TCTL2_ADDR)
695
696#define TCTL_TEN 0x0001 /* Timer Enable */
697#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
698#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
699#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
700#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
701#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
702#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
703#define TCTL_IRQEN 0x0010 /* IRQ Enable */
704#define TCTL_OM 0x0020 /* Output Mode */
705#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
706#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
707#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
708#define TCTL_FRR 0x0010 /* Free-Run Mode */
709
710/* 'EZ328-compatible definitions */
711#define TCTL_ADDR TCTL1_ADDR
712#define TCTL TCTL1
713
714/*
715 * Timer Unit 1 and 2 Prescaler Registers
716 */
717#define TPRER1_ADDR 0xfffff602
718#define TPRER1 WORD_REF(TPRER1_ADDR)
719#define TPRER2_ADDR 0xfffff60e
720#define TPRER2 WORD_REF(TPRER2_ADDR)
721
722/* 'EZ328-compatible definitions */
723#define TPRER_ADDR TPRER1_ADDR
724#define TPRER TPRER1
725
726/*
727 * Timer Unit 1 and 2 Compare Registers
728 */
729#define TCMP1_ADDR 0xfffff604
730#define TCMP1 WORD_REF(TCMP1_ADDR)
731#define TCMP2_ADDR 0xfffff610
732#define TCMP2 WORD_REF(TCMP2_ADDR)
733
734/* 'EZ328-compatible definitions */
735#define TCMP_ADDR TCMP1_ADDR
736#define TCMP TCMP1
737
738/*
739 * Timer Unit 1 and 2 Capture Registers
740 */
741#define TCR1_ADDR 0xfffff606
742#define TCR1 WORD_REF(TCR1_ADDR)
743#define TCR2_ADDR 0xfffff612
744#define TCR2 WORD_REF(TCR2_ADDR)
745
746/* 'EZ328-compatible definitions */
747#define TCR_ADDR TCR1_ADDR
748#define TCR TCR1
749
750/*
751 * Timer Unit 1 and 2 Counter Registers
752 */
753#define TCN1_ADDR 0xfffff608
754#define TCN1 WORD_REF(TCN1_ADDR)
755#define TCN2_ADDR 0xfffff614
756#define TCN2 WORD_REF(TCN2_ADDR)
757
758/* 'EZ328-compatible definitions */
759#define TCN_ADDR TCN1_ADDR
760#define TCN TCN
761
762/*
763 * Timer Unit 1 and 2 Status Registers
764 */
765#define TSTAT1_ADDR 0xfffff60a
766#define TSTAT1 WORD_REF(TSTAT1_ADDR)
767#define TSTAT2_ADDR 0xfffff616
768#define TSTAT2 WORD_REF(TSTAT2_ADDR)
769
770#define TSTAT_COMP 0x0001 /* Compare Event occurred */
771#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
772
773/* 'EZ328-compatible definitions */
774#define TSTAT_ADDR TSTAT1_ADDR
775#define TSTAT TSTAT1
776
777/*
778 * Watchdog Compare Register
779 */
780#define WRR_ADDR 0xfffff61a
781#define WRR WORD_REF(WRR_ADDR)
782
783/*
784 * Watchdog Counter Register
785 */
786#define WCN_ADDR 0xfffff61c
787#define WCN WORD_REF(WCN_ADDR)
788
789/*
790 * Watchdog Control and Status Register
791 */
792#define WCSR_ADDR 0xfffff618
793#define WCSR WORD_REF(WCSR_ADDR)
794
795#define WCSR_WDEN 0x0001 /* Watchdog Enable */
796#define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/
797#define WCSR_WRST 0x0004 /* Watchdog Reset */
798
799/**********
800 *
801 * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
802 *
803 **********/
804
805/*
806 * SPI Slave Register
807 */
808#define SPISR_ADDR 0xfffff700
809#define SPISR WORD_REF(SPISR_ADDR)
810
811#define SPISR_DATA_ADDR 0xfffff701
812#define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR)
813
814#define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */
815#define SPISR_DATA_SHIFT 0
816#define SPISR_SPISEN 0x0100 /* SPIS module enable */
817#define SPISR_POL 0x0200 /* SPSCLK polarity control */
818#define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */
819#define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */
820#define SPISR_DATARDY 0x1000 /* Data ready */
821#define SPISR_ENPOL 0x2000 /* Enable Polarity */
822#define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
823#define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */
824
825/**********
826 *
827 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
828 *
829 **********/
830
831/*
832 * SPIM Data Register
833 */
834#define SPIMDATA_ADDR 0xfffff800
835#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
836
837/*
838 * SPIM Control/Status Register
839 */
840#define SPIMCONT_ADDR 0xfffff802
841#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
842
843#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
844#define SPIMCONT_BIT_COUNT_SHIFT 0
845#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
846#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
847#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
848#define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */
849#define SPIMCONT_XCH 0x0100 /* Exchange */
850#define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
851#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
852#define SPIMCONT_DATA_RATE_SHIFT 13
853
854/* 'EZ328-compatible definitions */
855#define SPIMCONT_IRQ SPIMCONT_SPIMIRQ
856#define SPIMCONT_ENABLE SPIMCONT_SPIMEN
857/**********
858 *
859 * 0xFFFFF9xx -- UART
860 *
861 **********/
862
863/*
864 * UART Status/Control Register
865 */
866#define USTCNT_ADDR 0xfffff900
867#define USTCNT WORD_REF(USTCNT_ADDR)
868
869#define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
870#define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
871#define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
872#define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
873#define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
874#define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
875#define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
876#define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
877#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
878#define USTCNT_STOP 0x0200 /* Stop bit transmission */
879#define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */
880#define USTCNT_PARITYEN 0x0800 /* Parity Enable */
881#define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
882#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
883#define USTCNT_RXEN 0x4000 /* Receiver Enable */
884#define USTCNT_UARTEN 0x8000 /* UART Enable */
885
886/* 'EZ328-compatible definitions */
887#define USTCNT_TXAE USTCNT_TXAVAILEN
888#define USTCNT_TXHE USTCNT_TXHALFEN
889#define USTCNT_TXEE USTCNT_TXEMPTYEN
890#define USTCNT_RXRE USTCNT_RXREADYEN
891#define USTCNT_RXHE USTCNT_RXHALFEN
892#define USTCNT_RXFE USTCNT_RXFULLEN
893#define USTCNT_CTSD USTCNT_CTSDELTAEN
894#define USTCNT_ODD USTCNT_ODD_EVEN
895#define USTCNT_PEN USTCNT_PARITYEN
896#define USTCNT_CLKM USTCNT_CLKMODE
897#define USTCNT_UEN USTCNT_UARTEN
898
899/*
900 * UART Baud Control Register
901 */
902#define UBAUD_ADDR 0xfffff902
903#define UBAUD WORD_REF(UBAUD_ADDR)
904
905#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
906#define UBAUD_PRESCALER_SHIFT 0
907#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
908#define UBAUD_DIVIDE_SHIFT 8
909#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
910#define UBAUD_GPIOSRC 0x1000 /* GPIO source */
911#define UBAUD_GPIODIR 0x2000 /* GPIO Direction */
912#define UBAUD_GPIO 0x4000 /* Current GPIO pin status */
913#define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */
914
915/*
916 * UART Receiver Register
917 */
918#define URX_ADDR 0xfffff904
919#define URX WORD_REF(URX_ADDR)
920
921#define URX_RXDATA_ADDR 0xfffff905
922#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
923
924#define URX_RXDATA_MASK 0x00ff /* Received data */
925#define URX_RXDATA_SHIFT 0
926#define URX_PARITY_ERROR 0x0100 /* Parity Error */
927#define URX_BREAK 0x0200 /* Break Detected */
928#define URX_FRAME_ERROR 0x0400 /* Framing Error */
929#define URX_OVRUN 0x0800 /* Serial Overrun */
930#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
931#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
932#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
933
934/*
935 * UART Transmitter Register
936 */
937#define UTX_ADDR 0xfffff906
938#define UTX WORD_REF(UTX_ADDR)
939
940#define UTX_TXDATA_ADDR 0xfffff907
941#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
942
943#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
944#define UTX_TXDATA_SHIFT 0
945#define UTX_CTS_DELTA 0x0100 /* CTS changed */
946#define UTX_CTS_STATUS 0x0200 /* CTS State */
947#define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */
948#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
949#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
950#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
951#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
952
953/* 'EZ328-compatible definitions */
954#define UTX_CTS_STAT UTX_CTS_STATUS
955#define UTX_NOCTS UTX_IGNORE_CTS
956
957/*
958 * UART Miscellaneous Register
959 */
960#define UMISC_ADDR 0xfffff908
961#define UMISC WORD_REF(UMISC_ADDR)
962
963#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
964#define UMISC_RX_POL 0x0008 /* Receive Polarity */
965#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
966#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
967#define UMISC_RTS 0x0040 /* Set RTS status */
968#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
969#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
970#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
971#define UMISC_CLKSRC 0x4000 /* Clock Source */
972
973
974/* generalization of uart control registers to support multiple ports: */
975typedef volatile struct {
976 volatile unsigned short int ustcnt;
977 volatile unsigned short int ubaud;
978 union {
979 volatile unsigned short int w;
980 struct {
981 volatile unsigned char status;
982 volatile unsigned char rxdata;
983 } b;
984 } urx;
985 union {
986 volatile unsigned short int w;
987 struct {
988 volatile unsigned char status;
989 volatile unsigned char txdata;
990 } b;
991 } utx;
992 volatile unsigned short int umisc;
993 volatile unsigned short int pad1;
994 volatile unsigned short int pad2;
995 volatile unsigned short int pad3;
996} __attribute__((packed)) m68328_uart;
997
998
999/**********
1000 *
1001 * 0xFFFFFAxx -- LCD Controller
1002 *
1003 **********/
1004
1005/*
1006 * LCD Screen Starting Address Register
1007 */
1008#define LSSA_ADDR 0xfffffa00
1009#define LSSA LONG_REF(LSSA_ADDR)
1010
1011#define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */
1012
1013/*
1014 * LCD Virtual Page Width Register
1015 */
1016#define LVPW_ADDR 0xfffffa05
1017#define LVPW BYTE_REF(LVPW_ADDR)
1018
1019/*
1020 * LCD Screen Width Register (not compatible with 'EZ328 !!!)
1021 */
1022#define LXMAX_ADDR 0xfffffa08
1023#define LXMAX WORD_REF(LXMAX_ADDR)
1024
1025#define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
1026
1027/*
1028 * LCD Screen Height Register
1029 */
1030#define LYMAX_ADDR 0xfffffa0a
1031#define LYMAX WORD_REF(LYMAX_ADDR)
1032
1033#define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
1034
1035/*
1036 * LCD Cursor X Position Register
1037 */
1038#define LCXP_ADDR 0xfffffa18
1039#define LCXP WORD_REF(LCXP_ADDR)
1040
1041#define LCXP_CC_MASK 0xc000 /* Cursor Control */
1042#define LCXP_CC_TRAMSPARENT 0x0000
1043#define LCXP_CC_BLACK 0x4000
1044#define LCXP_CC_REVERSED 0x8000
1045#define LCXP_CC_WHITE 0xc000
1046#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
1047
1048/*
1049 * LCD Cursor Y Position Register
1050 */
1051#define LCYP_ADDR 0xfffffa1a
1052#define LCYP WORD_REF(LCYP_ADDR)
1053
1054#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
1055
1056/*
1057 * LCD Cursor Width and Heigth Register
1058 */
1059#define LCWCH_ADDR 0xfffffa1c
1060#define LCWCH WORD_REF(LCWCH_ADDR)
1061
1062#define LCWCH_CH_MASK 0x001f /* Cursor Height */
1063#define LCWCH_CH_SHIFT 0
1064#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
1065#define LCWCH_CW_SHIFT 8
1066
1067/*
1068 * LCD Blink Control Register
1069 */
1070#define LBLKC_ADDR 0xfffffa1f
1071#define LBLKC BYTE_REF(LBLKC_ADDR)
1072
1073#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
1074#define LBLKC_BD_SHIFT 0
1075#define LBLKC_BKEN 0x80 /* Blink Enabled */
1076
1077/*
1078 * LCD Panel Interface Configuration Register
1079 */
1080#define LPICF_ADDR 0xfffffa20
1081#define LPICF BYTE_REF(LPICF_ADDR)
1082
1083#define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
1084#define LPICF_GS_BW 0x00
1085#define LPICF_GS_GRAY_4 0x01
1086#define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */
1087#define LPICF_PBSIZ_1 0x00
1088#define LPICF_PBSIZ_2 0x02
1089#define LPICF_PBSIZ_4 0x04
1090
1091/*
1092 * LCD Polarity Configuration Register
1093 */
1094#define LPOLCF_ADDR 0xfffffa21
1095#define LPOLCF BYTE_REF(LPOLCF_ADDR)
1096
1097#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
1098#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
1099#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
1100#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
1101
1102/*
1103 * LACD (LCD Alternate Crystal Direction) Rate Control Register
1104 */
1105#define LACDRC_ADDR 0xfffffa23
1106#define LACDRC BYTE_REF(LACDRC_ADDR)
1107
1108#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
1109#define LACDRC_ACD_SHIFT 0
1110
1111/*
1112 * LCD Pixel Clock Divider Register
1113 */
1114#define LPXCD_ADDR 0xfffffa25
1115#define LPXCD BYTE_REF(LPXCD_ADDR)
1116
1117#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1118#define LPXCD_PCD_SHIFT 0
1119
1120/*
1121 * LCD Clocking Control Register
1122 */
1123#define LCKCON_ADDR 0xfffffa27
1124#define LCKCON BYTE_REF(LCKCON_ADDR)
1125
1126#define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
1127#define LCKCON_DWIDTH 0x02 /* Display Memory Width */
1128#define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
1129#define LCKCON_DWS_SHIFT 2
1130#define LCKCON_DMA16 0x40 /* DMA burst length */
1131#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
1132
1133/* 'EZ328-compatible definitions */
1134#define LCKCON_DW_MASK LCKCON_DWS_MASK
1135#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
1136
1137/*
1138 * LCD Last Buffer Address Register
1139 */
1140#define LLBAR_ADDR 0xfffffa29
1141#define LLBAR BYTE_REF(LLBAR_ADDR)
1142
1143#define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */
1144#define LLBAR_LBAR_SHIFT 0
1145
1146/*
1147 * LCD Octet Terminal Count Register
1148 */
1149#define LOTCR_ADDR 0xfffffa2b
1150#define LOTCR BYTE_REF(LOTCR_ADDR)
1151
1152/*
1153 * LCD Panning Offset Register
1154 */
1155#define LPOSR_ADDR 0xfffffa2d
1156#define LPOSR BYTE_REF(LPOSR_ADDR)
1157
1158#define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */
1159#define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */
1160#define LPOSR_POS_SHIFT 0
1161
1162/*
1163 * LCD Frame Rate Control Modulation Register
1164 */
1165#define LFRCM_ADDR 0xfffffa31
1166#define LFRCM BYTE_REF(LFRCM_ADDR)
1167
1168#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
1169#define LFRCM_YMOD_SHIFT 0
1170#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
1171#define LFRCM_XMOD_SHIFT 4
1172
1173/*
1174 * LCD Gray Palette Mapping Register
1175 */
1176#define LGPMR_ADDR 0xfffffa32
1177#define LGPMR WORD_REF(LGPMR_ADDR)
1178
1179#define LGPMR_GLEVEL3_MASK 0x000f
1180#define LGPMR_GLEVEL3_SHIFT 0
1181#define LGPMR_GLEVEL2_MASK 0x00f0
1182#define LGPMR_GLEVEL2_SHIFT 4
1183#define LGPMR_GLEVEL0_MASK 0x0f00
1184#define LGPMR_GLEVEL0_SHIFT 8
1185#define LGPMR_GLEVEL1_MASK 0xf000
1186#define LGPMR_GLEVEL1_SHIFT 12
1187
1188/**********
1189 *
1190 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1191 *
1192 **********/
1193
1194/*
1195 * RTC Hours Minutes and Seconds Register
1196 */
1197#define RTCTIME_ADDR 0xfffffb00
1198#define RTCTIME LONG_REF(RTCTIME_ADDR)
1199
1200#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1201#define RTCTIME_SECONDS_SHIFT 0
1202#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1203#define RTCTIME_MINUTES_SHIFT 16
1204#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1205#define RTCTIME_HOURS_SHIFT 24
1206
1207/*
1208 * RTC Alarm Register
1209 */
1210#define RTCALRM_ADDR 0xfffffb04
1211#define RTCALRM LONG_REF(RTCALRM_ADDR)
1212
1213#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1214#define RTCALRM_SECONDS_SHIFT 0
1215#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1216#define RTCALRM_MINUTES_SHIFT 16
1217#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1218#define RTCALRM_HOURS_SHIFT 24
1219
1220/*
1221 * RTC Control Register
1222 */
1223#define RTCCTL_ADDR 0xfffffb0c
1224#define RTCCTL WORD_REF(RTCCTL_ADDR)
1225
1226#define RTCCTL_384 0x0020 /* Crystal Selection */
1227#define RTCCTL_ENABLE 0x0080 /* RTC Enable */
1228
1229/* 'EZ328-compatible definitions */
1230#define RTCCTL_XTL RTCCTL_384
1231#define RTCCTL_EN RTCCTL_ENABLE
1232
1233/*
1234 * RTC Interrupt Status Register
1235 */
1236#define RTCISR_ADDR 0xfffffb0e
1237#define RTCISR WORD_REF(RTCISR_ADDR)
1238
1239#define RTCISR_SW 0x0001 /* Stopwatch timed out */
1240#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1241#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1242#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1243#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1244
1245/*
1246 * RTC Interrupt Enable Register
1247 */
1248#define RTCIENR_ADDR 0xfffffb10
1249#define RTCIENR WORD_REF(RTCIENR_ADDR)
1250
1251#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1252#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1253#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1254#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1255#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1256
1257/*
1258 * Stopwatch Minutes Register
1259 */
1260#define STPWCH_ADDR 0xfffffb12
1261#define STPWCH WORD_REF(STPWCH)
1262
1263#define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */
1264#define SPTWCH_CNT_SHIFT 0
1265
1266#endif /* _MC68328_H_ */
diff --git a/arch/m68knommu/include/asm/MC68332.h b/arch/m68knommu/include/asm/MC68332.h
new file mode 100644
index 000000000000..6bb8f02685a2
--- /dev/null
+++ b/arch/m68knommu/include/asm/MC68332.h
@@ -0,0 +1,152 @@
1
2/* include/asm-m68knommu/MC68332.h: '332 control registers
3 *
4 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
5 *
6 */
7
8#ifndef _MC68332_H_
9#define _MC68332_H_
10
11#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
12#define WORD_REF(addr) (*((volatile unsigned short*)addr))
13
14#define PORTE_ADDR 0xfffa11
15#define PORTE BYTE_REF(PORTE_ADDR)
16#define DDRE_ADDR 0xfffa15
17#define DDRE BYTE_REF(DDRE_ADDR)
18#define PEPAR_ADDR 0xfffa17
19#define PEPAR BYTE_REF(PEPAR_ADDR)
20
21#define PORTF_ADDR 0xfffa19
22#define PORTF BYTE_REF(PORTF_ADDR)
23#define DDRF_ADDR 0xfffa1d
24#define DDRF BYTE_REF(DDRF_ADDR)
25#define PFPAR_ADDR 0xfffa1f
26#define PFPAR BYTE_REF(PFPAR_ADDR)
27
28#define PORTQS_ADDR 0xfffc15
29#define PORTQS BYTE_REF(PORTQS_ADDR)
30#define DDRQS_ADDR 0xfffc17
31#define DDRQS BYTE_REF(DDRQS_ADDR)
32#define PQSPAR_ADDR 0xfffc16
33#define PQSPAR BYTE_REF(PQSPAR_ADDR)
34
35#define CSPAR0_ADDR 0xFFFA44
36#define CSPAR0 WORD_REF(CSPAR0_ADDR)
37#define CSPAR1_ADDR 0xFFFA46
38#define CSPAR1 WORD_REF(CSPAR1_ADDR)
39#define CSARBT_ADDR 0xFFFA48
40#define CSARBT WORD_REF(CSARBT_ADDR)
41#define CSOPBT_ADDR 0xFFFA4A
42#define CSOPBT WORD_REF(CSOPBT_ADDR)
43#define CSBAR0_ADDR 0xFFFA4C
44#define CSBAR0 WORD_REF(CSBAR0_ADDR)
45#define CSOR0_ADDR 0xFFFA4E
46#define CSOR0 WORD_REF(CSOR0_ADDR)
47#define CSBAR1_ADDR 0xFFFA50
48#define CSBAR1 WORD_REF(CSBAR1_ADDR)
49#define CSOR1_ADDR 0xFFFA52
50#define CSOR1 WORD_REF(CSOR1_ADDR)
51#define CSBAR2_ADDR 0xFFFA54
52#define CSBAR2 WORD_REF(CSBAR2_ADDR)
53#define CSOR2_ADDR 0xFFFA56
54#define CSOR2 WORD_REF(CSOR2_ADDR)
55#define CSBAR3_ADDR 0xFFFA58
56#define CSBAR3 WORD_REF(CSBAR3_ADDR)
57#define CSOR3_ADDR 0xFFFA5A
58#define CSOR3 WORD_REF(CSOR3_ADDR)
59#define CSBAR4_ADDR 0xFFFA5C
60#define CSBAR4 WORD_REF(CSBAR4_ADDR)
61#define CSOR4_ADDR 0xFFFA5E
62#define CSOR4 WORD_REF(CSOR4_ADDR)
63#define CSBAR5_ADDR 0xFFFA60
64#define CSBAR5 WORD_REF(CSBAR5_ADDR)
65#define CSOR5_ADDR 0xFFFA62
66#define CSOR5 WORD_REF(CSOR5_ADDR)
67#define CSBAR6_ADDR 0xFFFA64
68#define CSBAR6 WORD_REF(CSBAR6_ADDR)
69#define CSOR6_ADDR 0xFFFA66
70#define CSOR6 WORD_REF(CSOR6_ADDR)
71#define CSBAR7_ADDR 0xFFFA68
72#define CSBAR7 WORD_REF(CSBAR7_ADDR)
73#define CSOR7_ADDR 0xFFFA6A
74#define CSOR7 WORD_REF(CSOR7_ADDR)
75#define CSBAR8_ADDR 0xFFFA6C
76#define CSBAR8 WORD_REF(CSBAR8_ADDR)
77#define CSOR8_ADDR 0xFFFA6E
78#define CSOR8 WORD_REF(CSOR8_ADDR)
79#define CSBAR9_ADDR 0xFFFA70
80#define CSBAR9 WORD_REF(CSBAR9_ADDR)
81#define CSOR9_ADDR 0xFFFA72
82#define CSOR9 WORD_REF(CSOR9_ADDR)
83#define CSBAR10_ADDR 0xFFFA74
84#define CSBAR10 WORD_REF(CSBAR10_ADDR)
85#define CSOR10_ADDR 0xFFFA76
86#define CSOR10 WORD_REF(CSOR10_ADDR)
87
88#define CSOR_MODE_ASYNC 0x0000
89#define CSOR_MODE_SYNC 0x8000
90#define CSOR_MODE_MASK 0x8000
91#define CSOR_BYTE_DISABLE 0x0000
92#define CSOR_BYTE_UPPER 0x4000
93#define CSOR_BYTE_LOWER 0x2000
94#define CSOR_BYTE_BOTH 0x6000
95#define CSOR_BYTE_MASK 0x6000
96#define CSOR_RW_RSVD 0x0000
97#define CSOR_RW_READ 0x0800
98#define CSOR_RW_WRITE 0x1000
99#define CSOR_RW_BOTH 0x1800
100#define CSOR_RW_MASK 0x1800
101#define CSOR_STROBE_DS 0x0400
102#define CSOR_STROBE_AS 0x0000
103#define CSOR_STROBE_MASK 0x0400
104#define CSOR_DSACK_WAIT(x) (wait << 6)
105#define CSOR_DSACK_FTERM (14 << 6)
106#define CSOR_DSACK_EXTERNAL (15 << 6)
107#define CSOR_DSACK_MASK 0x03c0
108#define CSOR_SPACE_CPU 0x0000
109#define CSOR_SPACE_USER 0x0010
110#define CSOR_SPACE_SU 0x0020
111#define CSOR_SPACE_BOTH 0x0030
112#define CSOR_SPACE_MASK 0x0030
113#define CSOR_IPL_ALL 0x0000
114#define CSOR_IPL_PRIORITY(x) (x << 1)
115#define CSOR_IPL_MASK 0x000e
116#define CSOR_AVEC_ON 0x0001
117#define CSOR_AVEC_OFF 0x0000
118#define CSOR_AVEC_MASK 0x0001
119
120#define CSBAR_ADDR(x) ((addr >> 11) << 3)
121#define CSBAR_ADDR_MASK 0xfff8
122#define CSBAR_BLKSIZE_2K 0x0000
123#define CSBAR_BLKSIZE_8K 0x0001
124#define CSBAR_BLKSIZE_16K 0x0002
125#define CSBAR_BLKSIZE_64K 0x0003
126#define CSBAR_BLKSIZE_128K 0x0004
127#define CSBAR_BLKSIZE_256K 0x0005
128#define CSBAR_BLKSIZE_512K 0x0006
129#define CSBAR_BLKSIZE_1M 0x0007
130#define CSBAR_BLKSIZE_MASK 0x0007
131
132#define CSPAR_DISC 0
133#define CSPAR_ALT 1
134#define CSPAR_CS8 2
135#define CSPAR_CS16 3
136#define CSPAR_MASK 3
137
138#define CSPAR0_CSBOOT(x) (x << 0)
139#define CSPAR0_CS0(x) (x << 2)
140#define CSPAR0_CS1(x) (x << 4)
141#define CSPAR0_CS2(x) (x << 6)
142#define CSPAR0_CS3(x) (x << 8)
143#define CSPAR0_CS4(x) (x << 10)
144#define CSPAR0_CS5(x) (x << 12)
145
146#define CSPAR1_CS6(x) (x << 0)
147#define CSPAR1_CS7(x) (x << 2)
148#define CSPAR1_CS8(x) (x << 4)
149#define CSPAR1_CS9(x) (x << 6)
150#define CSPAR1_CS10(x) (x << 8)
151
152#endif
diff --git a/arch/m68knommu/include/asm/MC68EZ328.h b/arch/m68knommu/include/asm/MC68EZ328.h
new file mode 100644
index 000000000000..69b7f9139e5e
--- /dev/null
+++ b/arch/m68knommu/include/asm/MC68EZ328.h
@@ -0,0 +1,1253 @@
1
2/* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
3 *
4 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
5 * Bear & Hare Software, Inc.
6 *
7 * Based on include/asm-m68knommu/MC68332.h
8 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
9 * The Silver Hammer Group, Ltd.
10 *
11 */
12
13#ifndef _MC68EZ328_H_
14#define _MC68EZ328_H_
15
16#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
17#define WORD_REF(addr) (*((volatile unsigned short*)addr))
18#define LONG_REF(addr) (*((volatile unsigned long*)addr))
19
20#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
21#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
22
23/**********
24 *
25 * 0xFFFFF0xx -- System Control
26 *
27 **********/
28
29/*
30 * System Control Register (SCR)
31 */
32#define SCR_ADDR 0xfffff000
33#define SCR BYTE_REF(SCR_ADDR)
34
35#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
36#define SCR_DMAP 0x04 /* Double Map */
37#define SCR_SO 0x08 /* Supervisor Only */
38#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
39#define SCR_PRV 0x20 /* Privilege Violation */
40#define SCR_WPV 0x40 /* Write Protect Violation */
41#define SCR_BETO 0x80 /* Bus-Error TimeOut */
42
43/*
44 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
45 */
46#define MRR_ADDR 0xfffff004
47#define MRR LONG_REF(MRR_ADDR)
48
49/**********
50 *
51 * 0xFFFFF1xx -- Chip-Select logic
52 *
53 **********/
54
55/*
56 * Chip Select Group Base Registers
57 */
58#define CSGBA_ADDR 0xfffff100
59#define CSGBB_ADDR 0xfffff102
60
61#define CSGBC_ADDR 0xfffff104
62#define CSGBD_ADDR 0xfffff106
63
64#define CSGBA WORD_REF(CSGBA_ADDR)
65#define CSGBB WORD_REF(CSGBB_ADDR)
66#define CSGBC WORD_REF(CSGBC_ADDR)
67#define CSGBD WORD_REF(CSGBD_ADDR)
68
69/*
70 * Chip Select Registers
71 */
72#define CSA_ADDR 0xfffff110
73#define CSB_ADDR 0xfffff112
74#define CSC_ADDR 0xfffff114
75#define CSD_ADDR 0xfffff116
76
77#define CSA WORD_REF(CSA_ADDR)
78#define CSB WORD_REF(CSB_ADDR)
79#define CSC WORD_REF(CSC_ADDR)
80#define CSD WORD_REF(CSD_ADDR)
81
82#define CSA_EN 0x0001 /* Chip-Select Enable */
83#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
84#define CSA_SIZ_SHIFT 1
85#define CSA_WS_MASK 0x0070 /* Wait State */
86#define CSA_WS_SHIFT 4
87#define CSA_BSW 0x0080 /* Data Bus Width */
88#define CSA_FLASH 0x0100 /* FLASH Memory Support */
89#define CSA_RO 0x8000 /* Read-Only */
90
91#define CSB_EN 0x0001 /* Chip-Select Enable */
92#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
93#define CSB_SIZ_SHIFT 1
94#define CSB_WS_MASK 0x0070 /* Wait State */
95#define CSB_WS_SHIFT 4
96#define CSB_BSW 0x0080 /* Data Bus Width */
97#define CSB_FLASH 0x0100 /* FLASH Memory Support */
98#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
99#define CSB_UPSIZ_SHIFT 11
100#define CSB_ROP 0x2000 /* Readonly if protected */
101#define CSB_SOP 0x4000 /* Supervisor only if protected */
102#define CSB_RO 0x8000 /* Read-Only */
103
104#define CSC_EN 0x0001 /* Chip-Select Enable */
105#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
106#define CSC_SIZ_SHIFT 1
107#define CSC_WS_MASK 0x0070 /* Wait State */
108#define CSC_WS_SHIFT 4
109#define CSC_BSW 0x0080 /* Data Bus Width */
110#define CSC_FLASH 0x0100 /* FLASH Memory Support */
111#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
112#define CSC_UPSIZ_SHIFT 11
113#define CSC_ROP 0x2000 /* Readonly if protected */
114#define CSC_SOP 0x4000 /* Supervisor only if protected */
115#define CSC_RO 0x8000 /* Read-Only */
116
117#define CSD_EN 0x0001 /* Chip-Select Enable */
118#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
119#define CSD_SIZ_SHIFT 1
120#define CSD_WS_MASK 0x0070 /* Wait State */
121#define CSD_WS_SHIFT 4
122#define CSD_BSW 0x0080 /* Data Bus Width */
123#define CSD_FLASH 0x0100 /* FLASH Memory Support */
124#define CSD_DRAM 0x0200 /* Dram Selection */
125#define CSD_COMB 0x0400 /* Combining */
126#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
127#define CSD_UPSIZ_SHIFT 11
128#define CSD_ROP 0x2000 /* Readonly if protected */
129#define CSD_SOP 0x4000 /* Supervisor only if protected */
130#define CSD_RO 0x8000 /* Read-Only */
131
132/*
133 * Emulation Chip-Select Register
134 */
135#define EMUCS_ADDR 0xfffff118
136#define EMUCS WORD_REF(EMUCS_ADDR)
137
138#define EMUCS_WS_MASK 0x0070
139#define EMUCS_WS_SHIFT 4
140
141/**********
142 *
143 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
144 *
145 **********/
146
147/*
148 * PLL Control Register
149 */
150#define PLLCR_ADDR 0xfffff200
151#define PLLCR WORD_REF(PLLCR_ADDR)
152
153#define PLLCR_DISPLL 0x0008 /* Disable PLL */
154#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
155#define PLLCR_PRESC 0x0020 /* VCO prescaler */
156#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
157#define PLLCR_SYSCLK_SEL_SHIFT 8
158#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
159#define PLLCR_LCDCLK_SEL_SHIFT 11
160
161/* '328-compatible definitions */
162#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
163#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
164
165/*
166 * PLL Frequency Select Register
167 */
168#define PLLFSR_ADDR 0xfffff202
169#define PLLFSR WORD_REF(PLLFSR_ADDR)
170
171#define PLLFSR_PC_MASK 0x00ff /* P Count */
172#define PLLFSR_PC_SHIFT 0
173#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
174#define PLLFSR_QC_SHIFT 8
175#define PLLFSR_PROT 0x4000 /* Protect P & Q */
176#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
177
178/*
179 * Power Control Register
180 */
181#define PCTRL_ADDR 0xfffff207
182#define PCTRL BYTE_REF(PCTRL_ADDR)
183
184#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
185#define PCTRL_WIDTH_SHIFT 0
186#define PCTRL_PCEN 0x80 /* Power Control Enable */
187
188/**********
189 *
190 * 0xFFFFF3xx -- Interrupt Controller
191 *
192 **********/
193
194/*
195 * Interrupt Vector Register
196 */
197#define IVR_ADDR 0xfffff300
198#define IVR BYTE_REF(IVR_ADDR)
199
200#define IVR_VECTOR_MASK 0xF8
201
202/*
203 * Interrupt control Register
204 */
205#define ICR_ADDR 0xfffff302
206#define ICR WORD_REF(ICR_ADDR)
207
208#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
209#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
210#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
211#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
212#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
213#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
214#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
215#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
216#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
217
218/*
219 * Interrupt Mask Register
220 */
221#define IMR_ADDR 0xfffff304
222#define IMR LONG_REF(IMR_ADDR)
223
224/*
225 * Define the names for bit positions first. This is useful for
226 * request_irq
227 */
228#define SPI_IRQ_NUM 0 /* SPI interrupt */
229#define TMR_IRQ_NUM 1 /* Timer interrupt */
230#define UART_IRQ_NUM 2 /* UART interrupt */
231#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
232#define RTC_IRQ_NUM 4 /* RTC interrupt */
233#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
234#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
235#define INT0_IRQ_NUM 8 /* External INT0 */
236#define INT1_IRQ_NUM 9 /* External INT1 */
237#define INT2_IRQ_NUM 10 /* External INT2 */
238#define INT3_IRQ_NUM 11 /* External INT3 */
239#define IRQ1_IRQ_NUM 16 /* IRQ1 */
240#define IRQ2_IRQ_NUM 17 /* IRQ2 */
241#define IRQ3_IRQ_NUM 18 /* IRQ3 */
242#define IRQ6_IRQ_NUM 19 /* IRQ6 */
243#define IRQ5_IRQ_NUM 20 /* IRQ5 */
244#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
245#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
246
247/* '328-compatible definitions */
248#define SPIM_IRQ_NUM SPI_IRQ_NUM
249#define TMR1_IRQ_NUM TMR_IRQ_NUM
250
251/*
252 * Here go the bitmasks themselves
253 */
254#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
255#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
256#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
257#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
258#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
259#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
260#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
261#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
262#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
263#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
264#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
265#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
266#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
267#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
268#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
269#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
270#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
271#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
272
273/* '328-compatible definitions */
274#define IMR_MSPIM IMR_MSPI
275#define IMR_MTMR1 IMR_MTMR
276
277/*
278 * Interrupt Status Register
279 */
280#define ISR_ADDR 0xfffff30c
281#define ISR LONG_REF(ISR_ADDR)
282
283#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
284#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
285#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
286#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
287#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
288#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
289#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
290#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
291#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
292#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
293#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
294#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
295#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
296#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
297#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
298#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
299#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
300#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
301
302/* '328-compatible definitions */
303#define ISR_SPIM ISR_SPI
304#define ISR_TMR1 ISR_TMR
305
306/*
307 * Interrupt Pending Register
308 */
309#define IPR_ADDR 0xfffff30c
310#define IPR LONG_REF(IPR_ADDR)
311
312#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
313#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
314#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
315#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
316#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
317#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
318#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
319#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
320#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
321#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
322#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
323#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
324#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
325#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
326#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
327#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
328#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
329#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
330
331/* '328-compatible definitions */
332#define IPR_SPIM IPR_SPI
333#define IPR_TMR1 IPR_TMR
334
335/**********
336 *
337 * 0xFFFFF4xx -- Parallel Ports
338 *
339 **********/
340
341/*
342 * Port A
343 */
344#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
345#define PADATA_ADDR 0xfffff401 /* Port A data register */
346#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
347
348#define PADIR BYTE_REF(PADIR_ADDR)
349#define PADATA BYTE_REF(PADATA_ADDR)
350#define PAPUEN BYTE_REF(PAPUEN_ADDR)
351
352#define PA(x) (1 << (x))
353
354/*
355 * Port B
356 */
357#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
358#define PBDATA_ADDR 0xfffff409 /* Port B data register */
359#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
360#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
361
362#define PBDIR BYTE_REF(PBDIR_ADDR)
363#define PBDATA BYTE_REF(PBDATA_ADDR)
364#define PBPUEN BYTE_REF(PBPUEN_ADDR)
365#define PBSEL BYTE_REF(PBSEL_ADDR)
366
367#define PB(x) (1 << (x))
368
369#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
370#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
371#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
372#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
373#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
374#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
375#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
376#define PB_PWMO 0x80 /* Use PWMO as PB[7] */
377
378/*
379 * Port C
380 */
381#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
382#define PCDATA_ADDR 0xfffff411 /* Port C data register */
383#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
384#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
385
386#define PCDIR BYTE_REF(PCDIR_ADDR)
387#define PCDATA BYTE_REF(PCDATA_ADDR)
388#define PCPDEN BYTE_REF(PCPDEN_ADDR)
389#define PCSEL BYTE_REF(PCSEL_ADDR)
390
391#define PC(x) (1 << (x))
392
393#define PC_LD0 0x01 /* Use LD0 as PC[0] */
394#define PC_LD1 0x02 /* Use LD1 as PC[1] */
395#define PC_LD2 0x04 /* Use LD2 as PC[2] */
396#define PC_LD3 0x08 /* Use LD3 as PC[3] */
397#define PC_LFLM 0x10 /* Use LFLM as PC[4] */
398#define PC_LLP 0x20 /* Use LLP as PC[5] */
399#define PC_LCLK 0x40 /* Use LCLK as PC[6] */
400#define PC_LACD 0x80 /* Use LACD as PC[7] */
401
402/*
403 * Port D
404 */
405#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
406#define PDDATA_ADDR 0xfffff419 /* Port D data register */
407#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
408#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
409#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
410#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
411#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
412#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
413
414#define PDDIR BYTE_REF(PDDIR_ADDR)
415#define PDDATA BYTE_REF(PDDATA_ADDR)
416#define PDPUEN BYTE_REF(PDPUEN_ADDR)
417#define PDSEL BYTE_REF(PDSEL_ADDR)
418#define PDPOL BYTE_REF(PDPOL_ADDR)
419#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
420#define PDKBEN BYTE_REF(PDKBEN_ADDR)
421#define PDIQEG BYTE_REF(PDIQEG_ADDR)
422
423#define PD(x) (1 << (x))
424
425#define PD_INT0 0x01 /* Use INT0 as PD[0] */
426#define PD_INT1 0x02 /* Use INT1 as PD[1] */
427#define PD_INT2 0x04 /* Use INT2 as PD[2] */
428#define PD_INT3 0x08 /* Use INT3 as PD[3] */
429#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
430#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
431#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
432#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
433
434/*
435 * Port E
436 */
437#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
438#define PEDATA_ADDR 0xfffff421 /* Port E data register */
439#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
440#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
441
442#define PEDIR BYTE_REF(PEDIR_ADDR)
443#define PEDATA BYTE_REF(PEDATA_ADDR)
444#define PEPUEN BYTE_REF(PEPUEN_ADDR)
445#define PESEL BYTE_REF(PESEL_ADDR)
446
447#define PE(x) (1 << (x))
448
449#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
450#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
451#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
452#define PE_DWE 0x08 /* Use DWE as PE[3] */
453#define PE_RXD 0x10 /* Use RXD as PE[4] */
454#define PE_TXD 0x20 /* Use TXD as PE[5] */
455#define PE_RTS 0x40 /* Use RTS as PE[6] */
456#define PE_CTS 0x80 /* Use CTS as PE[7] */
457
458/*
459 * Port F
460 */
461#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
462#define PFDATA_ADDR 0xfffff429 /* Port F data register */
463#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
464#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
465
466#define PFDIR BYTE_REF(PFDIR_ADDR)
467#define PFDATA BYTE_REF(PFDATA_ADDR)
468#define PFPUEN BYTE_REF(PFPUEN_ADDR)
469#define PFSEL BYTE_REF(PFSEL_ADDR)
470
471#define PF(x) (1 << (x))
472
473#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
474#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
475#define PF_CLKO 0x04 /* Use CLKO as PF[2] */
476#define PF_A20 0x08 /* Use A20 as PF[3] */
477#define PF_A21 0x10 /* Use A21 as PF[4] */
478#define PF_A22 0x20 /* Use A22 as PF[5] */
479#define PF_A23 0x40 /* Use A23 as PF[6] */
480#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
481
482/*
483 * Port G
484 */
485#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
486#define PGDATA_ADDR 0xfffff431 /* Port G data register */
487#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
488#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
489
490#define PGDIR BYTE_REF(PGDIR_ADDR)
491#define PGDATA BYTE_REF(PGDATA_ADDR)
492#define PGPUEN BYTE_REF(PGPUEN_ADDR)
493#define PGSEL BYTE_REF(PGSEL_ADDR)
494
495#define PG(x) (1 << (x))
496
497#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
498#define PG_A0 0x02 /* Use A0 as PG[1] */
499#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
500#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
501#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
502#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
503
504/**********
505 *
506 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
507 *
508 **********/
509
510/*
511 * PWM Control Register
512 */
513#define PWMC_ADDR 0xfffff500
514#define PWMC WORD_REF(PWMC_ADDR)
515
516#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
517#define PWMC_CLKSEL_SHIFT 0
518#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
519#define PWMC_REPEAT_SHIFT 2
520#define PWMC_EN 0x0010 /* Enable PWM */
521#define PMNC_FIFOAV 0x0020 /* FIFO Available */
522#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
523#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
524#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
525#define PWMC_PRESCALER_SHIFT 8
526#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
527
528/* '328-compatible definitions */
529#define PWMC_PWMEN PWMC_EN
530
531/*
532 * PWM Sample Register
533 */
534#define PWMS_ADDR 0xfffff502
535#define PWMS WORD_REF(PWMS_ADDR)
536
537/*
538 * PWM Period Register
539 */
540#define PWMP_ADDR 0xfffff504
541#define PWMP BYTE_REF(PWMP_ADDR)
542
543/*
544 * PWM Counter Register
545 */
546#define PWMCNT_ADDR 0xfffff505
547#define PWMCNT BYTE_REF(PWMCNT_ADDR)
548
549/**********
550 *
551 * 0xFFFFF6xx -- General-Purpose Timer
552 *
553 **********/
554
555/*
556 * Timer Control register
557 */
558#define TCTL_ADDR 0xfffff600
559#define TCTL WORD_REF(TCTL_ADDR)
560
561#define TCTL_TEN 0x0001 /* Timer Enable */
562#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
563#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
564#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
565#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
566#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
567#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
568#define TCTL_IRQEN 0x0010 /* IRQ Enable */
569#define TCTL_OM 0x0020 /* Output Mode */
570#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
571#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
572#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
573#define TCTL_FRR 0x0010 /* Free-Run Mode */
574
575/* '328-compatible definitions */
576#define TCTL1_ADDR TCTL_ADDR
577#define TCTL1 TCTL
578
579/*
580 * Timer Prescaler Register
581 */
582#define TPRER_ADDR 0xfffff602
583#define TPRER WORD_REF(TPRER_ADDR)
584
585/* '328-compatible definitions */
586#define TPRER1_ADDR TPRER_ADDR
587#define TPRER1 TPRER
588
589/*
590 * Timer Compare Register
591 */
592#define TCMP_ADDR 0xfffff604
593#define TCMP WORD_REF(TCMP_ADDR)
594
595/* '328-compatible definitions */
596#define TCMP1_ADDR TCMP_ADDR
597#define TCMP1 TCMP
598
599/*
600 * Timer Capture register
601 */
602#define TCR_ADDR 0xfffff606
603#define TCR WORD_REF(TCR_ADDR)
604
605/* '328-compatible definitions */
606#define TCR1_ADDR TCR_ADDR
607#define TCR1 TCR
608
609/*
610 * Timer Counter Register
611 */
612#define TCN_ADDR 0xfffff608
613#define TCN WORD_REF(TCN_ADDR)
614
615/* '328-compatible definitions */
616#define TCN1_ADDR TCN_ADDR
617#define TCN1 TCN
618
619/*
620 * Timer Status Register
621 */
622#define TSTAT_ADDR 0xfffff60a
623#define TSTAT WORD_REF(TSTAT_ADDR)
624
625#define TSTAT_COMP 0x0001 /* Compare Event occurred */
626#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
627
628/* '328-compatible definitions */
629#define TSTAT1_ADDR TSTAT_ADDR
630#define TSTAT1 TSTAT
631
632/**********
633 *
634 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
635 *
636 **********/
637
638/*
639 * SPIM Data Register
640 */
641#define SPIMDATA_ADDR 0xfffff800
642#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
643
644/*
645 * SPIM Control/Status Register
646 */
647#define SPIMCONT_ADDR 0xfffff802
648#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
649
650#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
651#define SPIMCONT_BIT_COUNT_SHIFT 0
652#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
653#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
654#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
655#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
656#define SPIMCONT_XCH 0x0100 /* Exchange */
657#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
658#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
659#define SPIMCONT_DATA_RATE_SHIFT 13
660
661/* '328-compatible definitions */
662#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
663#define SPIMCONT_SPIMEN SPIMCONT_ENABLE
664
665/**********
666 *
667 * 0xFFFFF9xx -- UART
668 *
669 **********/
670
671/*
672 * UART Status/Control Register
673 */
674#define USTCNT_ADDR 0xfffff900
675#define USTCNT WORD_REF(USTCNT_ADDR)
676
677#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
678#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
679#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
680#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
681#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
682#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
683#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
684#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
685#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
686#define USTCNT_STOP 0x0200 /* Stop bit transmission */
687#define USTCNT_ODD 0x0400 /* Odd Parity */
688#define USTCNT_PEN 0x0800 /* Parity Enable */
689#define USTCNT_CLKM 0x1000 /* Clock Mode Select */
690#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
691#define USTCNT_RXEN 0x4000 /* Receiver Enable */
692#define USTCNT_UEN 0x8000 /* UART Enable */
693
694/* '328-compatible definitions */
695#define USTCNT_TXAVAILEN USTCNT_TXAE
696#define USTCNT_TXHALFEN USTCNT_TXHE
697#define USTCNT_TXEMPTYEN USTCNT_TXEE
698#define USTCNT_RXREADYEN USTCNT_RXRE
699#define USTCNT_RXHALFEN USTCNT_RXHE
700#define USTCNT_RXFULLEN USTCNT_RXFE
701#define USTCNT_CTSDELTAEN USTCNT_CTSD
702#define USTCNT_ODD_EVEN USTCNT_ODD
703#define USTCNT_PARITYEN USTCNT_PEN
704#define USTCNT_CLKMODE USTCNT_CLKM
705#define USTCNT_UARTEN USTCNT_UEN
706
707/*
708 * UART Baud Control Register
709 */
710#define UBAUD_ADDR 0xfffff902
711#define UBAUD WORD_REF(UBAUD_ADDR)
712
713#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
714#define UBAUD_PRESCALER_SHIFT 0
715#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
716#define UBAUD_DIVIDE_SHIFT 8
717#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
718#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
719
720/*
721 * UART Receiver Register
722 */
723#define URX_ADDR 0xfffff904
724#define URX WORD_REF(URX_ADDR)
725
726#define URX_RXDATA_ADDR 0xfffff905
727#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
728
729#define URX_RXDATA_MASK 0x00ff /* Received data */
730#define URX_RXDATA_SHIFT 0
731#define URX_PARITY_ERROR 0x0100 /* Parity Error */
732#define URX_BREAK 0x0200 /* Break Detected */
733#define URX_FRAME_ERROR 0x0400 /* Framing Error */
734#define URX_OVRUN 0x0800 /* Serial Overrun */
735#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
736#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
737#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
738#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
739
740/*
741 * UART Transmitter Register
742 */
743#define UTX_ADDR 0xfffff906
744#define UTX WORD_REF(UTX_ADDR)
745
746#define UTX_TXDATA_ADDR 0xfffff907
747#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
748
749#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
750#define UTX_TXDATA_SHIFT 0
751#define UTX_CTS_DELTA 0x0100 /* CTS changed */
752#define UTX_CTS_STAT 0x0200 /* CTS State */
753#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
754#define UTX_NOCTS 0x0800 /* Ignore CTS */
755#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
756#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
757#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
758#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
759
760/* '328-compatible definitions */
761#define UTX_CTS_STATUS UTX_CTS_STAT
762#define UTX_IGNORE_CTS UTX_NOCTS
763
764/*
765 * UART Miscellaneous Register
766 */
767#define UMISC_ADDR 0xfffff908
768#define UMISC WORD_REF(UMISC_ADDR)
769
770#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
771#define UMISC_RX_POL 0x0008 /* Receive Polarity */
772#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
773#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
774#define UMISC_RTS 0x0040 /* Set RTS status */
775#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
776#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
777#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
778#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
779#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
780#define UMISC_CLKSRC 0x4000 /* Clock Source */
781#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
782
783/*
784 * UART Non-integer Prescaler Register
785 */
786#define NIPR_ADDR 0xfffff90a
787#define NIPR WORD_REF(NIPR_ADDR)
788
789#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
790#define NIPR_STEP_VALUE_SHIFT 0
791#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
792#define NIPR_SELECT_SHIFT 8
793#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
794
795
796/* generalization of uart control registers to support multiple ports: */
797typedef volatile struct {
798 volatile unsigned short int ustcnt;
799 volatile unsigned short int ubaud;
800 union {
801 volatile unsigned short int w;
802 struct {
803 volatile unsigned char status;
804 volatile unsigned char rxdata;
805 } b;
806 } urx;
807 union {
808 volatile unsigned short int w;
809 struct {
810 volatile unsigned char status;
811 volatile unsigned char txdata;
812 } b;
813 } utx;
814 volatile unsigned short int umisc;
815 volatile unsigned short int nipr;
816 volatile unsigned short int pad1;
817 volatile unsigned short int pad2;
818} __attribute__((packed)) m68328_uart;
819
820
821/**********
822 *
823 * 0xFFFFFAxx -- LCD Controller
824 *
825 **********/
826
827/*
828 * LCD Screen Starting Address Register
829 */
830#define LSSA_ADDR 0xfffffa00
831#define LSSA LONG_REF(LSSA_ADDR)
832
833#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
834
835/*
836 * LCD Virtual Page Width Register
837 */
838#define LVPW_ADDR 0xfffffa05
839#define LVPW BYTE_REF(LVPW_ADDR)
840
841/*
842 * LCD Screen Width Register (not compatible with '328 !!!)
843 */
844#define LXMAX_ADDR 0xfffffa08
845#define LXMAX WORD_REF(LXMAX_ADDR)
846
847#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
848
849/*
850 * LCD Screen Height Register
851 */
852#define LYMAX_ADDR 0xfffffa0a
853#define LYMAX WORD_REF(LYMAX_ADDR)
854
855#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
856
857/*
858 * LCD Cursor X Position Register
859 */
860#define LCXP_ADDR 0xfffffa18
861#define LCXP WORD_REF(LCXP_ADDR)
862
863#define LCXP_CC_MASK 0xc000 /* Cursor Control */
864#define LCXP_CC_TRAMSPARENT 0x0000
865#define LCXP_CC_BLACK 0x4000
866#define LCXP_CC_REVERSED 0x8000
867#define LCXP_CC_WHITE 0xc000
868#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
869
870/*
871 * LCD Cursor Y Position Register
872 */
873#define LCYP_ADDR 0xfffffa1a
874#define LCYP WORD_REF(LCYP_ADDR)
875
876#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
877
878/*
879 * LCD Cursor Width and Heigth Register
880 */
881#define LCWCH_ADDR 0xfffffa1c
882#define LCWCH WORD_REF(LCWCH_ADDR)
883
884#define LCWCH_CH_MASK 0x001f /* Cursor Height */
885#define LCWCH_CH_SHIFT 0
886#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
887#define LCWCH_CW_SHIFT 8
888
889/*
890 * LCD Blink Control Register
891 */
892#define LBLKC_ADDR 0xfffffa1f
893#define LBLKC BYTE_REF(LBLKC_ADDR)
894
895#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
896#define LBLKC_BD_SHIFT 0
897#define LBLKC_BKEN 0x80 /* Blink Enabled */
898
899/*
900 * LCD Panel Interface Configuration Register
901 */
902#define LPICF_ADDR 0xfffffa20
903#define LPICF BYTE_REF(LPICF_ADDR)
904
905#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
906#define LPICF_GS_BW 0x00
907#define LPICF_GS_GRAY_4 0x01
908#define LPICF_GS_GRAY_16 0x02
909#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
910#define LPICF_PBSIZ_1 0x00
911#define LPICF_PBSIZ_2 0x04
912#define LPICF_PBSIZ_4 0x08
913
914/*
915 * LCD Polarity Configuration Register
916 */
917#define LPOLCF_ADDR 0xfffffa21
918#define LPOLCF BYTE_REF(LPOLCF_ADDR)
919
920#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
921#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
922#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
923#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
924
925/*
926 * LACD (LCD Alternate Crystal Direction) Rate Control Register
927 */
928#define LACDRC_ADDR 0xfffffa23
929#define LACDRC BYTE_REF(LACDRC_ADDR)
930
931#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
932#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
933#define LACDRC_ACD_SHIFT 0
934
935/*
936 * LCD Pixel Clock Divider Register
937 */
938#define LPXCD_ADDR 0xfffffa25
939#define LPXCD BYTE_REF(LPXCD_ADDR)
940
941#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
942#define LPXCD_PCD_SHIFT 0
943
944/*
945 * LCD Clocking Control Register
946 */
947#define LCKCON_ADDR 0xfffffa27
948#define LCKCON BYTE_REF(LCKCON_ADDR)
949
950#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
951#define LCKCON_DWS_SHIFT 0
952#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
953#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
954
955/* '328-compatible definitions */
956#define LCKCON_DW_MASK LCKCON_DWS_MASK
957#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
958
959/*
960 * LCD Refresh Rate Adjustment Register
961 */
962#define LRRA_ADDR 0xfffffa29
963#define LRRA BYTE_REF(LRRA_ADDR)
964
965/*
966 * LCD Panning Offset Register
967 */
968#define LPOSR_ADDR 0xfffffa2d
969#define LPOSR BYTE_REF(LPOSR_ADDR)
970
971#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
972#define LPOSR_POS_SHIFT 0
973
974/*
975 * LCD Frame Rate Control Modulation Register
976 */
977#define LFRCM_ADDR 0xfffffa31
978#define LFRCM BYTE_REF(LFRCM_ADDR)
979
980#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
981#define LFRCM_YMOD_SHIFT 0
982#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
983#define LFRCM_XMOD_SHIFT 4
984
985/*
986 * LCD Gray Palette Mapping Register
987 */
988#define LGPMR_ADDR 0xfffffa33
989#define LGPMR BYTE_REF(LGPMR_ADDR)
990
991#define LGPMR_G1_MASK 0x0f
992#define LGPMR_G1_SHIFT 0
993#define LGPMR_G2_MASK 0xf0
994#define LGPMR_G2_SHIFT 4
995
996/*
997 * PWM Contrast Control Register
998 */
999#define PWMR_ADDR 0xfffffa36
1000#define PWMR WORD_REF(PWMR_ADDR)
1001
1002#define PWMR_PW_MASK 0x00ff /* Pulse Width */
1003#define PWMR_PW_SHIFT 0
1004#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
1005#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1006#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
1007#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1008#define PWMR_SRC_LCD 0x4000 /* LCD clock */
1009
1010/**********
1011 *
1012 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1013 *
1014 **********/
1015
1016/*
1017 * RTC Hours Minutes and Seconds Register
1018 */
1019#define RTCTIME_ADDR 0xfffffb00
1020#define RTCTIME LONG_REF(RTCTIME_ADDR)
1021
1022#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1023#define RTCTIME_SECONDS_SHIFT 0
1024#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1025#define RTCTIME_MINUTES_SHIFT 16
1026#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1027#define RTCTIME_HOURS_SHIFT 24
1028
1029/*
1030 * RTC Alarm Register
1031 */
1032#define RTCALRM_ADDR 0xfffffb04
1033#define RTCALRM LONG_REF(RTCALRM_ADDR)
1034
1035#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1036#define RTCALRM_SECONDS_SHIFT 0
1037#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1038#define RTCALRM_MINUTES_SHIFT 16
1039#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1040#define RTCALRM_HOURS_SHIFT 24
1041
1042/*
1043 * Watchdog Timer Register
1044 */
1045#define WATCHDOG_ADDR 0xfffffb0a
1046#define WATCHDOG WORD_REF(WATCHDOG_ADDR)
1047
1048#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
1049#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
1050#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */
1051#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
1052#define WATCHDOG_CNT_SHIFT 8
1053
1054/*
1055 * RTC Control Register
1056 */
1057#define RTCCTL_ADDR 0xfffffb0c
1058#define RTCCTL WORD_REF(RTCCTL_ADDR)
1059
1060#define RTCCTL_XTL 0x0020 /* Crystal Selection */
1061#define RTCCTL_EN 0x0080 /* RTC Enable */
1062
1063/* '328-compatible definitions */
1064#define RTCCTL_384 RTCCTL_XTL
1065#define RTCCTL_ENABLE RTCCTL_EN
1066
1067/*
1068 * RTC Interrupt Status Register
1069 */
1070#define RTCISR_ADDR 0xfffffb0e
1071#define RTCISR WORD_REF(RTCISR_ADDR)
1072
1073#define RTCISR_SW 0x0001 /* Stopwatch timed out */
1074#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1075#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1076#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1077#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1078#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1079#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
1080#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
1081#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
1082#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
1083#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
1084#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
1085#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
1086#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
1087
1088/*
1089 * RTC Interrupt Enable Register
1090 */
1091#define RTCIENR_ADDR 0xfffffb10
1092#define RTCIENR WORD_REF(RTCIENR_ADDR)
1093
1094#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1095#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1096#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1097#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1098#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1099#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1100#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
1101#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
1102#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
1103#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
1104#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
1105#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
1106#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
1107#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
1108
1109/*
1110 * Stopwatch Minutes Register
1111 */
1112#define STPWCH_ADDR 0xfffffb12
1113#define STPWCH WORD_REF(STPWCH)
1114
1115#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
1116#define SPTWCH_CNT_SHIFT 0
1117
1118/*
1119 * RTC Day Count Register
1120 */
1121#define DAYR_ADDR 0xfffffb1a
1122#define DAYR WORD_REF(DAYR_ADDR)
1123
1124#define DAYR_DAYS_MASK 0x1ff /* Day Setting */
1125#define DAYR_DAYS_SHIFT 0
1126
1127/*
1128 * RTC Day Alarm Register
1129 */
1130#define DAYALARM_ADDR 0xfffffb1c
1131#define DAYALARM WORD_REF(DAYALARM_ADDR)
1132
1133#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
1134#define DAYALARM_DAYSAL_SHIFT 0
1135
1136/**********
1137 *
1138 * 0xFFFFFCxx -- DRAM Controller
1139 *
1140 **********/
1141
1142/*
1143 * DRAM Memory Configuration Register
1144 */
1145#define DRAMMC_ADDR 0xfffffc00
1146#define DRAMMC WORD_REF(DRAMMC_ADDR)
1147
1148#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
1149#define DRAMMC_ROW12_PA10 0x0000
1150#define DRAMMC_ROW12_PA21 0x4000
1151#define DRAMMC_ROW12_PA23 0x8000
1152#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
1153#define DRAMMC_ROW0_PA11 0x0000
1154#define DRAMMC_ROW0_PA22 0x1000
1155#define DRAMMC_ROW0_PA23 0x2000
1156#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
1157#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
1158#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
1159#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
1160#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
1161#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
1162#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
1163#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */
1164#define DRAMMC_REF_SHIFT 0
1165
1166/*
1167 * DRAM Control Register
1168 */
1169#define DRAMC_ADDR 0xfffffc02
1170#define DRAMC WORD_REF(DRAMC_ADDR)
1171
1172#define DRAMC_DWE 0x0001 /* DRAM Write Enable */
1173#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
1174#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1175#define DRAMC_SLW 0x0008 /* Slow RAM */
1176#define DRAMC_LSP 0x0010 /* Light Sleep */
1177#define DRAMC_MSW 0x0020 /* Slow Multiplexing */
1178#define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1179#define DRAMC_WS_SHIFT 6
1180#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
1181#define DRAMC_PGSZ_SHIFT 8
1182#define DRAMC_PGSZ_256K 0x0000
1183#define DRAMC_PGSZ_512K 0x0100
1184#define DRAMC_PGSZ_1024K 0x0200
1185#define DRAMC_PGSZ_2048K 0x0300
1186#define DRAMC_EDO 0x0400 /* EDO DRAM */
1187#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1188#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
1189#define DRAMC_BC_SHIFT 12
1190#define DRAMC_RM 0x4000 /* Refresh Mode */
1191#define DRAMC_EN 0x8000 /* DRAM Controller enable */
1192
1193
1194/**********
1195 *
1196 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1197 *
1198 **********/
1199
1200/*
1201 * ICE Module Address Compare Register
1202 */
1203#define ICEMACR_ADDR 0xfffffd00
1204#define ICEMACR LONG_REF(ICEMACR_ADDR)
1205
1206/*
1207 * ICE Module Address Mask Register
1208 */
1209#define ICEMAMR_ADDR 0xfffffd04
1210#define ICEMAMR LONG_REF(ICEMAMR_ADDR)
1211
1212/*
1213 * ICE Module Control Compare Register
1214 */
1215#define ICEMCCR_ADDR 0xfffffd08
1216#define ICEMCCR WORD_REF(ICEMCCR_ADDR)
1217
1218#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
1219#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
1220
1221/*
1222 * ICE Module Control Mask Register
1223 */
1224#define ICEMCMR_ADDR 0xfffffd0a
1225#define ICEMCMR WORD_REF(ICEMCMR_ADDR)
1226
1227#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
1228#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
1229
1230/*
1231 * ICE Module Control Register
1232 */
1233#define ICEMCR_ADDR 0xfffffd0c
1234#define ICEMCR WORD_REF(ICEMCR_ADDR)
1235
1236#define ICEMCR_CEN 0x0001 /* Compare Enable */
1237#define ICEMCR_PBEN 0x0002 /* Program Break Enable */
1238#define ICEMCR_SB 0x0004 /* Single Breakpoint */
1239#define ICEMCR_HMDIS 0x0008 /* HardMap disable */
1240#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
1241
1242/*
1243 * ICE Module Status Register
1244 */
1245#define ICEMSR_ADDR 0xfffffd0e
1246#define ICEMSR WORD_REF(ICEMSR_ADDR)
1247
1248#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
1249#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
1250#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
1251#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
1252
1253#endif /* _MC68EZ328_H_ */
diff --git a/arch/m68knommu/include/asm/MC68VZ328.h b/arch/m68knommu/include/asm/MC68VZ328.h
new file mode 100644
index 000000000000..2b9bf626a0a5
--- /dev/null
+++ b/arch/m68knommu/include/asm/MC68VZ328.h
@@ -0,0 +1,1349 @@
1
2/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
3 *
4 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
5 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
6 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
7 * Bare & Hare Software, Inc.
8 * Based on include/asm-m68knommu/MC68332.h
9 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 *
12 * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
13 * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
14 */
15
16#ifndef _MC68VZ328_H_
17#define _MC68VZ328_H_
18
19#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
20#define WORD_REF(addr) (*((volatile unsigned short*)addr))
21#define LONG_REF(addr) (*((volatile unsigned long*)addr))
22
23#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
24#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
25
26/**********
27 *
28 * 0xFFFFF0xx -- System Control
29 *
30 **********/
31
32/*
33 * System Control Register (SCR)
34 */
35#define SCR_ADDR 0xfffff000
36#define SCR BYTE_REF(SCR_ADDR)
37
38#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39#define SCR_DMAP 0x04 /* Double Map */
40#define SCR_SO 0x08 /* Supervisor Only */
41#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42#define SCR_PRV 0x20 /* Privilege Violation */
43#define SCR_WPV 0x40 /* Write Protect Violation */
44#define SCR_BETO 0x80 /* Bus-Error TimeOut */
45
46/*
47 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
48 */
49#define MRR_ADDR 0xfffff004
50#define MRR LONG_REF(MRR_ADDR)
51
52/**********
53 *
54 * 0xFFFFF1xx -- Chip-Select logic
55 *
56 **********/
57
58/*
59 * Chip Select Group Base Registers
60 */
61#define CSGBA_ADDR 0xfffff100
62#define CSGBB_ADDR 0xfffff102
63
64#define CSGBC_ADDR 0xfffff104
65#define CSGBD_ADDR 0xfffff106
66
67#define CSGBA WORD_REF(CSGBA_ADDR)
68#define CSGBB WORD_REF(CSGBB_ADDR)
69#define CSGBC WORD_REF(CSGBC_ADDR)
70#define CSGBD WORD_REF(CSGBD_ADDR)
71
72/*
73 * Chip Select Registers
74 */
75#define CSA_ADDR 0xfffff110
76#define CSB_ADDR 0xfffff112
77#define CSC_ADDR 0xfffff114
78#define CSD_ADDR 0xfffff116
79
80#define CSA WORD_REF(CSA_ADDR)
81#define CSB WORD_REF(CSB_ADDR)
82#define CSC WORD_REF(CSC_ADDR)
83#define CSD WORD_REF(CSD_ADDR)
84
85#define CSA_EN 0x0001 /* Chip-Select Enable */
86#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
87#define CSA_SIZ_SHIFT 1
88#define CSA_WS_MASK 0x0070 /* Wait State */
89#define CSA_WS_SHIFT 4
90#define CSA_BSW 0x0080 /* Data Bus Width */
91#define CSA_FLASH 0x0100 /* FLASH Memory Support */
92#define CSA_RO 0x8000 /* Read-Only */
93
94#define CSB_EN 0x0001 /* Chip-Select Enable */
95#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
96#define CSB_SIZ_SHIFT 1
97#define CSB_WS_MASK 0x0070 /* Wait State */
98#define CSB_WS_SHIFT 4
99#define CSB_BSW 0x0080 /* Data Bus Width */
100#define CSB_FLASH 0x0100 /* FLASH Memory Support */
101#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
102#define CSB_UPSIZ_SHIFT 11
103#define CSB_ROP 0x2000 /* Readonly if protected */
104#define CSB_SOP 0x4000 /* Supervisor only if protected */
105#define CSB_RO 0x8000 /* Read-Only */
106
107#define CSC_EN 0x0001 /* Chip-Select Enable */
108#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
109#define CSC_SIZ_SHIFT 1
110#define CSC_WS_MASK 0x0070 /* Wait State */
111#define CSC_WS_SHIFT 4
112#define CSC_BSW 0x0080 /* Data Bus Width */
113#define CSC_FLASH 0x0100 /* FLASH Memory Support */
114#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
115#define CSC_UPSIZ_SHIFT 11
116#define CSC_ROP 0x2000 /* Readonly if protected */
117#define CSC_SOP 0x4000 /* Supervisor only if protected */
118#define CSC_RO 0x8000 /* Read-Only */
119
120#define CSD_EN 0x0001 /* Chip-Select Enable */
121#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
122#define CSD_SIZ_SHIFT 1
123#define CSD_WS_MASK 0x0070 /* Wait State */
124#define CSD_WS_SHIFT 4
125#define CSD_BSW 0x0080 /* Data Bus Width */
126#define CSD_FLASH 0x0100 /* FLASH Memory Support */
127#define CSD_DRAM 0x0200 /* Dram Selection */
128#define CSD_COMB 0x0400 /* Combining */
129#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
130#define CSD_UPSIZ_SHIFT 11
131#define CSD_ROP 0x2000 /* Readonly if protected */
132#define CSD_SOP 0x4000 /* Supervisor only if protected */
133#define CSD_RO 0x8000 /* Read-Only */
134
135/*
136 * Emulation Chip-Select Register
137 */
138#define EMUCS_ADDR 0xfffff118
139#define EMUCS WORD_REF(EMUCS_ADDR)
140
141#define EMUCS_WS_MASK 0x0070
142#define EMUCS_WS_SHIFT 4
143
144/**********
145 *
146 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
147 *
148 **********/
149
150/*
151 * PLL Control Register
152 */
153#define PLLCR_ADDR 0xfffff200
154#define PLLCR WORD_REF(PLLCR_ADDR)
155
156#define PLLCR_DISPLL 0x0008 /* Disable PLL */
157#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
158#define PLLCR_PRESC 0x0020 /* VCO prescaler */
159#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
160#define PLLCR_SYSCLK_SEL_SHIFT 8
161#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
162#define PLLCR_LCDCLK_SEL_SHIFT 11
163
164/* '328-compatible definitions */
165#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
166#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
167
168/*
169 * PLL Frequency Select Register
170 */
171#define PLLFSR_ADDR 0xfffff202
172#define PLLFSR WORD_REF(PLLFSR_ADDR)
173
174#define PLLFSR_PC_MASK 0x00ff /* P Count */
175#define PLLFSR_PC_SHIFT 0
176#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
177#define PLLFSR_QC_SHIFT 8
178#define PLLFSR_PROT 0x4000 /* Protect P & Q */
179#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
180
181/*
182 * Power Control Register
183 */
184#define PCTRL_ADDR 0xfffff207
185#define PCTRL BYTE_REF(PCTRL_ADDR)
186
187#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
188#define PCTRL_WIDTH_SHIFT 0
189#define PCTRL_PCEN 0x80 /* Power Control Enable */
190
191/**********
192 *
193 * 0xFFFFF3xx -- Interrupt Controller
194 *
195 **********/
196
197/*
198 * Interrupt Vector Register
199 */
200#define IVR_ADDR 0xfffff300
201#define IVR BYTE_REF(IVR_ADDR)
202
203#define IVR_VECTOR_MASK 0xF8
204
205/*
206 * Interrupt control Register
207 */
208#define ICR_ADDR 0xfffff302
209#define ICR WORD_REF(ICR_ADDR)
210
211#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
212#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
213#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
214#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
215#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
216#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
217#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
218#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
219#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
220
221/*
222 * Interrupt Mask Register
223 */
224#define IMR_ADDR 0xfffff304
225#define IMR LONG_REF(IMR_ADDR)
226
227/*
228 * Define the names for bit positions first. This is useful for
229 * request_irq
230 */
231#define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */
232#define TMR_IRQ_NUM 1 /* Timer 1 interrupt */
233#define UART1_IRQ_NUM 2 /* UART 1 interrupt */
234#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
235#define RTC_IRQ_NUM 4 /* RTC interrupt */
236#define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */
237#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
238#define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
239#define INT0_IRQ_NUM 8 /* External INT0 */
240#define INT1_IRQ_NUM 9 /* External INT1 */
241#define INT2_IRQ_NUM 10 /* External INT2 */
242#define INT3_IRQ_NUM 11 /* External INT3 */
243#define UART2_IRQ_NUM 12 /* UART 2 interrupt */
244#define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
245#define IRQ1_IRQ_NUM 16 /* IRQ1 */
246#define IRQ2_IRQ_NUM 17 /* IRQ2 */
247#define IRQ3_IRQ_NUM 18 /* IRQ3 */
248#define IRQ6_IRQ_NUM 19 /* IRQ6 */
249#define IRQ5_IRQ_NUM 20 /* IRQ5 */
250#define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */
251#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
252#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
253
254#define SPI_IRQ_NUM SPI2_IRQ_NUM
255
256/* '328-compatible definitions */
257#define SPIM_IRQ_NUM SPI_IRQ_NUM
258#define TMR1_IRQ_NUM TMR_IRQ_NUM
259#define UART_IRQ_NUM UART1_IRQ_NUM
260
261/*
262 * Here go the bitmasks themselves
263 */
264#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
265#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
266#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
267#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
268#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
269#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
270#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
271#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
272#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
273#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
274#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
275#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
276#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
277#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
278#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
279#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
280#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
281#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
282
283/* '328-compatible definitions */
284#define IMR_MSPIM IMR_MSPI
285#define IMR_MTMR1 IMR_MTMR
286
287/*
288 * Interrupt Status Register
289 */
290#define ISR_ADDR 0xfffff30c
291#define ISR LONG_REF(ISR_ADDR)
292
293#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
294#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
295#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
296#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
297#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
298#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
299#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
300#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
301#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
302#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
303#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
304#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
305#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
306#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
307#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
308#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
309#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
310#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
311
312/* '328-compatible definitions */
313#define ISR_SPIM ISR_SPI
314#define ISR_TMR1 ISR_TMR
315
316/*
317 * Interrupt Pending Register
318 */
319#define IPR_ADDR 0xfffff30c
320#define IPR LONG_REF(IPR_ADDR)
321
322#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
323#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
324#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
325#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
326#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
327#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
328#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
329#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
330#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
331#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
332#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
333#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
334#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
335#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
336#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
337#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
338#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
339#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
340
341/* '328-compatible definitions */
342#define IPR_SPIM IPR_SPI
343#define IPR_TMR1 IPR_TMR
344
345/**********
346 *
347 * 0xFFFFF4xx -- Parallel Ports
348 *
349 **********/
350
351/*
352 * Port A
353 */
354#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
355#define PADATA_ADDR 0xfffff401 /* Port A data register */
356#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
357
358#define PADIR BYTE_REF(PADIR_ADDR)
359#define PADATA BYTE_REF(PADATA_ADDR)
360#define PAPUEN BYTE_REF(PAPUEN_ADDR)
361
362#define PA(x) (1 << (x))
363
364/*
365 * Port B
366 */
367#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
368#define PBDATA_ADDR 0xfffff409 /* Port B data register */
369#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
370#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
371
372#define PBDIR BYTE_REF(PBDIR_ADDR)
373#define PBDATA BYTE_REF(PBDATA_ADDR)
374#define PBPUEN BYTE_REF(PBPUEN_ADDR)
375#define PBSEL BYTE_REF(PBSEL_ADDR)
376
377#define PB(x) (1 << (x))
378
379#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
380#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
381#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
382#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
383#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
384#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
385#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
386#define PB_PWMO 0x80 /* Use PWMO as PB[7] */
387
388/*
389 * Port C
390 */
391#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
392#define PCDATA_ADDR 0xfffff411 /* Port C data register */
393#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
394#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
395
396#define PCDIR BYTE_REF(PCDIR_ADDR)
397#define PCDATA BYTE_REF(PCDATA_ADDR)
398#define PCPDEN BYTE_REF(PCPDEN_ADDR)
399#define PCSEL BYTE_REF(PCSEL_ADDR)
400
401#define PC(x) (1 << (x))
402
403#define PC_LD0 0x01 /* Use LD0 as PC[0] */
404#define PC_LD1 0x02 /* Use LD1 as PC[1] */
405#define PC_LD2 0x04 /* Use LD2 as PC[2] */
406#define PC_LD3 0x08 /* Use LD3 as PC[3] */
407#define PC_LFLM 0x10 /* Use LFLM as PC[4] */
408#define PC_LLP 0x20 /* Use LLP as PC[5] */
409#define PC_LCLK 0x40 /* Use LCLK as PC[6] */
410#define PC_LACD 0x80 /* Use LACD as PC[7] */
411
412/*
413 * Port D
414 */
415#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
416#define PDDATA_ADDR 0xfffff419 /* Port D data register */
417#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
418#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
419#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
420#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
421#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
422#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
423
424#define PDDIR BYTE_REF(PDDIR_ADDR)
425#define PDDATA BYTE_REF(PDDATA_ADDR)
426#define PDPUEN BYTE_REF(PDPUEN_ADDR)
427#define PDSEL BYTE_REF(PDSEL_ADDR)
428#define PDPOL BYTE_REF(PDPOL_ADDR)
429#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
430#define PDKBEN BYTE_REF(PDKBEN_ADDR)
431#define PDIQEG BYTE_REF(PDIQEG_ADDR)
432
433#define PD(x) (1 << (x))
434
435#define PD_INT0 0x01 /* Use INT0 as PD[0] */
436#define PD_INT1 0x02 /* Use INT1 as PD[1] */
437#define PD_INT2 0x04 /* Use INT2 as PD[2] */
438#define PD_INT3 0x08 /* Use INT3 as PD[3] */
439#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
440#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
441#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
442#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
443
444/*
445 * Port E
446 */
447#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
448#define PEDATA_ADDR 0xfffff421 /* Port E data register */
449#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
450#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
451
452#define PEDIR BYTE_REF(PEDIR_ADDR)
453#define PEDATA BYTE_REF(PEDATA_ADDR)
454#define PEPUEN BYTE_REF(PEPUEN_ADDR)
455#define PESEL BYTE_REF(PESEL_ADDR)
456
457#define PE(x) (1 << (x))
458
459#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
460#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
461#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
462#define PE_DWE 0x08 /* Use DWE as PE[3] */
463#define PE_RXD 0x10 /* Use RXD as PE[4] */
464#define PE_TXD 0x20 /* Use TXD as PE[5] */
465#define PE_RTS 0x40 /* Use RTS as PE[6] */
466#define PE_CTS 0x80 /* Use CTS as PE[7] */
467
468/*
469 * Port F
470 */
471#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
472#define PFDATA_ADDR 0xfffff429 /* Port F data register */
473#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
474#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
475
476#define PFDIR BYTE_REF(PFDIR_ADDR)
477#define PFDATA BYTE_REF(PFDATA_ADDR)
478#define PFPUEN BYTE_REF(PFPUEN_ADDR)
479#define PFSEL BYTE_REF(PFSEL_ADDR)
480
481#define PF(x) (1 << (x))
482
483#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
484#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
485#define PF_CLKO 0x04 /* Use CLKO as PF[2] */
486#define PF_A20 0x08 /* Use A20 as PF[3] */
487#define PF_A21 0x10 /* Use A21 as PF[4] */
488#define PF_A22 0x20 /* Use A22 as PF[5] */
489#define PF_A23 0x40 /* Use A23 as PF[6] */
490#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
491
492/*
493 * Port G
494 */
495#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
496#define PGDATA_ADDR 0xfffff431 /* Port G data register */
497#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
498#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
499
500#define PGDIR BYTE_REF(PGDIR_ADDR)
501#define PGDATA BYTE_REF(PGDATA_ADDR)
502#define PGPUEN BYTE_REF(PGPUEN_ADDR)
503#define PGSEL BYTE_REF(PGSEL_ADDR)
504
505#define PG(x) (1 << (x))
506
507#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
508#define PG_A0 0x02 /* Use A0 as PG[1] */
509#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
510#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
511#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
512#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
513
514/*
515 * Port J
516 */
517#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
518#define PJDATA_ADDR 0xfffff439 /* Port J data register */
519#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
520#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
521
522#define PJDIR BYTE_REF(PJDIR_ADDR)
523#define PJDATA BYTE_REF(PJDATA_ADDR)
524#define PJPUEN BYTE_REF(PJPUEN_ADDR)
525#define PJSEL BYTE_REF(PJSEL_ADDR)
526
527#define PJ(x) (1 << (x))
528
529/*
530 * Port K
531 */
532#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
533#define PKDATA_ADDR 0xfffff441 /* Port K data register */
534#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
535#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
536
537#define PKDIR BYTE_REF(PKDIR_ADDR)
538#define PKDATA BYTE_REF(PKDATA_ADDR)
539#define PKPUEN BYTE_REF(PKPUEN_ADDR)
540#define PKSEL BYTE_REF(PKSEL_ADDR)
541
542#define PK(x) (1 << (x))
543
544#define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
545#define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
546#define PK_R_W 0x02 /* Use R/W as PK[1] */
547#define PK_LDS 0x04 /* Use /LDS as PK[2] */
548#define PK_UDS 0x08 /* Use /UDS as PK[3] */
549#define PK_LD4 0x10 /* Use LD4 as PK[4] */
550#define PK_LD5 0x20 /* Use LD5 as PK[5] */
551#define PK_LD6 0x40 /* Use LD6 as PK[6] */
552#define PK_LD7 0x80 /* Use LD7 as PK[7] */
553
554#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
555#define PJDATA_ADDR 0xfffff439 /* Port J data register */
556#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
557#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
558
559#define PJDIR BYTE_REF(PJDIR_ADDR)
560#define PJDATA BYTE_REF(PJDATA_ADDR)
561#define PJPUEN BYTE_REF(PJPUEN_ADDR)
562#define PJSEL BYTE_REF(PJSEL_ADDR)
563
564#define PJ(x) (1 << (x))
565
566#define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
567#define PJ_MISO 0x02 /* Use MISO as PJ[1] */
568#define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
569#define PJ_SS 0x08 /* Use SS as PJ[3] */
570#define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
571#define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
572#define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
573#define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
574
575/*
576 * Port M
577 */
578#define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
579#define PMDATA_ADDR 0xfffff449 /* Port M data register */
580#define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
581#define PMSEL_ADDR 0xfffff44b /* Port M Select Register */
582
583#define PMDIR BYTE_REF(PMDIR_ADDR)
584#define PMDATA BYTE_REF(PMDATA_ADDR)
585#define PMPUEN BYTE_REF(PMPUEN_ADDR)
586#define PMSEL BYTE_REF(PMSEL_ADDR)
587
588#define PM(x) (1 << (x))
589
590#define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
591#define PM_SDCE 0x02 /* Use SDCE as PM[1] */
592#define PM_DQMH 0x04 /* Use DQMH as PM[2] */
593#define PM_DQML 0x08 /* Use DQML as PM[3] */
594#define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
595#define PM_DMOE 0x20 /* Use DMOE as PM[5] */
596
597/**********
598 *
599 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
600 *
601 **********/
602
603/*
604 * PWM Control Register
605 */
606#define PWMC_ADDR 0xfffff500
607#define PWMC WORD_REF(PWMC_ADDR)
608
609#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
610#define PWMC_CLKSEL_SHIFT 0
611#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
612#define PWMC_REPEAT_SHIFT 2
613#define PWMC_EN 0x0010 /* Enable PWM */
614#define PMNC_FIFOAV 0x0020 /* FIFO Available */
615#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
616#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
617#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
618#define PWMC_PRESCALER_SHIFT 8
619#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
620
621/* '328-compatible definitions */
622#define PWMC_PWMEN PWMC_EN
623
624/*
625 * PWM Sample Register
626 */
627#define PWMS_ADDR 0xfffff502
628#define PWMS WORD_REF(PWMS_ADDR)
629
630/*
631 * PWM Period Register
632 */
633#define PWMP_ADDR 0xfffff504
634#define PWMP BYTE_REF(PWMP_ADDR)
635
636/*
637 * PWM Counter Register
638 */
639#define PWMCNT_ADDR 0xfffff505
640#define PWMCNT BYTE_REF(PWMCNT_ADDR)
641
642/**********
643 *
644 * 0xFFFFF6xx -- General-Purpose Timer
645 *
646 **********/
647
648/*
649 * Timer Control register
650 */
651#define TCTL_ADDR 0xfffff600
652#define TCTL WORD_REF(TCTL_ADDR)
653
654#define TCTL_TEN 0x0001 /* Timer Enable */
655#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
656#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
657#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
658#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
659#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
660#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
661#define TCTL_IRQEN 0x0010 /* IRQ Enable */
662#define TCTL_OM 0x0020 /* Output Mode */
663#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
664#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
665#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
666#define TCTL_FRR 0x0010 /* Free-Run Mode */
667
668/* '328-compatible definitions */
669#define TCTL1_ADDR TCTL_ADDR
670#define TCTL1 TCTL
671
672/*
673 * Timer Prescaler Register
674 */
675#define TPRER_ADDR 0xfffff602
676#define TPRER WORD_REF(TPRER_ADDR)
677
678/* '328-compatible definitions */
679#define TPRER1_ADDR TPRER_ADDR
680#define TPRER1 TPRER
681
682/*
683 * Timer Compare Register
684 */
685#define TCMP_ADDR 0xfffff604
686#define TCMP WORD_REF(TCMP_ADDR)
687
688/* '328-compatible definitions */
689#define TCMP1_ADDR TCMP_ADDR
690#define TCMP1 TCMP
691
692/*
693 * Timer Capture register
694 */
695#define TCR_ADDR 0xfffff606
696#define TCR WORD_REF(TCR_ADDR)
697
698/* '328-compatible definitions */
699#define TCR1_ADDR TCR_ADDR
700#define TCR1 TCR
701
702/*
703 * Timer Counter Register
704 */
705#define TCN_ADDR 0xfffff608
706#define TCN WORD_REF(TCN_ADDR)
707
708/* '328-compatible definitions */
709#define TCN1_ADDR TCN_ADDR
710#define TCN1 TCN
711
712/*
713 * Timer Status Register
714 */
715#define TSTAT_ADDR 0xfffff60a
716#define TSTAT WORD_REF(TSTAT_ADDR)
717
718#define TSTAT_COMP 0x0001 /* Compare Event occurred */
719#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
720
721/* '328-compatible definitions */
722#define TSTAT1_ADDR TSTAT_ADDR
723#define TSTAT1 TSTAT
724
725/**********
726 *
727 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
728 *
729 **********/
730
731/*
732 * SPIM Data Register
733 */
734#define SPIMDATA_ADDR 0xfffff800
735#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
736
737/*
738 * SPIM Control/Status Register
739 */
740#define SPIMCONT_ADDR 0xfffff802
741#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
742
743#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
744#define SPIMCONT_BIT_COUNT_SHIFT 0
745#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
746#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
747#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
748#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
749#define SPIMCONT_XCH 0x0100 /* Exchange */
750#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
751#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
752#define SPIMCONT_DATA_RATE_SHIFT 13
753
754/* '328-compatible definitions */
755#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
756#define SPIMCONT_SPIMEN SPIMCONT_ENABLE
757
758/**********
759 *
760 * 0xFFFFF9xx -- UART
761 *
762 **********/
763
764/*
765 * UART Status/Control Register
766 */
767
768#define USTCNT_ADDR 0xfffff900
769#define USTCNT WORD_REF(USTCNT_ADDR)
770
771#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
772#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
773#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
774#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
775#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
776#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
777#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
778#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
779#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
780#define USTCNT_STOP 0x0200 /* Stop bit transmission */
781#define USTCNT_ODD 0x0400 /* Odd Parity */
782#define USTCNT_PEN 0x0800 /* Parity Enable */
783#define USTCNT_CLKM 0x1000 /* Clock Mode Select */
784#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
785#define USTCNT_RXEN 0x4000 /* Receiver Enable */
786#define USTCNT_UEN 0x8000 /* UART Enable */
787
788/* '328-compatible definitions */
789#define USTCNT_TXAVAILEN USTCNT_TXAE
790#define USTCNT_TXHALFEN USTCNT_TXHE
791#define USTCNT_TXEMPTYEN USTCNT_TXEE
792#define USTCNT_RXREADYEN USTCNT_RXRE
793#define USTCNT_RXHALFEN USTCNT_RXHE
794#define USTCNT_RXFULLEN USTCNT_RXFE
795#define USTCNT_CTSDELTAEN USTCNT_CTSD
796#define USTCNT_ODD_EVEN USTCNT_ODD
797#define USTCNT_PARITYEN USTCNT_PEN
798#define USTCNT_CLKMODE USTCNT_CLKM
799#define USTCNT_UARTEN USTCNT_UEN
800
801/*
802 * UART Baud Control Register
803 */
804#define UBAUD_ADDR 0xfffff902
805#define UBAUD WORD_REF(UBAUD_ADDR)
806
807#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
808#define UBAUD_PRESCALER_SHIFT 0
809#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
810#define UBAUD_DIVIDE_SHIFT 8
811#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
812#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
813
814/*
815 * UART Receiver Register
816 */
817#define URX_ADDR 0xfffff904
818#define URX WORD_REF(URX_ADDR)
819
820#define URX_RXDATA_ADDR 0xfffff905
821#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
822
823#define URX_RXDATA_MASK 0x00ff /* Received data */
824#define URX_RXDATA_SHIFT 0
825#define URX_PARITY_ERROR 0x0100 /* Parity Error */
826#define URX_BREAK 0x0200 /* Break Detected */
827#define URX_FRAME_ERROR 0x0400 /* Framing Error */
828#define URX_OVRUN 0x0800 /* Serial Overrun */
829#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
830#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
831#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
832#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
833
834/*
835 * UART Transmitter Register
836 */
837#define UTX_ADDR 0xfffff906
838#define UTX WORD_REF(UTX_ADDR)
839
840#define UTX_TXDATA_ADDR 0xfffff907
841#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
842
843#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
844#define UTX_TXDATA_SHIFT 0
845#define UTX_CTS_DELTA 0x0100 /* CTS changed */
846#define UTX_CTS_STAT 0x0200 /* CTS State */
847#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
848#define UTX_NOCTS 0x0800 /* Ignore CTS */
849#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
850#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
851#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
852#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
853
854/* '328-compatible definitions */
855#define UTX_CTS_STATUS UTX_CTS_STAT
856#define UTX_IGNORE_CTS UTX_NOCTS
857
858/*
859 * UART Miscellaneous Register
860 */
861#define UMISC_ADDR 0xfffff908
862#define UMISC WORD_REF(UMISC_ADDR)
863
864#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
865#define UMISC_RX_POL 0x0008 /* Receive Polarity */
866#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
867#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
868#define UMISC_RTS 0x0040 /* Set RTS status */
869#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
870#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
871#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
872#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
873#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
874#define UMISC_CLKSRC 0x4000 /* Clock Source */
875#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
876
877/*
878 * UART Non-integer Prescaler Register
879 */
880#define NIPR_ADDR 0xfffff90a
881#define NIPR WORD_REF(NIPR_ADDR)
882
883#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
884#define NIPR_STEP_VALUE_SHIFT 0
885#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
886#define NIPR_SELECT_SHIFT 8
887#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
888
889
890/* generalization of uart control registers to support multiple ports: */
891typedef struct {
892 volatile unsigned short int ustcnt;
893 volatile unsigned short int ubaud;
894 union {
895 volatile unsigned short int w;
896 struct {
897 volatile unsigned char status;
898 volatile unsigned char rxdata;
899 } b;
900 } urx;
901 union {
902 volatile unsigned short int w;
903 struct {
904 volatile unsigned char status;
905 volatile unsigned char txdata;
906 } b;
907 } utx;
908 volatile unsigned short int umisc;
909 volatile unsigned short int nipr;
910 volatile unsigned short int hmark;
911 volatile unsigned short int unused;
912} __attribute__((packed)) m68328_uart;
913
914
915
916
917/**********
918 *
919 * 0xFFFFFAxx -- LCD Controller
920 *
921 **********/
922
923/*
924 * LCD Screen Starting Address Register
925 */
926#define LSSA_ADDR 0xfffffa00
927#define LSSA LONG_REF(LSSA_ADDR)
928
929#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
930
931/*
932 * LCD Virtual Page Width Register
933 */
934#define LVPW_ADDR 0xfffffa05
935#define LVPW BYTE_REF(LVPW_ADDR)
936
937/*
938 * LCD Screen Width Register (not compatible with '328 !!!)
939 */
940#define LXMAX_ADDR 0xfffffa08
941#define LXMAX WORD_REF(LXMAX_ADDR)
942
943#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
944
945/*
946 * LCD Screen Height Register
947 */
948#define LYMAX_ADDR 0xfffffa0a
949#define LYMAX WORD_REF(LYMAX_ADDR)
950
951#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
952
953/*
954 * LCD Cursor X Position Register
955 */
956#define LCXP_ADDR 0xfffffa18
957#define LCXP WORD_REF(LCXP_ADDR)
958
959#define LCXP_CC_MASK 0xc000 /* Cursor Control */
960#define LCXP_CC_TRAMSPARENT 0x0000
961#define LCXP_CC_BLACK 0x4000
962#define LCXP_CC_REVERSED 0x8000
963#define LCXP_CC_WHITE 0xc000
964#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
965
966/*
967 * LCD Cursor Y Position Register
968 */
969#define LCYP_ADDR 0xfffffa1a
970#define LCYP WORD_REF(LCYP_ADDR)
971
972#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
973
974/*
975 * LCD Cursor Width and Heigth Register
976 */
977#define LCWCH_ADDR 0xfffffa1c
978#define LCWCH WORD_REF(LCWCH_ADDR)
979
980#define LCWCH_CH_MASK 0x001f /* Cursor Height */
981#define LCWCH_CH_SHIFT 0
982#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
983#define LCWCH_CW_SHIFT 8
984
985/*
986 * LCD Blink Control Register
987 */
988#define LBLKC_ADDR 0xfffffa1f
989#define LBLKC BYTE_REF(LBLKC_ADDR)
990
991#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
992#define LBLKC_BD_SHIFT 0
993#define LBLKC_BKEN 0x80 /* Blink Enabled */
994
995/*
996 * LCD Panel Interface Configuration Register
997 */
998#define LPICF_ADDR 0xfffffa20
999#define LPICF BYTE_REF(LPICF_ADDR)
1000
1001#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
1002#define LPICF_GS_BW 0x00
1003#define LPICF_GS_GRAY_4 0x01
1004#define LPICF_GS_GRAY_16 0x02
1005#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
1006#define LPICF_PBSIZ_1 0x00
1007#define LPICF_PBSIZ_2 0x04
1008#define LPICF_PBSIZ_4 0x08
1009
1010/*
1011 * LCD Polarity Configuration Register
1012 */
1013#define LPOLCF_ADDR 0xfffffa21
1014#define LPOLCF BYTE_REF(LPOLCF_ADDR)
1015
1016#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
1017#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
1018#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
1019#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
1020
1021/*
1022 * LACD (LCD Alternate Crystal Direction) Rate Control Register
1023 */
1024#define LACDRC_ADDR 0xfffffa23
1025#define LACDRC BYTE_REF(LACDRC_ADDR)
1026
1027#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
1028#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
1029#define LACDRC_ACD_SHIFT 0
1030
1031/*
1032 * LCD Pixel Clock Divider Register
1033 */
1034#define LPXCD_ADDR 0xfffffa25
1035#define LPXCD BYTE_REF(LPXCD_ADDR)
1036
1037#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1038#define LPXCD_PCD_SHIFT 0
1039
1040/*
1041 * LCD Clocking Control Register
1042 */
1043#define LCKCON_ADDR 0xfffffa27
1044#define LCKCON BYTE_REF(LCKCON_ADDR)
1045
1046#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
1047#define LCKCON_DWS_SHIFT 0
1048#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
1049#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
1050
1051/* '328-compatible definitions */
1052#define LCKCON_DW_MASK LCKCON_DWS_MASK
1053#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
1054
1055/*
1056 * LCD Refresh Rate Adjustment Register
1057 */
1058#define LRRA_ADDR 0xfffffa29
1059#define LRRA BYTE_REF(LRRA_ADDR)
1060
1061/*
1062 * LCD Panning Offset Register
1063 */
1064#define LPOSR_ADDR 0xfffffa2d
1065#define LPOSR BYTE_REF(LPOSR_ADDR)
1066
1067#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
1068#define LPOSR_POS_SHIFT 0
1069
1070/*
1071 * LCD Frame Rate Control Modulation Register
1072 */
1073#define LFRCM_ADDR 0xfffffa31
1074#define LFRCM BYTE_REF(LFRCM_ADDR)
1075
1076#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
1077#define LFRCM_YMOD_SHIFT 0
1078#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
1079#define LFRCM_XMOD_SHIFT 4
1080
1081/*
1082 * LCD Gray Palette Mapping Register
1083 */
1084#define LGPMR_ADDR 0xfffffa33
1085#define LGPMR BYTE_REF(LGPMR_ADDR)
1086
1087#define LGPMR_G1_MASK 0x0f
1088#define LGPMR_G1_SHIFT 0
1089#define LGPMR_G2_MASK 0xf0
1090#define LGPMR_G2_SHIFT 4
1091
1092/*
1093 * PWM Contrast Control Register
1094 */
1095#define PWMR_ADDR 0xfffffa36
1096#define PWMR WORD_REF(PWMR_ADDR)
1097
1098#define PWMR_PW_MASK 0x00ff /* Pulse Width */
1099#define PWMR_PW_SHIFT 0
1100#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
1101#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1102#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
1103#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1104#define PWMR_SRC_LCD 0x4000 /* LCD clock */
1105
1106/**********
1107 *
1108 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1109 *
1110 **********/
1111
1112/*
1113 * RTC Hours Minutes and Seconds Register
1114 */
1115#define RTCTIME_ADDR 0xfffffb00
1116#define RTCTIME LONG_REF(RTCTIME_ADDR)
1117
1118#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1119#define RTCTIME_SECONDS_SHIFT 0
1120#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1121#define RTCTIME_MINUTES_SHIFT 16
1122#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1123#define RTCTIME_HOURS_SHIFT 24
1124
1125/*
1126 * RTC Alarm Register
1127 */
1128#define RTCALRM_ADDR 0xfffffb04
1129#define RTCALRM LONG_REF(RTCALRM_ADDR)
1130
1131#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1132#define RTCALRM_SECONDS_SHIFT 0
1133#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1134#define RTCALRM_MINUTES_SHIFT 16
1135#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1136#define RTCALRM_HOURS_SHIFT 24
1137
1138/*
1139 * Watchdog Timer Register
1140 */
1141#define WATCHDOG_ADDR 0xfffffb0a
1142#define WATCHDOG WORD_REF(WATCHDOG_ADDR)
1143
1144#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
1145#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
1146#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */
1147#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
1148#define WATCHDOG_CNT_SHIFT 8
1149
1150/*
1151 * RTC Control Register
1152 */
1153#define RTCCTL_ADDR 0xfffffb0c
1154#define RTCCTL WORD_REF(RTCCTL_ADDR)
1155
1156#define RTCCTL_XTL 0x0020 /* Crystal Selection */
1157#define RTCCTL_EN 0x0080 /* RTC Enable */
1158
1159/* '328-compatible definitions */
1160#define RTCCTL_384 RTCCTL_XTL
1161#define RTCCTL_ENABLE RTCCTL_EN
1162
1163/*
1164 * RTC Interrupt Status Register
1165 */
1166#define RTCISR_ADDR 0xfffffb0e
1167#define RTCISR WORD_REF(RTCISR_ADDR)
1168
1169#define RTCISR_SW 0x0001 /* Stopwatch timed out */
1170#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1171#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1172#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1173#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1174#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1175#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
1176#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
1177#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
1178#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
1179#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
1180#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
1181#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
1182#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
1183
1184/*
1185 * RTC Interrupt Enable Register
1186 */
1187#define RTCIENR_ADDR 0xfffffb10
1188#define RTCIENR WORD_REF(RTCIENR_ADDR)
1189
1190#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1191#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1192#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1193#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1194#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1195#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1196#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
1197#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
1198#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
1199#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
1200#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
1201#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
1202#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
1203#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
1204
1205/*
1206 * Stopwatch Minutes Register
1207 */
1208#define STPWCH_ADDR 0xfffffb12
1209#define STPWCH WORD_REF(STPWCH_ADDR)
1210
1211#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
1212#define SPTWCH_CNT_SHIFT 0
1213
1214/*
1215 * RTC Day Count Register
1216 */
1217#define DAYR_ADDR 0xfffffb1a
1218#define DAYR WORD_REF(DAYR_ADDR)
1219
1220#define DAYR_DAYS_MASK 0x1ff /* Day Setting */
1221#define DAYR_DAYS_SHIFT 0
1222
1223/*
1224 * RTC Day Alarm Register
1225 */
1226#define DAYALARM_ADDR 0xfffffb1c
1227#define DAYALARM WORD_REF(DAYALARM_ADDR)
1228
1229#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
1230#define DAYALARM_DAYSAL_SHIFT 0
1231
1232/**********
1233 *
1234 * 0xFFFFFCxx -- DRAM Controller
1235 *
1236 **********/
1237
1238/*
1239 * DRAM Memory Configuration Register
1240 */
1241#define DRAMMC_ADDR 0xfffffc00
1242#define DRAMMC WORD_REF(DRAMMC_ADDR)
1243
1244#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
1245#define DRAMMC_ROW12_PA10 0x0000
1246#define DRAMMC_ROW12_PA21 0x4000
1247#define DRAMMC_ROW12_PA23 0x8000
1248#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
1249#define DRAMMC_ROW0_PA11 0x0000
1250#define DRAMMC_ROW0_PA22 0x1000
1251#define DRAMMC_ROW0_PA23 0x2000
1252#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
1253#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
1254#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
1255#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
1256#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
1257#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
1258#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
1259#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */
1260#define DRAMMC_REF_SHIFT 0
1261
1262/*
1263 * DRAM Control Register
1264 */
1265#define DRAMC_ADDR 0xfffffc02
1266#define DRAMC WORD_REF(DRAMC_ADDR)
1267
1268#define DRAMC_DWE 0x0001 /* DRAM Write Enable */
1269#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
1270#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1271#define DRAMC_SLW 0x0008 /* Slow RAM */
1272#define DRAMC_LSP 0x0010 /* Light Sleep */
1273#define DRAMC_MSW 0x0020 /* Slow Multiplexing */
1274#define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1275#define DRAMC_WS_SHIFT 6
1276#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
1277#define DRAMC_PGSZ_SHIFT 8
1278#define DRAMC_PGSZ_256K 0x0000
1279#define DRAMC_PGSZ_512K 0x0100
1280#define DRAMC_PGSZ_1024K 0x0200
1281#define DRAMC_PGSZ_2048K 0x0300
1282#define DRAMC_EDO 0x0400 /* EDO DRAM */
1283#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1284#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
1285#define DRAMC_BC_SHIFT 12
1286#define DRAMC_RM 0x4000 /* Refresh Mode */
1287#define DRAMC_EN 0x8000 /* DRAM Controller enable */
1288
1289
1290/**********
1291 *
1292 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1293 *
1294 **********/
1295
1296/*
1297 * ICE Module Address Compare Register
1298 */
1299#define ICEMACR_ADDR 0xfffffd00
1300#define ICEMACR LONG_REF(ICEMACR_ADDR)
1301
1302/*
1303 * ICE Module Address Mask Register
1304 */
1305#define ICEMAMR_ADDR 0xfffffd04
1306#define ICEMAMR LONG_REF(ICEMAMR_ADDR)
1307
1308/*
1309 * ICE Module Control Compare Register
1310 */
1311#define ICEMCCR_ADDR 0xfffffd08
1312#define ICEMCCR WORD_REF(ICEMCCR_ADDR)
1313
1314#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
1315#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
1316
1317/*
1318 * ICE Module Control Mask Register
1319 */
1320#define ICEMCMR_ADDR 0xfffffd0a
1321#define ICEMCMR WORD_REF(ICEMCMR_ADDR)
1322
1323#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
1324#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
1325
1326/*
1327 * ICE Module Control Register
1328 */
1329#define ICEMCR_ADDR 0xfffffd0c
1330#define ICEMCR WORD_REF(ICEMCR_ADDR)
1331
1332#define ICEMCR_CEN 0x0001 /* Compare Enable */
1333#define ICEMCR_PBEN 0x0002 /* Program Break Enable */
1334#define ICEMCR_SB 0x0004 /* Single Breakpoint */
1335#define ICEMCR_HMDIS 0x0008 /* HardMap disable */
1336#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
1337
1338/*
1339 * ICE Module Status Register
1340 */
1341#define ICEMSR_ADDR 0xfffffd0e
1342#define ICEMSR WORD_REF(ICEMSR_ADDR)
1343
1344#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
1345#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
1346#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
1347#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
1348
1349#endif /* _MC68VZ328_H_ */
diff --git a/arch/m68knommu/include/asm/a.out.h b/arch/m68knommu/include/asm/a.out.h
new file mode 100644
index 000000000000..ce18ef99de04
--- /dev/null
+++ b/arch/m68knommu/include/asm/a.out.h
@@ -0,0 +1 @@
#include <asm-m68k/a.out.h>
diff --git a/arch/m68knommu/include/asm/anchor.h b/arch/m68knommu/include/asm/anchor.h
new file mode 100644
index 000000000000..871c0d5cfc3d
--- /dev/null
+++ b/arch/m68knommu/include/asm/anchor.h
@@ -0,0 +1,112 @@
1/****************************************************************************/
2
3/*
4 * anchor.h -- Anchor CO-MEM Lite PCI host bridge part.
5 *
6 * (C) Copyright 2000, Moreton Bay (www.moreton.com.au)
7 */
8
9/****************************************************************************/
10#ifndef anchor_h
11#define anchor_h
12/****************************************************************************/
13
14/*
15 * Define basic addressing info.
16 */
17#if defined(CONFIG_M5407C3)
18#define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */
19#define COMEM_IRQ 25 /* IRQ of anchor part */
20#else
21#define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */
22#define COMEM_IRQ 25 /* IRQ of anchor part */
23#endif
24
25/****************************************************************************/
26
27/*
28 * 4-byte registers of CO-MEM, so adjust register addresses for
29 * easy access. Handy macro for word access too.
30 */
31#define LREG(a) ((a) >> 2)
32#define WREG(a) ((a) >> 1)
33
34
35/*
36 * Define base addresses within CO-MEM Lite register address space.
37 */
38#define COMEM_I2O 0x0000 /* I2O registers */
39#define COMEM_OPREGS 0x0400 /* Operation registers */
40#define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */
41#define COMEM_SHMEM 0x4000 /* Shared memory region */
42
43#define COMEM_SHMEMSIZE 0x4000 /* Size of shared memory */
44
45
46/*
47 * Define CO-MEM Registers.
48 */
49#define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */
50#define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */
51#define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */
52#define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */
53#define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */
54#define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */
55#define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */
56#define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */
57
58#define COMEM_DAHBASE 0x0460 /* Direct access base address */
59
60#define COMEM_NVCMD 0x04a0 /* I2C serial command */
61#define COMEM_NVREAD 0x04a4 /* I2C serial read */
62#define COMEM_NVSTAT 0x04a8 /* I2C status */
63
64#define COMEM_DMALBASE 0x04b0 /* DMA local base address */
65#define COMEM_DMAHBASE 0x04b4 /* DMA host base address */
66#define COMEM_DMASIZE 0x04b8 /* DMA size */
67#define COMEM_DMACTL 0x04bc /* DMA control */
68
69#define COMEM_HCTL 0x04e0 /* Host control */
70#define COMEM_HINT 0x04e4 /* Host interrupt control/status */
71#define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */
72#define COMEM_LINT 0x04f4 /* Local interrupt contole status */
73#define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */
74
75#define COMEM_LBUSCFG 0x04fc /* Local bus configuration */
76
77
78/*
79 * Commands and flags for use with Direct Access Register.
80 */
81#define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */
82#define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */
83#define COMEM_DA_MEMRD 0x00000004 /* Memory read cycle */
84#define COMEM_DA_MEMWR 0x00000004 /* Memory write cycle */
85#define COMEM_DA_IORD 0x00000002 /* I/O read cycle */
86#define COMEM_DA_IOWR 0x00000002 /* I/O write cycle */
87#define COMEM_DA_CFGRD 0x00000006 /* Configuration read cycle */
88#define COMEM_DA_CFGWR 0x00000006 /* Configuration write cycle */
89
90#define COMEM_DA_ADDR(a) ((a) & 0xffffe000)
91
92#define COMEM_DA_OFFSET(a) ((a) & 0x00001fff)
93
94
95/*
96 * The PCI bus will be limited in what slots will actually be used.
97 * Define valid device numbers for different boards.
98 */
99#if defined(CONFIG_M5407C3)
100#define COMEM_MINDEV 14 /* Minimum valid DEVICE */
101#define COMEM_MAXDEV 14 /* Maximum valid DEVICE */
102#define COMEM_BRIDGEDEV 15 /* Slot bridge is in */
103#else
104#define COMEM_MINDEV 0 /* Minimum valid DEVICE */
105#define COMEM_MAXDEV 3 /* Maximum valid DEVICE */
106#endif
107
108#define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */
109
110
111/****************************************************************************/
112#endif /* anchor_h */
diff --git a/arch/m68knommu/include/asm/atomic.h b/arch/m68knommu/include/asm/atomic.h
new file mode 100644
index 000000000000..d5632a305dae
--- /dev/null
+++ b/arch/m68knommu/include/asm/atomic.h
@@ -0,0 +1,155 @@
1#ifndef __ARCH_M68KNOMMU_ATOMIC__
2#define __ARCH_M68KNOMMU_ATOMIC__
3
4#include <asm/system.h>
5
6/*
7 * Atomic operations that C can't guarantee us. Useful for
8 * resource counting etc..
9 */
10
11/*
12 * We do not have SMP m68k systems, so we don't have to deal with that.
13 */
14
15typedef struct { int counter; } atomic_t;
16#define ATOMIC_INIT(i) { (i) }
17
18#define atomic_read(v) ((v)->counter)
19#define atomic_set(v, i) (((v)->counter) = i)
20
21static __inline__ void atomic_add(int i, atomic_t *v)
22{
23#ifdef CONFIG_COLDFIRE
24 __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "d" (i));
25#else
26 __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "di" (i));
27#endif
28}
29
30static __inline__ void atomic_sub(int i, atomic_t *v)
31{
32#ifdef CONFIG_COLDFIRE
33 __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "d" (i));
34#else
35 __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "di" (i));
36#endif
37}
38
39static __inline__ int atomic_sub_and_test(int i, atomic_t * v)
40{
41 char c;
42#ifdef CONFIG_COLDFIRE
43 __asm__ __volatile__("subl %2,%1; seq %0"
44 : "=d" (c), "+m" (*v)
45 : "d" (i));
46#else
47 __asm__ __volatile__("subl %2,%1; seq %0"
48 : "=d" (c), "+m" (*v)
49 : "di" (i));
50#endif
51 return c != 0;
52}
53
54static __inline__ void atomic_inc(volatile atomic_t *v)
55{
56 __asm__ __volatile__("addql #1,%0" : "+m" (*v));
57}
58
59/*
60 * atomic_inc_and_test - increment and test
61 * @v: pointer of type atomic_t
62 *
63 * Atomically increments @v by 1
64 * and returns true if the result is zero, or false for all
65 * other cases.
66 */
67
68static __inline__ int atomic_inc_and_test(volatile atomic_t *v)
69{
70 char c;
71 __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
72 return c != 0;
73}
74
75static __inline__ void atomic_dec(volatile atomic_t *v)
76{
77 __asm__ __volatile__("subql #1,%0" : "+m" (*v));
78}
79
80static __inline__ int atomic_dec_and_test(volatile atomic_t *v)
81{
82 char c;
83 __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
84 return c != 0;
85}
86
87static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v)
88{
89 __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask)));
90}
91
92static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v)
93{
94 __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
95}
96
97/* Atomic operations are already serializing */
98#define smp_mb__before_atomic_dec() barrier()
99#define smp_mb__after_atomic_dec() barrier()
100#define smp_mb__before_atomic_inc() barrier()
101#define smp_mb__after_atomic_inc() barrier()
102
103static inline int atomic_add_return(int i, atomic_t * v)
104{
105 unsigned long temp, flags;
106
107 local_irq_save(flags);
108 temp = *(long *)v;
109 temp += i;
110 *(long *)v = temp;
111 local_irq_restore(flags);
112
113 return temp;
114}
115
116#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
117
118static inline int atomic_sub_return(int i, atomic_t * v)
119{
120 unsigned long temp, flags;
121
122 local_irq_save(flags);
123 temp = *(long *)v;
124 temp -= i;
125 *(long *)v = temp;
126 local_irq_restore(flags);
127
128 return temp;
129}
130
131#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
132#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
133
134static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
135{
136 int c, old;
137 c = atomic_read(v);
138 for (;;) {
139 if (unlikely(c == (u)))
140 break;
141 old = atomic_cmpxchg((v), c, c + (a));
142 if (likely(old == c))
143 break;
144 c = old;
145 }
146 return c != (u);
147}
148
149#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
150
151#define atomic_dec_return(v) atomic_sub_return(1,(v))
152#define atomic_inc_return(v) atomic_add_return(1,(v))
153
154#include <asm-generic/atomic.h>
155#endif /* __ARCH_M68KNOMMU_ATOMIC __ */
diff --git a/arch/m68knommu/include/asm/auxvec.h b/arch/m68knommu/include/asm/auxvec.h
new file mode 100644
index 000000000000..844d6d52204b
--- /dev/null
+++ b/arch/m68knommu/include/asm/auxvec.h
@@ -0,0 +1,4 @@
1#ifndef __ASMm68k_AUXVEC_H
2#define __ASMm68k_AUXVEC_H
3
4#endif
diff --git a/arch/m68knommu/include/asm/bitops.h b/arch/m68knommu/include/asm/bitops.h
new file mode 100644
index 000000000000..6f3685eab44c
--- /dev/null
+++ b/arch/m68knommu/include/asm/bitops.h
@@ -0,0 +1,336 @@
1#ifndef _M68KNOMMU_BITOPS_H
2#define _M68KNOMMU_BITOPS_H
3
4/*
5 * Copyright 1992, Linus Torvalds.
6 */
7
8#include <linux/compiler.h>
9#include <asm/byteorder.h> /* swab32 */
10
11#ifdef __KERNEL__
12
13#ifndef _LINUX_BITOPS_H
14#error only <linux/bitops.h> can be included directly
15#endif
16
17#if defined (__mcfisaaplus__) || defined (__mcfisac__)
18static inline int ffs(unsigned int val)
19{
20 if (!val)
21 return 0;
22
23 asm volatile(
24 "bitrev %0\n\t"
25 "ff1 %0\n\t"
26 : "=d" (val)
27 : "0" (val)
28 );
29 val++;
30 return val;
31}
32
33static inline int __ffs(unsigned int val)
34{
35 asm volatile(
36 "bitrev %0\n\t"
37 "ff1 %0\n\t"
38 : "=d" (val)
39 : "0" (val)
40 );
41 return val;
42}
43
44#else
45#include <asm-generic/bitops/ffs.h>
46#include <asm-generic/bitops/__ffs.h>
47#endif
48
49#include <asm-generic/bitops/sched.h>
50#include <asm-generic/bitops/ffz.h>
51
52static __inline__ void set_bit(int nr, volatile unsigned long * addr)
53{
54#ifdef CONFIG_COLDFIRE
55 __asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)"
56 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
57 : "d" (nr)
58 : "%a0", "cc");
59#else
60 __asm__ __volatile__ ("bset %1,%0"
61 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
62 : "di" (nr)
63 : "cc");
64#endif
65}
66
67#define __set_bit(nr, addr) set_bit(nr, addr)
68
69/*
70 * clear_bit() doesn't provide any barrier for the compiler.
71 */
72#define smp_mb__before_clear_bit() barrier()
73#define smp_mb__after_clear_bit() barrier()
74
75static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
76{
77#ifdef CONFIG_COLDFIRE
78 __asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)"
79 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
80 : "d" (nr)
81 : "%a0", "cc");
82#else
83 __asm__ __volatile__ ("bclr %1,%0"
84 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
85 : "di" (nr)
86 : "cc");
87#endif
88}
89
90#define __clear_bit(nr, addr) clear_bit(nr, addr)
91
92static __inline__ void change_bit(int nr, volatile unsigned long * addr)
93{
94#ifdef CONFIG_COLDFIRE
95 __asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)"
96 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
97 : "d" (nr)
98 : "%a0", "cc");
99#else
100 __asm__ __volatile__ ("bchg %1,%0"
101 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
102 : "di" (nr)
103 : "cc");
104#endif
105}
106
107#define __change_bit(nr, addr) change_bit(nr, addr)
108
109static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
110{
111 char retval;
112
113#ifdef CONFIG_COLDFIRE
114 __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
115 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
116 : "d" (nr)
117 : "%a0");
118#else
119 __asm__ __volatile__ ("bset %2,%1; sne %0"
120 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
121 : "di" (nr)
122 /* No clobber */);
123#endif
124
125 return retval;
126}
127
128#define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
129
130static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
131{
132 char retval;
133
134#ifdef CONFIG_COLDFIRE
135 __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
136 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
137 : "d" (nr)
138 : "%a0");
139#else
140 __asm__ __volatile__ ("bclr %2,%1; sne %0"
141 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
142 : "di" (nr)
143 /* No clobber */);
144#endif
145
146 return retval;
147}
148
149#define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
150
151static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
152{
153 char retval;
154
155#ifdef CONFIG_COLDFIRE
156 __asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0"
157 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
158 : "d" (nr)
159 : "%a0");
160#else
161 __asm__ __volatile__ ("bchg %2,%1; sne %0"
162 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
163 : "di" (nr)
164 /* No clobber */);
165#endif
166
167 return retval;
168}
169
170#define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr)
171
172/*
173 * This routine doesn't need to be atomic.
174 */
175static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr)
176{
177 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
178}
179
180static __inline__ int __test_bit(int nr, const volatile unsigned long * addr)
181{
182 int * a = (int *) addr;
183 int mask;
184
185 a += nr >> 5;
186 mask = 1 << (nr & 0x1f);
187 return ((mask & *a) != 0);
188}
189
190#define test_bit(nr,addr) \
191(__builtin_constant_p(nr) ? \
192 __constant_test_bit((nr),(addr)) : \
193 __test_bit((nr),(addr)))
194
195#include <asm-generic/bitops/find.h>
196#include <asm-generic/bitops/hweight.h>
197#include <asm-generic/bitops/lock.h>
198
199static __inline__ int ext2_set_bit(int nr, volatile void * addr)
200{
201 char retval;
202
203#ifdef CONFIG_COLDFIRE
204 __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
205 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
206 : "d" (nr)
207 : "%a0");
208#else
209 __asm__ __volatile__ ("bset %2,%1; sne %0"
210 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
211 : "di" (nr)
212 /* No clobber */);
213#endif
214
215 return retval;
216}
217
218static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
219{
220 char retval;
221
222#ifdef CONFIG_COLDFIRE
223 __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
224 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
225 : "d" (nr)
226 : "%a0");
227#else
228 __asm__ __volatile__ ("bclr %2,%1; sne %0"
229 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
230 : "di" (nr)
231 /* No clobber */);
232#endif
233
234 return retval;
235}
236
237#define ext2_set_bit_atomic(lock, nr, addr) \
238 ({ \
239 int ret; \
240 spin_lock(lock); \
241 ret = ext2_set_bit((nr), (addr)); \
242 spin_unlock(lock); \
243 ret; \
244 })
245
246#define ext2_clear_bit_atomic(lock, nr, addr) \
247 ({ \
248 int ret; \
249 spin_lock(lock); \
250 ret = ext2_clear_bit((nr), (addr)); \
251 spin_unlock(lock); \
252 ret; \
253 })
254
255static __inline__ int ext2_test_bit(int nr, const volatile void * addr)
256{
257 char retval;
258
259#ifdef CONFIG_COLDFIRE
260 __asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0"
261 : "=d" (retval)
262 : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr)
263 : "%a0");
264#else
265 __asm__ __volatile__ ("btst %2,%1; sne %0"
266 : "=d" (retval)
267 : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr)
268 /* No clobber */);
269#endif
270
271 return retval;
272}
273
274#define ext2_find_first_zero_bit(addr, size) \
275 ext2_find_next_zero_bit((addr), (size), 0)
276
277static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
278{
279 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
280 unsigned long result = offset & ~31UL;
281 unsigned long tmp;
282
283 if (offset >= size)
284 return size;
285 size -= result;
286 offset &= 31UL;
287 if(offset) {
288 /* We hold the little endian value in tmp, but then the
289 * shift is illegal. So we could keep a big endian value
290 * in tmp, like this:
291 *
292 * tmp = __swab32(*(p++));
293 * tmp |= ~0UL >> (32-offset);
294 *
295 * but this would decrease performance, so we change the
296 * shift:
297 */
298 tmp = *(p++);
299 tmp |= __swab32(~0UL >> (32-offset));
300 if(size < 32)
301 goto found_first;
302 if(~tmp)
303 goto found_middle;
304 size -= 32;
305 result += 32;
306 }
307 while(size & ~31UL) {
308 if(~(tmp = *(p++)))
309 goto found_middle;
310 result += 32;
311 size -= 32;
312 }
313 if(!size)
314 return result;
315 tmp = *p;
316
317found_first:
318 /* tmp is little endian, so we would have to swab the shift,
319 * see above. But then we have to swab tmp below for ffz, so
320 * we might as well do this here.
321 */
322 return result + ffz(__swab32(tmp) | (~0UL << size));
323found_middle:
324 return result + ffz(__swab32(tmp));
325}
326
327#define ext2_find_next_bit(addr, size, off) \
328 generic_find_next_le_bit((unsigned long *)(addr), (size), (off))
329#include <asm-generic/bitops/minix.h>
330
331#endif /* __KERNEL__ */
332
333#include <asm-generic/bitops/fls.h>
334#include <asm-generic/bitops/fls64.h>
335
336#endif /* _M68KNOMMU_BITOPS_H */
diff --git a/arch/m68knommu/include/asm/bootinfo.h b/arch/m68knommu/include/asm/bootinfo.h
new file mode 100644
index 000000000000..c12e526f5189
--- /dev/null
+++ b/arch/m68knommu/include/asm/bootinfo.h
@@ -0,0 +1,2 @@
1
2/* Nothing for m68knommu */
diff --git a/arch/m68knommu/include/asm/bootstd.h b/arch/m68knommu/include/asm/bootstd.h
new file mode 100644
index 000000000000..bdc1a4ac4fe9
--- /dev/null
+++ b/arch/m68knommu/include/asm/bootstd.h
@@ -0,0 +1,132 @@
1/* bootstd.h: Bootloader system call interface
2 *
3 * (c) 1999, Rt-Control, Inc.
4 */
5
6#ifndef __BOOTSTD_H__
7#define __BOOTSTD_H__
8
9#define NR_BSC 21 /* last used bootloader system call */
10
11#define __BN_reset 0 /* reset and start the bootloader */
12#define __BN_test 1 /* tests the system call interface */
13#define __BN_exec 2 /* executes a bootloader image */
14#define __BN_exit 3 /* terminates a bootloader image */
15#define __BN_program 4 /* program FLASH from a chain */
16#define __BN_erase 5 /* erase sector(s) of FLASH */
17#define __BN_open 6
18#define __BN_write 7
19#define __BN_read 8
20#define __BN_close 9
21#define __BN_mmap 10 /* map a file descriptor into memory */
22#define __BN_munmap 11 /* remove a file to memory mapping */
23#define __BN_gethwaddr 12 /* get the hardware address of my interfaces */
24#define __BN_getserialnum 13 /* get the serial number of this board */
25#define __BN_getbenv 14 /* get a bootloader envvar */
26#define __BN_setbenv 15 /* get a bootloader envvar */
27#define __BN_setpmask 16 /* set the protection mask */
28#define __BN_readenv 17 /* read environment variables */
29#define __BN_flash_chattr_range 18
30#define __BN_flash_erase_range 19
31#define __BN_flash_write_range 20
32
33/* Calling conventions compatible to (uC)linux/68k
34 * We use simmilar macros to call into the bootloader as for uClinux
35 */
36
37#define __bsc_return(type, res) \
38do { \
39 if ((unsigned long)(res) >= (unsigned long)(-64)) { \
40 /* let errno be a function, preserve res in %d0 */ \
41 int __err = -(res); \
42 errno = __err; \
43 res = -1; \
44 } \
45 return (type)(res); \
46} while (0)
47
48#define _bsc0(type,name) \
49type name(void) \
50{ \
51 register long __res __asm__ ("%d0") = __BN_##name; \
52 __asm__ __volatile__ ("trap #2" \
53 : "=g" (__res) \
54 : "0" (__res) \
55 ); \
56 __bsc_return(type,__res); \
57}
58
59#define _bsc1(type,name,atype,a) \
60type name(atype a) \
61{ \
62 register long __res __asm__ ("%d0") = __BN_##name; \
63 register long __a __asm__ ("%d1") = (long)a; \
64 __asm__ __volatile__ ("trap #2" \
65 : "=g" (__res) \
66 : "0" (__res), "d" (__a) \
67 ); \
68 __bsc_return(type,__res); \
69}
70
71#define _bsc2(type,name,atype,a,btype,b) \
72type name(atype a, btype b) \
73{ \
74 register long __res __asm__ ("%d0") = __BN_##name; \
75 register long __a __asm__ ("%d1") = (long)a; \
76 register long __b __asm__ ("%d2") = (long)b; \
77 __asm__ __volatile__ ("trap #2" \
78 : "=g" (__res) \
79 : "0" (__res), "d" (__a), "d" (__b) \
80 ); \
81 __bsc_return(type,__res); \
82}
83
84#define _bsc3(type,name,atype,a,btype,b,ctype,c) \
85type name(atype a, btype b, ctype c) \
86{ \
87 register long __res __asm__ ("%d0") = __BN_##name; \
88 register long __a __asm__ ("%d1") = (long)a; \
89 register long __b __asm__ ("%d2") = (long)b; \
90 register long __c __asm__ ("%d3") = (long)c; \
91 __asm__ __volatile__ ("trap #2" \
92 : "=g" (__res) \
93 : "0" (__res), "d" (__a), "d" (__b), \
94 "d" (__c) \
95 ); \
96 __bsc_return(type,__res); \
97}
98
99#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
100type name(atype a, btype b, ctype c, dtype d) \
101{ \
102 register long __res __asm__ ("%d0") = __BN_##name; \
103 register long __a __asm__ ("%d1") = (long)a; \
104 register long __b __asm__ ("%d2") = (long)b; \
105 register long __c __asm__ ("%d3") = (long)c; \
106 register long __d __asm__ ("%d4") = (long)d; \
107 __asm__ __volatile__ ("trap #2" \
108 : "=g" (__res) \
109 : "0" (__res), "d" (__a), "d" (__b), \
110 "d" (__c), "d" (__d) \
111 ); \
112 __bsc_return(type,__res); \
113}
114
115#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
116type name(atype a, btype b, ctype c, dtype d, etype e) \
117{ \
118 register long __res __asm__ ("%d0") = __BN_##name; \
119 register long __a __asm__ ("%d1") = (long)a; \
120 register long __b __asm__ ("%d2") = (long)b; \
121 register long __c __asm__ ("%d3") = (long)c; \
122 register long __d __asm__ ("%d4") = (long)d; \
123 register long __e __asm__ ("%d5") = (long)e; \
124 __asm__ __volatile__ ("trap #2" \
125 : "=g" (__res) \
126 : "0" (__res), "d" (__a), "d" (__b), \
127 "d" (__c), "d" (__d), "d" (__e) \
128 ); \
129 __bsc_return(type,__res); \
130}
131
132#endif /* __BOOTSTD_H__ */
diff --git a/arch/m68knommu/include/asm/bug.h b/arch/m68knommu/include/asm/bug.h
new file mode 100644
index 000000000000..70e7dc0af21a
--- /dev/null
+++ b/arch/m68knommu/include/asm/bug.h
@@ -0,0 +1,4 @@
1#ifndef _M68KNOMMU_BUG_H
2#define _M68KNOMMU_BUG_H
3#include <asm-generic/bug.h>
4#endif
diff --git a/arch/m68knommu/include/asm/bugs.h b/arch/m68knommu/include/asm/bugs.h
new file mode 100644
index 000000000000..5f382dac3a60
--- /dev/null
+++ b/arch/m68knommu/include/asm/bugs.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-m68k/bugs.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7/*
8 * This is included by init/main.c to check for architecture-dependent bugs.
9 *
10 * Needs:
11 * void check_bugs(void);
12 */
13
14static void check_bugs(void)
15{
16}
diff --git a/arch/m68knommu/include/asm/byteorder.h b/arch/m68knommu/include/asm/byteorder.h
new file mode 100644
index 000000000000..20bb4426b610
--- /dev/null
+++ b/arch/m68knommu/include/asm/byteorder.h
@@ -0,0 +1,27 @@
1#ifndef _M68KNOMMU_BYTEORDER_H
2#define _M68KNOMMU_BYTEORDER_H
3
4#include <linux/types.h>
5
6#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
7# define __BYTEORDER_HAS_U64__
8# define __SWAB_64_THRU_32__
9#endif
10
11#if defined (__mcfisaaplus__) || defined (__mcfisac__)
12static inline __attribute_const__ __u32 ___arch__swab32(__u32 val)
13{
14 asm(
15 "byterev %0"
16 : "=d" (val)
17 : "0" (val)
18 );
19 return val;
20}
21
22#define __arch__swab32(x) ___arch__swab32(x)
23#endif
24
25#include <linux/byteorder/big_endian.h>
26
27#endif /* _M68KNOMMU_BYTEORDER_H */
diff --git a/arch/m68knommu/include/asm/cache.h b/arch/m68knommu/include/asm/cache.h
new file mode 100644
index 000000000000..24e9eace5f8c
--- /dev/null
+++ b/arch/m68knommu/include/asm/cache.h
@@ -0,0 +1,12 @@
1#ifndef __ARCH_M68KNOMMU_CACHE_H
2#define __ARCH_M68KNOMMU_CACHE_H
3
4/* bytes per L1 cache line */
5#define L1_CACHE_BYTES 16 /* this need to be at least 1 */
6
7/* m68k-elf-gcc 2.95.2 doesn't like these */
8
9#define __cacheline_aligned
10#define ____cacheline_aligned
11
12#endif
diff --git a/arch/m68knommu/include/asm/cachectl.h b/arch/m68knommu/include/asm/cachectl.h
new file mode 100644
index 000000000000..bcf5a6a9dd52
--- /dev/null
+++ b/arch/m68knommu/include/asm/cachectl.h
@@ -0,0 +1 @@
#include <asm-m68k/cachectl.h>
diff --git a/arch/m68knommu/include/asm/cacheflush.h b/arch/m68knommu/include/asm/cacheflush.h
new file mode 100644
index 000000000000..87e5dc0413b4
--- /dev/null
+++ b/arch/m68knommu/include/asm/cacheflush.h
@@ -0,0 +1,84 @@
1#ifndef _M68KNOMMU_CACHEFLUSH_H
2#define _M68KNOMMU_CACHEFLUSH_H
3
4/*
5 * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
6 */
7#include <linux/mm.h>
8
9#define flush_cache_all() __flush_cache_all()
10#define flush_cache_mm(mm) do { } while (0)
11#define flush_cache_dup_mm(mm) do { } while (0)
12#define flush_cache_range(vma, start, end) __flush_cache_all()
13#define flush_cache_page(vma, vmaddr) do { } while (0)
14#define flush_dcache_range(start,len) __flush_cache_all()
15#define flush_dcache_page(page) do { } while (0)
16#define flush_dcache_mmap_lock(mapping) do { } while (0)
17#define flush_dcache_mmap_unlock(mapping) do { } while (0)
18#define flush_icache_range(start,len) __flush_cache_all()
19#define flush_icache_page(vma,pg) do { } while (0)
20#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
21#define flush_cache_vmap(start, end) do { } while (0)
22#define flush_cache_vunmap(start, end) do { } while (0)
23
24#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
25 memcpy(dst, src, len)
26#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
27 memcpy(dst, src, len)
28
29static inline void __flush_cache_all(void)
30{
31#ifdef CONFIG_M5407
32 /*
33 * Use cpushl to push and invalidate all cache lines.
34 * Gas doesn't seem to know how to generate the ColdFire
35 * cpushl instruction... Oh well, bit stuff it for now.
36 */
37 __asm__ __volatile__ (
38 "nop\n\t"
39 "clrl %%d0\n\t"
40 "1:\n\t"
41 "movel %%d0,%%a0\n\t"
42 "2:\n\t"
43 ".word 0xf468\n\t"
44 "addl #0x10,%%a0\n\t"
45 "cmpl #0x00000800,%%a0\n\t"
46 "blt 2b\n\t"
47 "addql #1,%%d0\n\t"
48 "cmpil #4,%%d0\n\t"
49 "bne 1b\n\t"
50 "movel #0xb6088500,%%d0\n\t"
51 "movec %%d0,%%CACR\n\t"
52 : : : "d0", "a0" );
53#endif /* CONFIG_M5407 */
54#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
55 __asm__ __volatile__ (
56 "movel #0x81000200, %%d0\n\t"
57 "movec %%d0, %%CACR\n\t"
58 "nop\n\t"
59 : : : "d0" );
60#endif /* CONFIG_M527x || CONFIG_M528x */
61#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
62 __asm__ __volatile__ (
63 "movel #0x81000100, %%d0\n\t"
64 "movec %%d0, %%CACR\n\t"
65 "nop\n\t"
66 : : : "d0" );
67#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
68#ifdef CONFIG_M5249
69 __asm__ __volatile__ (
70 "movel #0xa1000200, %%d0\n\t"
71 "movec %%d0, %%CACR\n\t"
72 "nop\n\t"
73 : : : "d0" );
74#endif /* CONFIG_M5249 */
75#ifdef CONFIG_M532x
76 __asm__ __volatile__ (
77 "movel #0x81000200, %%d0\n\t"
78 "movec %%d0, %%CACR\n\t"
79 "nop\n\t"
80 : : : "d0" );
81#endif /* CONFIG_M532x */
82}
83
84#endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68knommu/include/asm/checksum.h b/arch/m68knommu/include/asm/checksum.h
new file mode 100644
index 000000000000..81883482ffb1
--- /dev/null
+++ b/arch/m68knommu/include/asm/checksum.h
@@ -0,0 +1,132 @@
1#ifndef _M68K_CHECKSUM_H
2#define _M68K_CHECKSUM_H
3
4#include <linux/in6.h>
5
6/*
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18__wsum csum_partial(const void *buff, int len, __wsum sum);
19
20/*
21 * the same as csum_partial, but copies from src while it
22 * checksums
23 *
24 * here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
26 */
27
28__wsum csum_partial_copy_nocheck(const void *src, void *dst,
29 int len, __wsum sum);
30
31
32/*
33 * the same as csum_partial_copy, but copies from user space.
34 *
35 * here even more important to align src and dst on a 32-bit (or even
36 * better 64-bit) boundary
37 */
38
39extern __wsum csum_partial_copy_from_user(const void __user *src,
40 void *dst, int len, __wsum sum, int *csum_err);
41
42__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
43
44/*
45 * Fold a partial checksum
46 */
47
48static inline __sum16 csum_fold(__wsum sum)
49{
50 unsigned int tmp = (__force u32)sum;
51#ifdef CONFIG_COLDFIRE
52 tmp = (tmp & 0xffff) + (tmp >> 16);
53 tmp = (tmp & 0xffff) + (tmp >> 16);
54 return (__force __sum16)~tmp;
55#else
56 __asm__("swap %1\n\t"
57 "addw %1, %0\n\t"
58 "clrw %1\n\t"
59 "addxw %1, %0"
60 : "=&d" (sum), "=&d" (tmp)
61 : "0" (sum), "1" (sum));
62 return (__force __sum16)~sum;
63#endif
64}
65
66
67/*
68 * computes the checksum of the TCP/UDP pseudo-header
69 * returns a 16-bit checksum, already complemented
70 */
71
72static inline __wsum
73csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
74 unsigned short proto, __wsum sum)
75{
76 __asm__ ("addl %1,%0\n\t"
77 "addxl %4,%0\n\t"
78 "addxl %5,%0\n\t"
79 "clrl %1\n\t"
80 "addxl %1,%0"
81 : "=&d" (sum), "=&d" (saddr)
82 : "0" (daddr), "1" (saddr), "d" (len + proto),
83 "d"(sum));
84 return sum;
85}
86
87static inline __sum16
88csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
89 unsigned short proto, __wsum sum)
90{
91 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
92}
93
94/*
95 * this routine is used for miscellaneous IP-like checksums, mainly
96 * in icmp.c
97 */
98
99extern __sum16 ip_compute_csum(const void *buff, int len);
100
101#define _HAVE_ARCH_IPV6_CSUM
102static __inline__ __sum16
103csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
104 __u32 len, unsigned short proto, __wsum sum)
105{
106 register unsigned long tmp;
107 __asm__("addl %2@,%0\n\t"
108 "movel %2@(4),%1\n\t"
109 "addxl %1,%0\n\t"
110 "movel %2@(8),%1\n\t"
111 "addxl %1,%0\n\t"
112 "movel %2@(12),%1\n\t"
113 "addxl %1,%0\n\t"
114 "movel %3@,%1\n\t"
115 "addxl %1,%0\n\t"
116 "movel %3@(4),%1\n\t"
117 "addxl %1,%0\n\t"
118 "movel %3@(8),%1\n\t"
119 "addxl %1,%0\n\t"
120 "movel %3@(12),%1\n\t"
121 "addxl %1,%0\n\t"
122 "addxl %4,%0\n\t"
123 "clrl %1\n\t"
124 "addxl %1,%0"
125 : "=&d" (sum), "=&d" (tmp)
126 : "a" (saddr), "a" (daddr), "d" (len + proto),
127 "0" (sum));
128
129 return csum_fold(sum);
130}
131
132#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68knommu/include/asm/coldfire.h b/arch/m68knommu/include/asm/coldfire.h
new file mode 100644
index 000000000000..83a9fa4e618a
--- /dev/null
+++ b/arch/m68knommu/include/asm/coldfire.h
@@ -0,0 +1,51 @@
1/****************************************************************************/
2
3/*
4 * coldfire.h -- Motorola ColdFire CPU sepecific defines
5 *
6 * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef coldfire_h
12#define coldfire_h
13/****************************************************************************/
14
15
16/*
17 * Define master clock frequency. This is essentially done at config
18 * time now. No point enumerating dozens of possible clock options
19 * here. Also the peripheral clock (bus clock) divide ratio is set
20 * at config time too.
21 */
22#ifdef CONFIG_CLOCK_SET
23#define MCF_CLK CONFIG_CLOCK_FREQ
24#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
25#else
26#error "Don't know what your ColdFire CPU clock frequency is??"
27#endif
28
29/*
30 * Define the processor support peripherals base address.
31 * This is generally setup by the boards start up code.
32 */
33#define MCF_MBAR 0x10000000
34#define MCF_MBAR2 0x80000000
35#if defined(CONFIG_M520x)
36#define MCF_IPSBAR 0xFC000000
37#else
38#define MCF_IPSBAR 0x40000000
39#endif
40
41#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
42 defined(CONFIG_M520x)
43#undef MCF_MBAR
44#define MCF_MBAR MCF_IPSBAR
45#elif defined(CONFIG_M532x)
46#undef MCF_MBAR
47#define MCF_MBAR 0x00000000
48#endif
49
50/****************************************************************************/
51#endif /* coldfire_h */
diff --git a/arch/m68knommu/include/asm/commproc.h b/arch/m68knommu/include/asm/commproc.h
new file mode 100644
index 000000000000..edf5eb6c08d2
--- /dev/null
+++ b/arch/m68knommu/include/asm/commproc.h
@@ -0,0 +1,703 @@
1
2/*
3 * 68360 Communication Processor Module.
4 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
5 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
6 *
7 * This file contains structures and information for the communication
8 * processor channels. Some CPM control and status is available
9 * through the 68360 internal memory map. See include/asm/360_immap.h for details.
10 * This file is not a complete map of all of the 360 QUICC's capabilities
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM_360__
18#define __CPM_360__
19
20
21/* CPM Command register masks: */
22#define CPM_CR_RST ((ushort)0x8000)
23#define CPM_CR_OPCODE ((ushort)0x0f00)
24#define CPM_CR_CHAN ((ushort)0x00f0)
25#define CPM_CR_FLG ((ushort)0x0001)
26
27/* CPM Command set (opcodes): */
28#define CPM_CR_INIT_TRX ((ushort)0x0000)
29#define CPM_CR_INIT_RX ((ushort)0x0001)
30#define CPM_CR_INIT_TX ((ushort)0x0002)
31#define CPM_CR_HUNT_MODE ((ushort)0x0003)
32#define CPM_CR_STOP_TX ((ushort)0x0004)
33#define CPM_CR_GRSTOP_TX ((ushort)0x0005)
34#define CPM_CR_RESTART_TX ((ushort)0x0006)
35#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
36#define CPM_CR_SET_GADDR ((ushort)0x0008)
37#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
38#define CPM_CR_GCI_ABORT ((ushort)0x000a)
39#define CPM_CR_RESET_BCS ((ushort)0x000a)
40
41/* CPM Channel numbers. */
42#define CPM_CR_CH_SCC1 ((ushort)0x0000)
43#define CPM_CR_CH_SCC2 ((ushort)0x0004)
44#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
45#define CPM_CR_CH_TMR ((ushort)0x0005)
46#define CPM_CR_CH_SCC3 ((ushort)0x0008)
47#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
48#define CPM_CR_CH_IDMA1 ((ushort)0x0009)
49#define CPM_CR_CH_SCC4 ((ushort)0x000c)
50#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
51#define CPM_CR_CH_IDMA2 ((ushort)0x000d)
52
53
54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
55
56#if 1 /* mleslie: I dinna think we have any such restrictions on
57 * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
58
59/* The dual ported RAM is multi-functional. Some areas can be (and are
60 * being) used for microcode. There is an area that can only be used
61 * as data ram for buffer descriptors, which is all we use right now.
62 * Currently the first 512 and last 256 bytes are used for microcode.
63 */
64/* mleslie: The uCquicc board is using no extra microcode in DPRAM */
65#define CPM_DATAONLY_BASE ((uint)0x0000)
66#define CPM_DATAONLY_SIZE ((uint)0x0800)
67#define CPM_DP_NOSPACE ((uint)0x7fffffff)
68
69#endif
70
71
72/* Export the base address of the communication processor registers
73 * and dual port ram. */
74/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */
75extern QUICC *pquicc;
76uint m360_cpm_dpalloc(uint size);
77/* void *m360_cpm_hostalloc(uint size); */
78void m360_cpm_setbrg(uint brg, uint rate);
79
80#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */
81/* Buffer descriptors used by many of the CPM protocols. */
82typedef struct cpm_buf_desc {
83 ushort cbd_sc; /* Status and Control */
84 ushort cbd_datlen; /* Data length in buffer */
85 uint cbd_bufaddr; /* Buffer address in host memory */
86} cbd_t;
87#endif
88
89
90/* rx bd status/control bits */
91#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
95
96#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
97#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
98
99#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
100#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
101
102#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
103#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
104
105#define BD_SC_BR ((ushort)0x0020) /* Break received */
106#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
107
108#define BD_SC_FR ((ushort)0x0010) /* Framing error */
109#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
110
111#define BD_SC_PR ((ushort)0x0008) /* Parity error */
112#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
113
114#define BD_SC_OV ((ushort)0x0002) /* Overrun */
115#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
116
117/* tx bd status/control bits (as differ from rx bd) */
118#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
119#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
120#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
121#define BD_SC_UN ((ushort)0x0002) /* Underrun */
122
123
124
125
126/* Parameter RAM offsets. */
127
128
129
130/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
131 * In 2.0, we use a more structured C struct map of DPRAM, and so
132 * instead, we need only a parameter ram `slot' */
133
134#define PRSLOT_SCC1 0
135#define PRSLOT_SCC2 1
136#define PRSLOT_SCC3 2
137#define PRSLOT_SMC1 2
138#define PRSLOT_SCC4 3
139#define PRSLOT_SMC2 3
140
141
142/* #define PROFF_SCC1 ((uint)0x0000) */
143/* #define PROFF_SCC2 ((uint)0x0100) */
144/* #define PROFF_SCC3 ((uint)0x0200) */
145/* #define PROFF_SMC1 ((uint)0x0280) */
146/* #define PROFF_SCC4 ((uint)0x0300) */
147/* #define PROFF_SMC2 ((uint)0x0380) */
148
149
150/* Define enough so I can at least use the serial port as a UART.
151 * The MBX uses SMC1 as the host serial port.
152 */
153typedef struct smc_uart {
154 ushort smc_rbase; /* Rx Buffer descriptor base address */
155 ushort smc_tbase; /* Tx Buffer descriptor base address */
156 u_char smc_rfcr; /* Rx function code */
157 u_char smc_tfcr; /* Tx function code */
158 ushort smc_mrblr; /* Max receive buffer length */
159 uint smc_rstate; /* Internal */
160 uint smc_idp; /* Internal */
161 ushort smc_rbptr; /* Internal */
162 ushort smc_ibc; /* Internal */
163 uint smc_rxtmp; /* Internal */
164 uint smc_tstate; /* Internal */
165 uint smc_tdp; /* Internal */
166 ushort smc_tbptr; /* Internal */
167 ushort smc_tbc; /* Internal */
168 uint smc_txtmp; /* Internal */
169 ushort smc_maxidl; /* Maximum idle characters */
170 ushort smc_tmpidl; /* Temporary idle counter */
171 ushort smc_brklen; /* Last received break length */
172 ushort smc_brkec; /* rcv'd break condition counter */
173 ushort smc_brkcr; /* xmt break count register */
174 ushort smc_rmask; /* Temporary bit mask */
175} smc_uart_t;
176
177/* Function code bits.
178*/
179#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
180
181/* SMC uart mode register.
182*/
183#define SMCMR_REN ((ushort)0x0001)
184#define SMCMR_TEN ((ushort)0x0002)
185#define SMCMR_DM ((ushort)0x000c)
186#define SMCMR_SM_GCI ((ushort)0x0000)
187#define SMCMR_SM_UART ((ushort)0x0020)
188#define SMCMR_SM_TRANS ((ushort)0x0030)
189#define SMCMR_SM_MASK ((ushort)0x0030)
190#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
191#define SMCMR_REVD SMCMR_PM_EVEN
192#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
193#define SMCMR_BS SMCMR_PEN
194#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
195#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
196#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
197
198/* SMC2 as Centronics parallel printer. It is half duplex, in that
199 * it can only receive or transmit. The parameter ram values for
200 * each direction are either unique or properly overlap, so we can
201 * include them in one structure.
202 */
203typedef struct smc_centronics {
204 ushort scent_rbase;
205 ushort scent_tbase;
206 u_char scent_cfcr;
207 u_char scent_smask;
208 ushort scent_mrblr;
209 uint scent_rstate;
210 uint scent_r_ptr;
211 ushort scent_rbptr;
212 ushort scent_r_cnt;
213 uint scent_rtemp;
214 uint scent_tstate;
215 uint scent_t_ptr;
216 ushort scent_tbptr;
217 ushort scent_t_cnt;
218 uint scent_ttemp;
219 ushort scent_max_sl;
220 ushort scent_sl_cnt;
221 ushort scent_character1;
222 ushort scent_character2;
223 ushort scent_character3;
224 ushort scent_character4;
225 ushort scent_character5;
226 ushort scent_character6;
227 ushort scent_character7;
228 ushort scent_character8;
229 ushort scent_rccm;
230 ushort scent_rccr;
231} smc_cent_t;
232
233/* Centronics Status Mask Register.
234*/
235#define SMC_CENT_F ((u_char)0x08)
236#define SMC_CENT_PE ((u_char)0x04)
237#define SMC_CENT_S ((u_char)0x02)
238
239/* SMC Event and Mask register.
240*/
241#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
242#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
243#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
244#define SMCM_BSY ((unsigned char)0x04)
245#define SMCM_TX ((unsigned char)0x02)
246#define SMCM_RX ((unsigned char)0x01)
247
248/* Baud rate generators.
249*/
250#define CPM_BRG_RST ((uint)0x00020000)
251#define CPM_BRG_EN ((uint)0x00010000)
252#define CPM_BRG_EXTC_INT ((uint)0x00000000)
253#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
254#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
255#define CPM_BRG_ATB ((uint)0x00002000)
256#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
257#define CPM_BRG_DIV16 ((uint)0x00000001)
258
259/* SCCs.
260*/
261#define SCC_GSMRH_IRP ((uint)0x00040000)
262#define SCC_GSMRH_GDE ((uint)0x00010000)
263#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
264#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
265#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
266#define SCC_GSMRH_REVD ((uint)0x00002000)
267#define SCC_GSMRH_TRX ((uint)0x00001000)
268#define SCC_GSMRH_TTX ((uint)0x00000800)
269#define SCC_GSMRH_CDP ((uint)0x00000400)
270#define SCC_GSMRH_CTSP ((uint)0x00000200)
271#define SCC_GSMRH_CDS ((uint)0x00000100)
272#define SCC_GSMRH_CTSS ((uint)0x00000080)
273#define SCC_GSMRH_TFL ((uint)0x00000040)
274#define SCC_GSMRH_RFW ((uint)0x00000020)
275#define SCC_GSMRH_TXSY ((uint)0x00000010)
276#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
277#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
278#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
279#define SCC_GSMRH_RTSM ((uint)0x00000002)
280#define SCC_GSMRH_RSYN ((uint)0x00000001)
281
282#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
283#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
284#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
285#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
286#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
287#define SCC_GSMRL_TCI ((uint)0x10000000)
288#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
289#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
290#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
291#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
292#define SCC_GSMRL_RINV ((uint)0x02000000)
293#define SCC_GSMRL_TINV ((uint)0x01000000)
294#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
295#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
296#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
297#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
298#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
299#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
300#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
301#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
302#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
303#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
304#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
305#define SCC_GSMRL_TEND ((uint)0x00040000)
306#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
307#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
308#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
309#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
310#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
311#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
312#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
313#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
314#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
315#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
316#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
317#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
318#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
319#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
320#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
321#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
322#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
323#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
324#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
325#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
326#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
327#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
328#define SCC_GSMRL_ENR ((uint)0x00000020)
329#define SCC_GSMRL_ENT ((uint)0x00000010)
330#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
331#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
332#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
333#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
334#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
335#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
336#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
337#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
338#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
339#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
340
341#define SCC_TODR_TOD ((ushort)0x8000)
342
343/* SCC Event and Mask register.
344*/
345#define SCCM_TXE ((unsigned char)0x10)
346#define SCCM_BSY ((unsigned char)0x04)
347#define SCCM_TX ((unsigned char)0x02)
348#define SCCM_RX ((unsigned char)0x01)
349
350typedef struct scc_param {
351 ushort scc_rbase; /* Rx Buffer descriptor base address */
352 ushort scc_tbase; /* Tx Buffer descriptor base address */
353 u_char scc_rfcr; /* Rx function code */
354 u_char scc_tfcr; /* Tx function code */
355 ushort scc_mrblr; /* Max receive buffer length */
356 uint scc_rstate; /* Internal */
357 uint scc_idp; /* Internal */
358 ushort scc_rbptr; /* Internal */
359 ushort scc_ibc; /* Internal */
360 uint scc_rxtmp; /* Internal */
361 uint scc_tstate; /* Internal */
362 uint scc_tdp; /* Internal */
363 ushort scc_tbptr; /* Internal */
364 ushort scc_tbc; /* Internal */
365 uint scc_txtmp; /* Internal */
366 uint scc_rcrc; /* Internal */
367 uint scc_tcrc; /* Internal */
368} sccp_t;
369
370
371/* Function code bits.
372 */
373#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
374#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
375
376/* CPM Ethernet through SCC1.
377 */
378typedef struct scc_enet {
379 sccp_t sen_genscc;
380 uint sen_cpres; /* Preset CRC */
381 uint sen_cmask; /* Constant mask for CRC */
382 uint sen_crcec; /* CRC Error counter */
383 uint sen_alec; /* alignment error counter */
384 uint sen_disfc; /* discard frame counter */
385 ushort sen_pads; /* Tx short frame pad character */
386 ushort sen_retlim; /* Retry limit threshold */
387 ushort sen_retcnt; /* Retry limit counter */
388 ushort sen_maxflr; /* maximum frame length register */
389 ushort sen_minflr; /* minimum frame length register */
390 ushort sen_maxd1; /* maximum DMA1 length */
391 ushort sen_maxd2; /* maximum DMA2 length */
392 ushort sen_maxd; /* Rx max DMA */
393 ushort sen_dmacnt; /* Rx DMA counter */
394 ushort sen_maxb; /* Max BD byte count */
395 ushort sen_gaddr1; /* Group address filter */
396 ushort sen_gaddr2;
397 ushort sen_gaddr3;
398 ushort sen_gaddr4;
399 uint sen_tbuf0data0; /* Save area 0 - current frame */
400 uint sen_tbuf0data1; /* Save area 1 - current frame */
401 uint sen_tbuf0rba; /* Internal */
402 uint sen_tbuf0crc; /* Internal */
403 ushort sen_tbuf0bcnt; /* Internal */
404 ushort sen_paddrh; /* physical address (MSB) */
405 ushort sen_paddrm;
406 ushort sen_paddrl; /* physical address (LSB) */
407 ushort sen_pper; /* persistence */
408 ushort sen_rfbdptr; /* Rx first BD pointer */
409 ushort sen_tfbdptr; /* Tx first BD pointer */
410 ushort sen_tlbdptr; /* Tx last BD pointer */
411 uint sen_tbuf1data0; /* Save area 0 - current frame */
412 uint sen_tbuf1data1; /* Save area 1 - current frame */
413 uint sen_tbuf1rba; /* Internal */
414 uint sen_tbuf1crc; /* Internal */
415 ushort sen_tbuf1bcnt; /* Internal */
416 ushort sen_txlen; /* Tx Frame length counter */
417 ushort sen_iaddr1; /* Individual address filter */
418 ushort sen_iaddr2;
419 ushort sen_iaddr3;
420 ushort sen_iaddr4;
421 ushort sen_boffcnt; /* Backoff counter */
422
423 /* NOTE: Some versions of the manual have the following items
424 * incorrectly documented. Below is the proper order.
425 */
426 ushort sen_taddrh; /* temp address (MSB) */
427 ushort sen_taddrm;
428 ushort sen_taddrl; /* temp address (LSB) */
429} scc_enet_t;
430
431
432
433#if defined (CONFIG_UCQUICC)
434/* uCquicc has the following signals connected to Ethernet:
435 * 68360 - lxt905
436 * PA0/RXD1 - rxd
437 * PA1/TXD1 - txd
438 * PA8/CLK1 - tclk
439 * PA9/CLK2 - rclk
440 * PC0/!RTS1 - t_en
441 * PC1/!CTS1 - col
442 * PC5/!CD1 - cd
443 */
444#define PA_ENET_RXD PA_RXD1
445#define PA_ENET_TXD PA_TXD1
446#define PA_ENET_TCLK PA_CLK1
447#define PA_ENET_RCLK PA_CLK2
448#define PC_ENET_TENA PC_RTS1
449#define PC_ENET_CLSN PC_CTS1
450#define PC_ENET_RENA PC_CD1
451
452/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
453 * SCC1.
454 */
455#define SICR_ENET_MASK ((uint)0x000000ff)
456#define SICR_ENET_CLKRT ((uint)0x0000002c)
457
458#endif /* config_ucquicc */
459
460
461#ifdef MBX
462/* Bits in parallel I/O port registers that have to be set/cleared
463 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
464 * to the MBX860 board. Any two of the four available clocks could be
465 * used, and the MPC860 cookbook manual has an example using different
466 * clock pins.
467 */
468#define PA_ENET_RXD ((ushort)0x0001)
469#define PA_ENET_TXD ((ushort)0x0002)
470#define PA_ENET_TCLK ((ushort)0x0200)
471#define PA_ENET_RCLK ((ushort)0x0800)
472#define PC_ENET_TENA ((ushort)0x0001)
473#define PC_ENET_CLSN ((ushort)0x0010)
474#define PC_ENET_RENA ((ushort)0x0020)
475
476/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
477 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
478 */
479#define SICR_ENET_MASK ((uint)0x000000ff)
480#define SICR_ENET_CLKRT ((uint)0x0000003d)
481#endif
482
483#ifdef CONFIG_RPXLITE
484/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
485 * this may be unique to the RPX-Lite configuration.
486 * Note TENA is on Port B.
487 */
488#define PA_ENET_RXD ((ushort)0x0004)
489#define PA_ENET_TXD ((ushort)0x0008)
490#define PA_ENET_TCLK ((ushort)0x0200)
491#define PA_ENET_RCLK ((ushort)0x0800)
492#define PB_ENET_TENA ((uint)0x00002000)
493#define PC_ENET_CLSN ((ushort)0x0040)
494#define PC_ENET_RENA ((ushort)0x0080)
495
496#define SICR_ENET_MASK ((uint)0x0000ff00)
497#define SICR_ENET_CLKRT ((uint)0x00003d00)
498#endif
499
500#ifdef CONFIG_BSEIP
501/* This ENET stuff is for the MPC823 with ethernet on SCC2.
502 * This is unique to the BSE ip-Engine board.
503 */
504#define PA_ENET_RXD ((ushort)0x0004)
505#define PA_ENET_TXD ((ushort)0x0008)
506#define PA_ENET_TCLK ((ushort)0x0100)
507#define PA_ENET_RCLK ((ushort)0x0200)
508#define PB_ENET_TENA ((uint)0x00002000)
509#define PC_ENET_CLSN ((ushort)0x0040)
510#define PC_ENET_RENA ((ushort)0x0080)
511
512/* BSE uses port B and C bits for PHY control also.
513*/
514#define PB_BSE_POWERUP ((uint)0x00000004)
515#define PB_BSE_FDXDIS ((uint)0x00008000)
516#define PC_BSE_LOOPBACK ((ushort)0x0800)
517
518#define SICR_ENET_MASK ((uint)0x0000ff00)
519#define SICR_ENET_CLKRT ((uint)0x00002c00)
520#endif
521
522/* SCC Event register as used by Ethernet.
523*/
524#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
525#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
526#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
527#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
528#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
529#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
530
531/* SCC Mode Register (PMSR) as used by Ethernet.
532*/
533#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
534#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
535#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
536#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
537#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
538#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
539#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
540#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
541#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
542#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
543#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
544#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
545#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
546
547/* Buffer descriptor control/status used by Ethernet receive.
548*/
549#define BD_ENET_RX_EMPTY ((ushort)0x8000)
550#define BD_ENET_RX_WRAP ((ushort)0x2000)
551#define BD_ENET_RX_INTR ((ushort)0x1000)
552#define BD_ENET_RX_LAST ((ushort)0x0800)
553#define BD_ENET_RX_FIRST ((ushort)0x0400)
554#define BD_ENET_RX_MISS ((ushort)0x0100)
555#define BD_ENET_RX_LG ((ushort)0x0020)
556#define BD_ENET_RX_NO ((ushort)0x0010)
557#define BD_ENET_RX_SH ((ushort)0x0008)
558#define BD_ENET_RX_CR ((ushort)0x0004)
559#define BD_ENET_RX_OV ((ushort)0x0002)
560#define BD_ENET_RX_CL ((ushort)0x0001)
561#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
562
563/* Buffer descriptor control/status used by Ethernet transmit.
564*/
565#define BD_ENET_TX_READY ((ushort)0x8000)
566#define BD_ENET_TX_PAD ((ushort)0x4000)
567#define BD_ENET_TX_WRAP ((ushort)0x2000)
568#define BD_ENET_TX_INTR ((ushort)0x1000)
569#define BD_ENET_TX_LAST ((ushort)0x0800)
570#define BD_ENET_TX_TC ((ushort)0x0400)
571#define BD_ENET_TX_DEF ((ushort)0x0200)
572#define BD_ENET_TX_HB ((ushort)0x0100)
573#define BD_ENET_TX_LC ((ushort)0x0080)
574#define BD_ENET_TX_RL ((ushort)0x0040)
575#define BD_ENET_TX_RCMASK ((ushort)0x003c)
576#define BD_ENET_TX_UN ((ushort)0x0002)
577#define BD_ENET_TX_CSL ((ushort)0x0001)
578#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
579
580/* SCC as UART
581*/
582typedef struct scc_uart {
583 sccp_t scc_genscc;
584 uint scc_res1; /* Reserved */
585 uint scc_res2; /* Reserved */
586 ushort scc_maxidl; /* Maximum idle chars */
587 ushort scc_idlc; /* temp idle counter */
588 ushort scc_brkcr; /* Break count register */
589 ushort scc_parec; /* receive parity error counter */
590 ushort scc_frmec; /* receive framing error counter */
591 ushort scc_nosec; /* receive noise counter */
592 ushort scc_brkec; /* receive break condition counter */
593 ushort scc_brkln; /* last received break length */
594 ushort scc_uaddr1; /* UART address character 1 */
595 ushort scc_uaddr2; /* UART address character 2 */
596 ushort scc_rtemp; /* Temp storage */
597 ushort scc_toseq; /* Transmit out of sequence char */
598 ushort scc_char1; /* control character 1 */
599 ushort scc_char2; /* control character 2 */
600 ushort scc_char3; /* control character 3 */
601 ushort scc_char4; /* control character 4 */
602 ushort scc_char5; /* control character 5 */
603 ushort scc_char6; /* control character 6 */
604 ushort scc_char7; /* control character 7 */
605 ushort scc_char8; /* control character 8 */
606 ushort scc_rccm; /* receive control character mask */
607 ushort scc_rccr; /* receive control character register */
608 ushort scc_rlbc; /* receive last break character */
609} scc_uart_t;
610
611/* SCC Event and Mask registers when it is used as a UART.
612*/
613#define UART_SCCM_GLR ((ushort)0x1000)
614#define UART_SCCM_GLT ((ushort)0x0800)
615#define UART_SCCM_AB ((ushort)0x0200)
616#define UART_SCCM_IDL ((ushort)0x0100)
617#define UART_SCCM_GRA ((ushort)0x0080)
618#define UART_SCCM_BRKE ((ushort)0x0040)
619#define UART_SCCM_BRKS ((ushort)0x0020)
620#define UART_SCCM_CCR ((ushort)0x0008)
621#define UART_SCCM_BSY ((ushort)0x0004)
622#define UART_SCCM_TX ((ushort)0x0002)
623#define UART_SCCM_RX ((ushort)0x0001)
624
625/* The SCC PMSR when used as a UART.
626*/
627#define SCU_PMSR_FLC ((ushort)0x8000)
628#define SCU_PMSR_SL ((ushort)0x4000)
629#define SCU_PMSR_CL ((ushort)0x3000)
630#define SCU_PMSR_UM ((ushort)0x0c00)
631#define SCU_PMSR_FRZ ((ushort)0x0200)
632#define SCU_PMSR_RZS ((ushort)0x0100)
633#define SCU_PMSR_SYN ((ushort)0x0080)
634#define SCU_PMSR_DRT ((ushort)0x0040)
635#define SCU_PMSR_PEN ((ushort)0x0010)
636#define SCU_PMSR_RPM ((ushort)0x000c)
637#define SCU_PMSR_REVP ((ushort)0x0008)
638#define SCU_PMSR_TPM ((ushort)0x0003)
639#define SCU_PMSR_TEVP ((ushort)0x0003)
640
641/* CPM Transparent mode SCC.
642 */
643typedef struct scc_trans {
644 sccp_t st_genscc;
645 uint st_cpres; /* Preset CRC */
646 uint st_cmask; /* Constant mask for CRC */
647} scc_trans_t;
648
649#define BD_SCC_TX_LAST ((ushort)0x0800)
650
651
652
653/* CPM interrupts. There are nearly 32 interrupts generated by CPM
654 * channels or devices. All of these are presented to the PPC core
655 * as a single interrupt. The CPM interrupt handler dispatches its
656 * own handlers, in a similar fashion to the PPC core handler. We
657 * use the table as defined in the manuals (i.e. no special high
658 * priority and SCC1 == SCCa, etc...).
659 */
660/* #define CPMVEC_NR 32 */
661/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
662/* #define CPMVEC_SCC1 ((ushort)0x1e) */
663/* #define CPMVEC_SCC2 ((ushort)0x1d) */
664/* #define CPMVEC_SCC3 ((ushort)0x1c) */
665/* #define CPMVEC_SCC4 ((ushort)0x1b) */
666/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
667/* #define CPMVEC_TIMER1 ((ushort)0x19) */
668/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
669/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
670/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
671/* #define CPMVEC_IDMA1 ((ushort)0x15) */
672/* #define CPMVEC_IDMA2 ((ushort)0x14) */
673/* #define CPMVEC_TIMER2 ((ushort)0x12) */
674/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
675/* #define CPMVEC_I2C ((ushort)0x10) */
676/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
677/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
678/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
679/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
680/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
681/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
682/* #define CPMVEC_TIMER4 ((ushort)0x07) */
683/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
684/* #define CPMVEC_SPI ((ushort)0x05) */
685/* #define CPMVEC_SMC1 ((ushort)0x04) */
686/* #define CPMVEC_SMC2 ((ushort)0x03) */
687/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
688/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
689/* #define CPMVEC_ERROR ((ushort)0x00) */
690
691extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
692
693/* CPM interrupt configuration vector.
694*/
695#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
696#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
697#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
698#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
699#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
700#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
701#define CICR_IEN ((uint)0x00000080) /* Int. enable */
702#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
703#endif /* __CPM_360__ */
diff --git a/arch/m68knommu/include/asm/cputime.h b/arch/m68knommu/include/asm/cputime.h
new file mode 100644
index 000000000000..a0c4a660878d
--- /dev/null
+++ b/arch/m68knommu/include/asm/cputime.h
@@ -0,0 +1,6 @@
1#ifndef __M68KNOMMU_CPUTIME_H
2#define __M68KNOMMU_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __M68KNOMMU_CPUTIME_H */
diff --git a/arch/m68knommu/include/asm/current.h b/arch/m68knommu/include/asm/current.h
new file mode 100644
index 000000000000..53ee0f9f7cef
--- /dev/null
+++ b/arch/m68knommu/include/asm/current.h
@@ -0,0 +1,24 @@
1#ifndef _M68KNOMMU_CURRENT_H
2#define _M68KNOMMU_CURRENT_H
3/*
4 * current.h
5 * (C) Copyright 2000, Lineo, David McCullough <davidm@uclinux.org>
6 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
7 *
8 * rather than dedicate a register (as the m68k source does), we
9 * just keep a global, we should probably just change it all to be
10 * current and lose _current_task.
11 */
12
13#include <linux/thread_info.h>
14
15struct task_struct;
16
17static inline struct task_struct *get_current(void)
18{
19 return(current_thread_info()->task);
20}
21
22#define current get_current()
23
24#endif /* _M68KNOMMU_CURRENT_H */
diff --git a/arch/m68knommu/include/asm/dbg.h b/arch/m68knommu/include/asm/dbg.h
new file mode 100644
index 000000000000..27af3270f671
--- /dev/null
+++ b/arch/m68knommu/include/asm/dbg.h
@@ -0,0 +1,6 @@
1#define DEBUG 1
2#ifdef CONFIG_COLDFIRE
3#define BREAK asm volatile ("halt")
4#else
5#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0
6#endif
diff --git a/arch/m68knommu/include/asm/delay.h b/arch/m68knommu/include/asm/delay.h
new file mode 100644
index 000000000000..55cbd6294ab6
--- /dev/null
+++ b/arch/m68knommu/include/asm/delay.h
@@ -0,0 +1,76 @@
1#ifndef _M68KNOMMU_DELAY_H
2#define _M68KNOMMU_DELAY_H
3
4/*
5 * Copyright (C) 1994 Hamish Macdonald
6 * Copyright (C) 2004 Greg Ungerer <gerg@snapgear.com>
7 */
8
9#include <asm/param.h>
10
11static inline void __delay(unsigned long loops)
12{
13#if defined(CONFIG_COLDFIRE)
14 /* The coldfire runs this loop at significantly different speeds
15 * depending upon long word alignment or not. We'll pad it to
16 * long word alignment which is the faster version.
17 * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
18 * than using a NOP (0x4e71) instruction because it executes in one
19 * cycle not three and doesn't allow for an arbitary delay waiting
20 * for bus cycles to finish. Also fp/a6 isn't likely to cause a
21 * stall waiting for the register to become valid if such is added
22 * to the coldfire at some stage.
23 */
24 __asm__ __volatile__ ( ".balignw 4, 0x4a8e\n\t"
25 "1: subql #1, %0\n\t"
26 "jcc 1b"
27 : "=d" (loops) : "0" (loops));
28#else
29 __asm__ __volatile__ ( "1: subql #1, %0\n\t"
30 "jcc 1b"
31 : "=d" (loops) : "0" (loops));
32#endif
33}
34
35/*
36 * Ideally we use a 32*32->64 multiply to calculate the number of
37 * loop iterations, but the older standard 68k and ColdFire do not
38 * have this instruction. So for them we have a clsoe approximation
39 * loop using 32*32->32 multiplies only. This calculation based on
40 * the ARM version of delay.
41 *
42 * We want to implement:
43 *
44 * loops = (usecs * 0x10c6 * HZ * loops_per_jiffy) / 2^32
45 */
46
47#define HZSCALE (268435456 / (1000000/HZ))
48
49extern unsigned long loops_per_jiffy;
50
51static inline void _udelay(unsigned long usecs)
52{
53#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \
54 defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \
55 defined(CONFIG_COLDFIRE)
56 __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6);
57#else
58 unsigned long tmp;
59
60 usecs *= 4295; /* 2**32 / 1000000 */
61 __asm__ ("mulul %2,%0:%1"
62 : "=d" (usecs), "=d" (tmp)
63 : "d" (usecs), "1" (loops_per_jiffy*HZ));
64 __delay(usecs);
65#endif
66}
67
68/*
69 * Moved the udelay() function into library code, no longer inlined.
70 * I had to change the algorithm because we are overflowing now on
71 * the faster ColdFire parts. The code is a little bigger, so it makes
72 * sense to library it.
73 */
74extern void udelay(unsigned long usecs);
75
76#endif /* defined(_M68KNOMMU_DELAY_H) */
diff --git a/arch/m68knommu/include/asm/device.h b/arch/m68knommu/include/asm/device.h
new file mode 100644
index 000000000000..d8f9872b0e2d
--- /dev/null
+++ b/arch/m68knommu/include/asm/device.h
@@ -0,0 +1,7 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#include <asm-generic/device.h>
7
diff --git a/arch/m68knommu/include/asm/div64.h b/arch/m68knommu/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/m68knommu/include/asm/div64.h
@@ -0,0 +1 @@
#include <asm-generic/div64.h>
diff --git a/arch/m68knommu/include/asm/dma-mapping.h b/arch/m68knommu/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..6aeab18e58bd
--- /dev/null
+++ b/arch/m68knommu/include/asm/dma-mapping.h
@@ -0,0 +1,10 @@
1#ifndef _M68KNOMMU_DMA_MAPPING_H
2#define _M68KNOMMU_DMA_MAPPING_H
3
4#ifdef CONFIG_PCI
5#include <asm-generic/dma-mapping.h>
6#else
7#include <asm-generic/dma-mapping-broken.h>
8#endif
9
10#endif /* _M68KNOMMU_DMA_MAPPING_H */
diff --git a/arch/m68knommu/include/asm/dma.h b/arch/m68knommu/include/asm/dma.h
new file mode 100644
index 000000000000..939a02056217
--- /dev/null
+++ b/arch/m68knommu/include/asm/dma.h
@@ -0,0 +1,494 @@
1#ifndef _M68K_DMA_H
2#define _M68K_DMA_H 1
3
4//#define DMA_DEBUG 1
5
6
7#ifdef CONFIG_COLDFIRE
8/*
9 * ColdFire DMA Model:
10 * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
11 * address mode emits a source address, and expects that the device will either
12 * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
13 * the device will place data on the correct byte(s) of the data bus, as the
14 * memory transactions are always 32 bits. This implies that only 32 bit
15 * devices will find single mode transfers useful. Dual address DMA mode
16 * performs two cycles: source read and destination write. ColdFire will
17 * align the data so that the device will always get the correct bytes, thus
18 * is useful for 8 and 16 bit devices. This is the mode that is supported
19 * below.
20 *
21 * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
22 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
23 *
24 * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
25 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
26 *
27 * APR/18/2002 : added proper support for MCF5272 DMA controller.
28 * Arthur Shipkowski (art@videon-central.com)
29 */
30
31#include <asm/coldfire.h>
32#include <asm/mcfsim.h>
33#include <asm/mcfdma.h>
34
35/*
36 * Set number of channels of DMA on ColdFire for different implementations.
37 */
38#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
39 defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
40#define MAX_M68K_DMA_CHANNELS 4
41#elif defined(CONFIG_M5272)
42#define MAX_M68K_DMA_CHANNELS 1
43#elif defined(CONFIG_M532x)
44#define MAX_M68K_DMA_CHANNELS 0
45#else
46#define MAX_M68K_DMA_CHANNELS 2
47#endif
48
49extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
50extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
51
52#if !defined(CONFIG_M5272)
53#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
54#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
55#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
56#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
57
58/* I/O to memory, 8 bits, mode */
59#define DMA_MODE_READ 0
60/* memory to I/O, 8 bits, mode */
61#define DMA_MODE_WRITE 1
62/* I/O to memory, 16 bits, mode */
63#define DMA_MODE_READ_WORD 2
64/* memory to I/O, 16 bits, mode */
65#define DMA_MODE_WRITE_WORD 3
66/* I/O to memory, 32 bits, mode */
67#define DMA_MODE_READ_LONG 4
68/* memory to I/O, 32 bits, mode */
69#define DMA_MODE_WRITE_LONG 5
70/* I/O to memory, 8 bits, single-address-mode */
71#define DMA_MODE_READ_SINGLE 8
72/* memory to I/O, 8 bits, single-address-mode */
73#define DMA_MODE_WRITE_SINGLE 9
74/* I/O to memory, 16 bits, single-address-mode */
75#define DMA_MODE_READ_WORD_SINGLE 10
76/* memory to I/O, 16 bits, single-address-mode */
77#define DMA_MODE_WRITE_WORD_SINGLE 11
78/* I/O to memory, 32 bits, single-address-mode */
79#define DMA_MODE_READ_LONG_SINGLE 12
80/* memory to I/O, 32 bits, single-address-mode */
81#define DMA_MODE_WRITE_LONG_SINGLE 13
82
83#else /* CONFIG_M5272 is defined */
84
85/* Source static-address mode */
86#define DMA_MODE_SRC_SA_BIT 0x01
87/* Two bits to select between all four modes */
88#define DMA_MODE_SSIZE_MASK 0x06
89/* Offset to shift bits in */
90#define DMA_MODE_SSIZE_OFF 0x01
91/* Destination static-address mode */
92#define DMA_MODE_DES_SA_BIT 0x10
93/* Two bits to select between all four modes */
94#define DMA_MODE_DSIZE_MASK 0x60
95/* Offset to shift bits in */
96#define DMA_MODE_DSIZE_OFF 0x05
97/* Size modifiers */
98#define DMA_MODE_SIZE_LONG 0x00
99#define DMA_MODE_SIZE_BYTE 0x01
100#define DMA_MODE_SIZE_WORD 0x02
101#define DMA_MODE_SIZE_LINE 0x03
102
103/*
104 * Aliases to help speed quick ports; these may be suboptimal, however. They
105 * do not include the SINGLE mode modifiers since the MCF5272 does not have a
106 * mode where the device is in control of its addressing.
107 */
108
109/* I/O to memory, 8 bits, mode */
110#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
111/* memory to I/O, 8 bits, mode */
112#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
113/* I/O to memory, 16 bits, mode */
114#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
115/* memory to I/O, 16 bits, mode */
116#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
117/* I/O to memory, 32 bits, mode */
118#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
119/* memory to I/O, 32 bits, mode */
120#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
121
122#endif /* !defined(CONFIG_M5272) */
123
124#if !defined(CONFIG_M5272)
125/* enable/disable a specific DMA channel */
126static __inline__ void enable_dma(unsigned int dmanr)
127{
128 volatile unsigned short *dmawp;
129
130#ifdef DMA_DEBUG
131 printk("enable_dma(dmanr=%d)\n", dmanr);
132#endif
133
134 dmawp = (unsigned short *) dma_base_addr[dmanr];
135 dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
136}
137
138static __inline__ void disable_dma(unsigned int dmanr)
139{
140 volatile unsigned short *dmawp;
141 volatile unsigned char *dmapb;
142
143#ifdef DMA_DEBUG
144 printk("disable_dma(dmanr=%d)\n", dmanr);
145#endif
146
147 dmawp = (unsigned short *) dma_base_addr[dmanr];
148 dmapb = (unsigned char *) dma_base_addr[dmanr];
149
150 /* Turn off external requests, and stop any DMA in progress */
151 dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
152 dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
153}
154
155/*
156 * Clear the 'DMA Pointer Flip Flop'.
157 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
158 * Use this once to initialize the FF to a known state.
159 * After that, keep track of it. :-)
160 * --- In order to do that, the DMA routines below should ---
161 * --- only be used while interrupts are disabled! ---
162 *
163 * This is a NOP for ColdFire. Provide a stub for compatibility.
164 */
165static __inline__ void clear_dma_ff(unsigned int dmanr)
166{
167}
168
169/* set mode (above) for a specific DMA channel */
170static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
171{
172
173 volatile unsigned char *dmabp;
174 volatile unsigned short *dmawp;
175
176#ifdef DMA_DEBUG
177 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
178#endif
179
180 dmabp = (unsigned char *) dma_base_addr[dmanr];
181 dmawp = (unsigned short *) dma_base_addr[dmanr];
182
183 // Clear config errors
184 dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
185
186 // Set command register
187 dmawp[MCFDMA_DCR] =
188 MCFDMA_DCR_INT | // Enable completion irq
189 MCFDMA_DCR_CS | // Force one xfer per request
190 MCFDMA_DCR_AA | // Enable auto alignment
191 // single-address-mode
192 ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
193 // sets s_rw (-> r/w) high if Memory to I/0
194 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
195 // Memory to I/O or I/O to Memory
196 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
197 // 32 bit, 16 bit or 8 bit transfers
198 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
199 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
200 MCFDMA_DCR_SSIZE_BYTE)) |
201 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
202 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
203 MCFDMA_DCR_DSIZE_BYTE));
204
205#ifdef DEBUG_DMA
206 printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
207 dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
208 (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
209#endif
210}
211
212/* Set transfer address for specific DMA channel */
213static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
214{
215 volatile unsigned short *dmawp;
216 volatile unsigned int *dmalp;
217
218#ifdef DMA_DEBUG
219 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
220#endif
221
222 dmawp = (unsigned short *) dma_base_addr[dmanr];
223 dmalp = (unsigned int *) dma_base_addr[dmanr];
224
225 // Determine which address registers are used for memory/device accesses
226 if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
227 // Source incrementing, must be memory
228 dmalp[MCFDMA_SAR] = a;
229 // Set dest address, must be device
230 dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
231 } else {
232 // Destination incrementing, must be memory
233 dmalp[MCFDMA_DAR] = a;
234 // Set source address, must be device
235 dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
236 }
237
238#ifdef DEBUG_DMA
239 printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
240 __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
241 (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
242 (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
243#endif
244}
245
246/*
247 * Specific for Coldfire - sets device address.
248 * Should be called after the mode set call, and before set DMA address.
249 */
250static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
251{
252#ifdef DMA_DEBUG
253 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
254#endif
255
256 dma_device_address[dmanr] = a;
257}
258
259/*
260 * NOTE 2: "count" represents _bytes_.
261 */
262static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
263{
264 volatile unsigned short *dmawp;
265
266#ifdef DMA_DEBUG
267 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
268#endif
269
270 dmawp = (unsigned short *) dma_base_addr[dmanr];
271 dmawp[MCFDMA_BCR] = (unsigned short)count;
272}
273
274/*
275 * Get DMA residue count. After a DMA transfer, this
276 * should return zero. Reading this while a DMA transfer is
277 * still in progress will return unpredictable results.
278 * Otherwise, it returns the number of _bytes_ left to transfer.
279 */
280static __inline__ int get_dma_residue(unsigned int dmanr)
281{
282 volatile unsigned short *dmawp;
283 unsigned short count;
284
285#ifdef DMA_DEBUG
286 printk("get_dma_residue(dmanr=%d)\n", dmanr);
287#endif
288
289 dmawp = (unsigned short *) dma_base_addr[dmanr];
290 count = dmawp[MCFDMA_BCR];
291 return((int) count);
292}
293#else /* CONFIG_M5272 is defined */
294
295/*
296 * The MCF5272 DMA controller is very different than the controller defined above
297 * in terms of register mapping. For instance, with the exception of the 16-bit
298 * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
299 *
300 * The big difference, however, is the lack of device-requested DMA. All modes
301 * are dual address transfer, and there is no 'device' setup or direction bit.
302 * You can DMA between a device and memory, between memory and memory, or even between
303 * two devices directly, with any combination of incrementing and non-incrementing
304 * addresses you choose. This puts a crimp in distinguishing between the 'device
305 * address' set up by set_dma_device_addr.
306 *
307 * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
308 * which will act exactly as above in -- it will look to see if the source is set to
309 * autoincrement, and if so it will make the source use the set_dma_addr value and the
310 * destination the set_dma_device_addr value. Otherwise the source will be set to the
311 * set_dma_device_addr value and the destination will get the set_dma_addr value.
312 *
313 * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
314 * and make it explicit. Depending on what you're doing, one of these two should work
315 * for you, but don't mix them in the same transfer setup.
316 */
317
318/* enable/disable a specific DMA channel */
319static __inline__ void enable_dma(unsigned int dmanr)
320{
321 volatile unsigned int *dmalp;
322
323#ifdef DMA_DEBUG
324 printk("enable_dma(dmanr=%d)\n", dmanr);
325#endif
326
327 dmalp = (unsigned int *) dma_base_addr[dmanr];
328 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
329}
330
331static __inline__ void disable_dma(unsigned int dmanr)
332{
333 volatile unsigned int *dmalp;
334
335#ifdef DMA_DEBUG
336 printk("disable_dma(dmanr=%d)\n", dmanr);
337#endif
338
339 dmalp = (unsigned int *) dma_base_addr[dmanr];
340
341 /* Turn off external requests, and stop any DMA in progress */
342 dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
343 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
344}
345
346/*
347 * Clear the 'DMA Pointer Flip Flop'.
348 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
349 * Use this once to initialize the FF to a known state.
350 * After that, keep track of it. :-)
351 * --- In order to do that, the DMA routines below should ---
352 * --- only be used while interrupts are disabled! ---
353 *
354 * This is a NOP for ColdFire. Provide a stub for compatibility.
355 */
356static __inline__ void clear_dma_ff(unsigned int dmanr)
357{
358}
359
360/* set mode (above) for a specific DMA channel */
361static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
362{
363
364 volatile unsigned int *dmalp;
365 volatile unsigned short *dmawp;
366
367#ifdef DMA_DEBUG
368 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
369#endif
370 dmalp = (unsigned int *) dma_base_addr[dmanr];
371 dmawp = (unsigned short *) dma_base_addr[dmanr];
372
373 // Clear config errors
374 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
375
376 // Set command register
377 dmalp[MCFDMA_DMR] =
378 MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting
379 MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data.
380 MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data.
381 // source static-address-mode
382 ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
383 // dest static-address-mode
384 ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
385 // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272
386 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
387 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
388
389 dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
390
391#ifdef DEBUG_DMA
392 printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
393 dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
394 (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
395#endif
396}
397
398/* Set transfer address for specific DMA channel */
399static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
400{
401 volatile unsigned int *dmalp;
402
403#ifdef DMA_DEBUG
404 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
405#endif
406
407 dmalp = (unsigned int *) dma_base_addr[dmanr];
408
409 // Determine which address registers are used for memory/device accesses
410 if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
411 // Source incrementing, must be memory
412 dmalp[MCFDMA_DSAR] = a;
413 // Set dest address, must be device
414 dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
415 } else {
416 // Destination incrementing, must be memory
417 dmalp[MCFDMA_DDAR] = a;
418 // Set source address, must be device
419 dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
420 }
421
422#ifdef DEBUG_DMA
423 printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
424 __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
425 (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
426 (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
427#endif
428}
429
430/*
431 * Specific for Coldfire - sets device address.
432 * Should be called after the mode set call, and before set DMA address.
433 */
434static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
435{
436#ifdef DMA_DEBUG
437 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
438#endif
439
440 dma_device_address[dmanr] = a;
441}
442
443/*
444 * NOTE 2: "count" represents _bytes_.
445 *
446 * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
447 */
448static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
449{
450 volatile unsigned int *dmalp;
451
452#ifdef DMA_DEBUG
453 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
454#endif
455
456 dmalp = (unsigned int *) dma_base_addr[dmanr];
457 dmalp[MCFDMA_DBCR] = count;
458}
459
460/*
461 * Get DMA residue count. After a DMA transfer, this
462 * should return zero. Reading this while a DMA transfer is
463 * still in progress will return unpredictable results.
464 * Otherwise, it returns the number of _bytes_ left to transfer.
465 */
466static __inline__ int get_dma_residue(unsigned int dmanr)
467{
468 volatile unsigned int *dmalp;
469 unsigned int count;
470
471#ifdef DMA_DEBUG
472 printk("get_dma_residue(dmanr=%d)\n", dmanr);
473#endif
474
475 dmalp = (unsigned int *) dma_base_addr[dmanr];
476 count = dmalp[MCFDMA_DBCR];
477 return(count);
478}
479
480#endif /* !defined(CONFIG_M5272) */
481#endif /* CONFIG_COLDFIRE */
482
483#define MAX_DMA_CHANNELS 8
484
485/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
486 occurrence should be flagged as an error. */
487/* under 2.4 it is actually needed by the new bootmem allocator */
488#define MAX_DMA_ADDRESS PAGE_OFFSET
489
490/* These are in kernel/dma.c: */
491extern int request_dma(unsigned int dmanr, const char *device_id); /* reserve a DMA channel */
492extern void free_dma(unsigned int dmanr); /* release it again */
493
494#endif /* _M68K_DMA_H */
diff --git a/arch/m68knommu/include/asm/elf.h b/arch/m68knommu/include/asm/elf.h
new file mode 100644
index 000000000000..27f0ec70fba8
--- /dev/null
+++ b/arch/m68knommu/include/asm/elf.h
@@ -0,0 +1,110 @@
1#ifndef __ASMm68k_ELF_H
2#define __ASMm68k_ELF_H
3
4/*
5 * ELF register definitions..
6 */
7
8#include <asm/ptrace.h>
9#include <asm/user.h>
10
11/*
12 * 68k ELF relocation types
13 */
14#define R_68K_NONE 0
15#define R_68K_32 1
16#define R_68K_16 2
17#define R_68K_8 3
18#define R_68K_PC32 4
19#define R_68K_PC16 5
20#define R_68K_PC8 6
21#define R_68K_GOT32 7
22#define R_68K_GOT16 8
23#define R_68K_GOT8 9
24#define R_68K_GOT32O 10
25#define R_68K_GOT16O 11
26#define R_68K_GOT8O 12
27#define R_68K_PLT32 13
28#define R_68K_PLT16 14
29#define R_68K_PLT8 15
30#define R_68K_PLT32O 16
31#define R_68K_PLT16O 17
32#define R_68K_PLT8O 18
33#define R_68K_COPY 19
34#define R_68K_GLOB_DAT 20
35#define R_68K_JMP_SLOT 21
36#define R_68K_RELATIVE 22
37
38typedef unsigned long elf_greg_t;
39
40#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
41typedef elf_greg_t elf_gregset_t[ELF_NGREG];
42
43typedef struct user_m68kfp_struct elf_fpregset_t;
44
45/*
46 * This is used to ensure we don't load something for the wrong architecture.
47 */
48#define elf_check_arch(x) ((x)->e_machine == EM_68K)
49
50/*
51 * These are used to set parameters in the core dumps.
52 */
53#define ELF_CLASS ELFCLASS32
54#define ELF_DATA ELFDATA2MSB
55#define ELF_ARCH EM_68K
56
57/* For SVR4/m68k the function pointer to be registered with `atexit' is
58 passed in %a1. Although my copy of the ABI has no such statement, it
59 is actually used on ASV. */
60#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
61
62#define USE_ELF_CORE_DUMP
63#define ELF_EXEC_PAGESIZE 4096
64
65/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
66 use of this is to invoke "./ld.so someprog" to test out a new version of
67 the loader. We need to make sure that it is out of the way of the program
68 that it will "exec", and that there is sufficient room for the brk. */
69
70#define ELF_ET_DYN_BASE 0xD0000000UL
71
72#define ELF_CORE_COPY_REGS(pr_reg, regs) \
73 /* Bleech. */ \
74 pr_reg[0] = regs->d1; \
75 pr_reg[1] = regs->d2; \
76 pr_reg[2] = regs->d3; \
77 pr_reg[3] = regs->d4; \
78 pr_reg[4] = regs->d5; \
79 pr_reg[7] = regs->a0; \
80 pr_reg[8] = regs->a1; \
81 pr_reg[14] = regs->d0; \
82 pr_reg[15] = rdusp(); \
83 pr_reg[16] = 0 /* regs->orig_d0 */; \
84 pr_reg[17] = regs->sr; \
85 pr_reg[18] = regs->pc; \
86 /* pr_reg[19] = (regs->format << 12) | regs->vector; */ \
87 { \
88 struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
89 pr_reg[5] = sw->d6; \
90 pr_reg[6] = sw->d7; \
91 pr_reg[10] = sw->a3; \
92 pr_reg[11] = sw->a4; \
93 pr_reg[12] = sw->a5; \
94 pr_reg[13] = sw->a6; \
95 }
96
97/* This yields a mask that user programs can use to figure out what
98 instruction set this cpu supports. */
99
100#define ELF_HWCAP (0)
101
102/* This yields a string that ld.so will use to load implementation
103 specific libraries for optimization. This is more specific in
104 intent than poking at uname or /proc/cpuinfo. */
105
106#define ELF_PLATFORM (NULL)
107
108#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
109
110#endif
diff --git a/arch/m68knommu/include/asm/elia.h b/arch/m68knommu/include/asm/elia.h
new file mode 100644
index 000000000000..e037d4e2de33
--- /dev/null
+++ b/arch/m68knommu/include/asm/elia.h
@@ -0,0 +1,41 @@
1/****************************************************************************/
2
3/*
4 * elia.h -- Lineo (formerly Moreton Bay) eLIA platform support.
5 *
6 * (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au)
7 * (C) Copyright 1999-2000, Lineo (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef elia_h
12#define elia_h
13/****************************************************************************/
14
15#include <asm/coldfire.h>
16
17#ifdef CONFIG_eLIA
18
19/*
20 * The serial port DTR and DCD lines are also on the Parallel I/O
21 * as well, so define those too.
22 */
23
24#define eLIA_DCD1 0x0001
25#define eLIA_DCD0 0x0002
26#define eLIA_DTR1 0x0004
27#define eLIA_DTR0 0x0008
28
29#define eLIA_PCIRESET 0x0020
30
31/*
32 * Kernel macros to set and unset the LEDs.
33 */
34#ifndef __ASSEMBLY__
35extern unsigned short ppdata;
36#endif /* __ASSEMBLY__ */
37
38#endif /* CONFIG_eLIA */
39
40/****************************************************************************/
41#endif /* elia_h */
diff --git a/arch/m68knommu/include/asm/emergency-restart.h b/arch/m68knommu/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/m68knommu/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/m68knommu/include/asm/entry.h b/arch/m68knommu/include/asm/entry.h
new file mode 100644
index 000000000000..c2553d26273d
--- /dev/null
+++ b/arch/m68knommu/include/asm/entry.h
@@ -0,0 +1,182 @@
1#ifndef __M68KNOMMU_ENTRY_H
2#define __M68KNOMMU_ENTRY_H
3
4#include <asm/setup.h>
5#include <asm/page.h>
6
7/*
8 * Stack layout in 'ret_from_exception':
9 *
10 * This allows access to the syscall arguments in registers d1-d5
11 *
12 * 0(sp) - d1
13 * 4(sp) - d2
14 * 8(sp) - d3
15 * C(sp) - d4
16 * 10(sp) - d5
17 * 14(sp) - a0
18 * 18(sp) - a1
19 * 1C(sp) - a2
20 * 20(sp) - d0
21 * 24(sp) - orig_d0
22 * 28(sp) - stack adjustment
23 * 2C(sp) - [ sr ] [ format & vector ]
24 * 2E(sp) - [ pc-hiword ] [ sr ]
25 * 30(sp) - [ pc-loword ] [ pc-hiword ]
26 * 32(sp) - [ format & vector ] [ pc-loword ]
27 * ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
28 * M68K COLDFIRE
29 */
30
31#define ALLOWINT 0xf8ff
32
33#ifdef __ASSEMBLY__
34
35/* process bits for task_struct.flags */
36PF_TRACESYS_OFF = 3
37PF_TRACESYS_BIT = 5
38PF_PTRACED_OFF = 3
39PF_PTRACED_BIT = 4
40PF_DTRACE_OFF = 1
41PF_DTRACE_BIT = 5
42
43LENOSYS = 38
44
45#define SWITCH_STACK_SIZE (6*4+4) /* Includes return address */
46
47/*
48 * This defines the normal kernel pt-regs layout.
49 *
50 * regs are a2-a6 and d6-d7 preserved by C code
51 * the kernel doesn't mess with usp unless it needs to
52 */
53
54#ifdef CONFIG_COLDFIRE
55/*
56 * This is made a little more tricky on the ColdFire. There is no
57 * separate kernel and user stack pointers. Need to artificially
58 * construct a usp in software... When doing this we need to disable
59 * interrupts, otherwise bad things could happen.
60 */
61.macro SAVE_ALL
62 move #0x2700,%sr /* disable intrs */
63 btst #5,%sp@(2) /* from user? */
64 bnes 6f /* no, skip */
65 movel %sp,sw_usp /* save user sp */
66 addql #8,sw_usp /* remove exception */
67 movel sw_ksp,%sp /* kernel sp */
68 subql #8,%sp /* room for exception */
69 clrl %sp@- /* stkadj */
70 movel %d0,%sp@- /* orig d0 */
71 movel %d0,%sp@- /* d0 */
72 lea %sp@(-32),%sp /* space for 8 regs */
73 moveml %d1-%d5/%a0-%a2,%sp@
74 movel sw_usp,%a0 /* get usp */
75 movel %a0@-,%sp@(PT_PC) /* copy exception program counter */
76 movel %a0@-,%sp@(PT_FORMATVEC)/* copy exception format/vector/sr */
77 bra 7f
78 6:
79 clrl %sp@- /* stkadj */
80 movel %d0,%sp@- /* orig d0 */
81 movel %d0,%sp@- /* d0 */
82 lea %sp@(-32),%sp /* space for 8 regs */
83 moveml %d1-%d5/%a0-%a2,%sp@
84 7:
85.endm
86
87.macro RESTORE_ALL
88 btst #5,%sp@(PT_SR) /* going user? */
89 bnes 8f /* no, skip */
90 move #0x2700,%sr /* disable intrs */
91 movel sw_usp,%a0 /* get usp */
92 movel %sp@(PT_PC),%a0@- /* copy exception program counter */
93 movel %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */
94 moveml %sp@,%d1-%d5/%a0-%a2
95 lea %sp@(32),%sp /* space for 8 regs */
96 movel %sp@+,%d0
97 addql #4,%sp /* orig d0 */
98 addl %sp@+,%sp /* stkadj */
99 addql #8,%sp /* remove exception */
100 movel %sp,sw_ksp /* save ksp */
101 subql #8,sw_usp /* set exception */
102 movel sw_usp,%sp /* restore usp */
103 rte
104 8:
105 moveml %sp@,%d1-%d5/%a0-%a2
106 lea %sp@(32),%sp /* space for 8 regs */
107 movel %sp@+,%d0
108 addql #4,%sp /* orig d0 */
109 addl %sp@+,%sp /* stkadj */
110 rte
111.endm
112
113/*
114 * Quick exception save, use current stack only.
115 */
116.macro SAVE_LOCAL
117 move #0x2700,%sr /* disable intrs */
118 clrl %sp@- /* stkadj */
119 movel %d0,%sp@- /* orig d0 */
120 movel %d0,%sp@- /* d0 */
121 lea %sp@(-32),%sp /* space for 8 regs */
122 moveml %d1-%d5/%a0-%a2,%sp@
123.endm
124
125.macro RESTORE_LOCAL
126 moveml %sp@,%d1-%d5/%a0-%a2
127 lea %sp@(32),%sp /* space for 8 regs */
128 movel %sp@+,%d0
129 addql #4,%sp /* orig d0 */
130 addl %sp@+,%sp /* stkadj */
131 rte
132.endm
133
134.macro SAVE_SWITCH_STACK
135 lea %sp@(-24),%sp /* 6 regs */
136 moveml %a3-%a6/%d6-%d7,%sp@
137.endm
138
139.macro RESTORE_SWITCH_STACK
140 moveml %sp@,%a3-%a6/%d6-%d7
141 lea %sp@(24),%sp /* 6 regs */
142.endm
143
144/*
145 * Software copy of the user and kernel stack pointers... Ugh...
146 * Need these to get around ColdFire not having separate kernel
147 * and user stack pointers.
148 */
149.globl sw_usp
150.globl sw_ksp
151
152#else /* !CONFIG_COLDFIRE */
153
154/*
155 * Standard 68k interrupt entry and exit macros.
156 */
157.macro SAVE_ALL
158 clrl %sp@- /* stkadj */
159 movel %d0,%sp@- /* orig d0 */
160 movel %d0,%sp@- /* d0 */
161 moveml %d1-%d5/%a0-%a2,%sp@-
162.endm
163
164.macro RESTORE_ALL
165 moveml %sp@+,%a0-%a2/%d1-%d5
166 movel %sp@+,%d0
167 addql #4,%sp /* orig d0 */
168 addl %sp@+,%sp /* stkadj */
169 rte
170.endm
171
172.macro SAVE_SWITCH_STACK
173 moveml %a3-%a6/%d6-%d7,%sp@-
174.endm
175
176.macro RESTORE_SWITCH_STACK
177 moveml %sp@+,%a3-%a6/%d6-%d7
178.endm
179
180#endif /* !CONFIG_COLDFIRE */
181#endif /* __ASSEMBLY__ */
182#endif /* __M68KNOMMU_ENTRY_H */
diff --git a/arch/m68knommu/include/asm/errno.h b/arch/m68knommu/include/asm/errno.h
new file mode 100644
index 000000000000..7e8c22b9a5e6
--- /dev/null
+++ b/arch/m68knommu/include/asm/errno.h
@@ -0,0 +1 @@
#include <asm-m68k/errno.h>
diff --git a/arch/m68knommu/include/asm/fb.h b/arch/m68knommu/include/asm/fb.h
new file mode 100644
index 000000000000..c7df38030992
--- /dev/null
+++ b/arch/m68knommu/include/asm/fb.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3#include <linux/fb.h>
4
5#define fb_pgprotect(...) do {} while (0)
6
7static inline int fb_is_primary_device(struct fb_info *info)
8{
9 return 0;
10}
11
12#endif /* _ASM_FB_H_ */
diff --git a/arch/m68knommu/include/asm/fcntl.h b/arch/m68knommu/include/asm/fcntl.h
new file mode 100644
index 000000000000..f6a552cda4cd
--- /dev/null
+++ b/arch/m68knommu/include/asm/fcntl.h
@@ -0,0 +1 @@
#include <asm-m68k/fcntl.h>
diff --git a/arch/m68knommu/include/asm/flat.h b/arch/m68knommu/include/asm/flat.h
new file mode 100644
index 000000000000..814b5174a8e0
--- /dev/null
+++ b/arch/m68knommu/include/asm/flat.h
@@ -0,0 +1,17 @@
1/*
2 * include/asm-m68knommu/flat.h -- uClinux flat-format executables
3 */
4
5#ifndef __M68KNOMMU_FLAT_H__
6#define __M68KNOMMU_FLAT_H__
7
8#define flat_stack_align(sp) /* nothing needed */
9#define flat_argvp_envp_on_stack() 1
10#define flat_old_ram_flag(flags) (flags)
11#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
12#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
13#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
14#define flat_get_relocate_addr(rel) (rel)
15#define flat_set_persistent(relval, p) 0
16
17#endif /* __M68KNOMMU_FLAT_H__ */
diff --git a/arch/m68knommu/include/asm/fpu.h b/arch/m68knommu/include/asm/fpu.h
new file mode 100644
index 000000000000..b16b2e4fca2a
--- /dev/null
+++ b/arch/m68knommu/include/asm/fpu.h
@@ -0,0 +1,21 @@
1#ifndef __M68KNOMMU_FPU_H
2#define __M68KNOMMU_FPU_H
3
4
5/*
6 * MAX floating point unit state size (FSAVE/FRESTORE)
7 */
8#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
9#define FPSTATESIZE (216/sizeof(unsigned char))
10#elif defined(CONFIG_M68040)
11#define FPSTATESIZE (96/sizeof(unsigned char))
12#elif defined(CONFIG_M68KFPU_EMU)
13#define FPSTATESIZE (28/sizeof(unsigned char))
14#elif defined(CONFIG_M68060)
15#define FPSTATESIZE (12/sizeof(unsigned char))
16#else
17/* Assume no FP unit present then... */
18#define FPSTATESIZE (2) /* dummy size */
19#endif
20
21#endif /* __M68K_FPU_H */
diff --git a/arch/m68knommu/include/asm/futex.h b/arch/m68knommu/include/asm/futex.h
new file mode 100644
index 000000000000..6a332a9f099c
--- /dev/null
+++ b/arch/m68knommu/include/asm/futex.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_FUTEX_H
2#define _ASM_FUTEX_H
3
4#include <asm-generic/futex.h>
5
6#endif
diff --git a/arch/m68knommu/include/asm/hardirq.h b/arch/m68knommu/include/asm/hardirq.h
new file mode 100644
index 000000000000..bfad28149a49
--- /dev/null
+++ b/arch/m68knommu/include/asm/hardirq.h
@@ -0,0 +1,27 @@
1#ifndef __M68K_HARDIRQ_H
2#define __M68K_HARDIRQ_H
3
4#include <linux/cache.h>
5#include <linux/threads.h>
6#include <asm/irq.h>
7
8typedef struct {
9 unsigned int __softirq_pending;
10} ____cacheline_aligned irq_cpustat_t;
11
12#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
13
14#define HARDIRQ_BITS 8
15
16/*
17 * The hardirq mask has to be large enough to have
18 * space for potentially all IRQ sources in the system
19 * nesting on a single CPU:
20 */
21#if (1 << HARDIRQ_BITS) < NR_IRQS
22# error HARDIRQ_BITS is too low!
23#endif
24
25void ack_bad_irq(unsigned int irq);
26
27#endif /* __M68K_HARDIRQ_H */
diff --git a/arch/m68knommu/include/asm/hw_irq.h b/arch/m68knommu/include/asm/hw_irq.h
new file mode 100644
index 000000000000..f3ec9e5ae049
--- /dev/null
+++ b/arch/m68knommu/include/asm/hw_irq.h
@@ -0,0 +1,4 @@
1#ifndef __M68KNOMMU_HW_IRQ_H__
2#define __M68KNOMMU_HW_IRQ_H__
3
4#endif /* __M68KNOMMU_HW_IRQ_H__ */
diff --git a/arch/m68knommu/include/asm/hwtest.h b/arch/m68knommu/include/asm/hwtest.h
new file mode 100644
index 000000000000..700626a1b1bf
--- /dev/null
+++ b/arch/m68knommu/include/asm/hwtest.h
@@ -0,0 +1 @@
#include <asm-m68k/hwtest.h>
diff --git a/arch/m68knommu/include/asm/io.h b/arch/m68knommu/include/asm/io.h
new file mode 100644
index 000000000000..6adef1ee2082
--- /dev/null
+++ b/arch/m68knommu/include/asm/io.h
@@ -0,0 +1,194 @@
1#ifndef _M68KNOMMU_IO_H
2#define _M68KNOMMU_IO_H
3
4#ifdef __KERNEL__
5
6
7/*
8 * These are for ISA/PCI shared memory _only_ and should never be used
9 * on any other type of memory, including Zorro memory. They are meant to
10 * access the bus in the bus byte order which is little-endian!.
11 *
12 * readX/writeX() are used to access memory mapped devices. On some
13 * architectures the memory mapped IO stuff needs to be accessed
14 * differently. On the m68k architecture, we just read/write the
15 * memory location directly.
16 */
17/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
18 * two accesses to memory, which may be undesireable for some devices.
19 */
20
21/*
22 * swap functions are sometimes needed to interface little-endian hardware
23 */
24static inline unsigned short _swapw(volatile unsigned short v)
25{
26 return ((v << 8) | (v >> 8));
27}
28
29static inline unsigned int _swapl(volatile unsigned long v)
30{
31 return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
32}
33
34#define readb(addr) \
35 ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
36#define readw(addr) \
37 ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
38#define readl(addr) \
39 ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
40
41#define readb_relaxed(addr) readb(addr)
42#define readw_relaxed(addr) readw(addr)
43#define readl_relaxed(addr) readl(addr)
44
45#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
46#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
47#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
48
49#define __raw_readb readb
50#define __raw_readw readw
51#define __raw_readl readl
52#define __raw_writeb writeb
53#define __raw_writew writew
54#define __raw_writel writel
55
56static inline void io_outsb(unsigned int addr, void *buf, int len)
57{
58 volatile unsigned char *ap = (volatile unsigned char *) addr;
59 unsigned char *bp = (unsigned char *) buf;
60 while (len--)
61 *ap = *bp++;
62}
63
64static inline void io_outsw(unsigned int addr, void *buf, int len)
65{
66 volatile unsigned short *ap = (volatile unsigned short *) addr;
67 unsigned short *bp = (unsigned short *) buf;
68 while (len--)
69 *ap = _swapw(*bp++);
70}
71
72static inline void io_outsl(unsigned int addr, void *buf, int len)
73{
74 volatile unsigned int *ap = (volatile unsigned int *) addr;
75 unsigned int *bp = (unsigned int *) buf;
76 while (len--)
77 *ap = _swapl(*bp++);
78}
79
80static inline void io_insb(unsigned int addr, void *buf, int len)
81{
82 volatile unsigned char *ap = (volatile unsigned char *) addr;
83 unsigned char *bp = (unsigned char *) buf;
84 while (len--)
85 *bp++ = *ap;
86}
87
88static inline void io_insw(unsigned int addr, void *buf, int len)
89{
90 volatile unsigned short *ap = (volatile unsigned short *) addr;
91 unsigned short *bp = (unsigned short *) buf;
92 while (len--)
93 *bp++ = _swapw(*ap);
94}
95
96static inline void io_insl(unsigned int addr, void *buf, int len)
97{
98 volatile unsigned int *ap = (volatile unsigned int *) addr;
99 unsigned int *bp = (unsigned int *) buf;
100 while (len--)
101 *bp++ = _swapl(*ap);
102}
103
104#define mmiowb()
105
106/*
107 * make the short names macros so specific devices
108 * can override them as required
109 */
110
111#define memset_io(a,b,c) memset((void *)(a),(b),(c))
112#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
113#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
114
115#define inb(addr) readb(addr)
116#define inw(addr) readw(addr)
117#define inl(addr) readl(addr)
118#define outb(x,addr) ((void) writeb(x,addr))
119#define outw(x,addr) ((void) writew(x,addr))
120#define outl(x,addr) ((void) writel(x,addr))
121
122#define inb_p(addr) inb(addr)
123#define inw_p(addr) inw(addr)
124#define inl_p(addr) inl(addr)
125#define outb_p(x,addr) outb(x,addr)
126#define outw_p(x,addr) outw(x,addr)
127#define outl_p(x,addr) outl(x,addr)
128
129#define outsb(a,b,l) io_outsb(a,b,l)
130#define outsw(a,b,l) io_outsw(a,b,l)
131#define outsl(a,b,l) io_outsl(a,b,l)
132
133#define insb(a,b,l) io_insb(a,b,l)
134#define insw(a,b,l) io_insw(a,b,l)
135#define insl(a,b,l) io_insl(a,b,l)
136
137#define IO_SPACE_LIMIT 0xffff
138
139
140/* Values for nocacheflag and cmode */
141#define IOMAP_FULL_CACHING 0
142#define IOMAP_NOCACHE_SER 1
143#define IOMAP_NOCACHE_NONSER 2
144#define IOMAP_WRITETHROUGH 3
145
146extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
147extern void __iounmap(void *addr, unsigned long size);
148
149static inline void *ioremap(unsigned long physaddr, unsigned long size)
150{
151 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
152}
153static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
154{
155 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
156}
157static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
158{
159 return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
160}
161static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
162{
163 return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
164}
165
166extern void iounmap(void *addr);
167
168/* Pages to physical address... */
169#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
170#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
171
172/*
173 * Macros used for converting between virtual and physical mappings.
174 */
175#define phys_to_virt(vaddr) ((void *) (vaddr))
176#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
177
178#define virt_to_bus virt_to_phys
179#define bus_to_virt phys_to_virt
180
181/*
182 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
183 * access
184 */
185#define xlate_dev_mem_ptr(p) __va(p)
186
187/*
188 * Convert a virtual cached pointer to an uncached pointer
189 */
190#define xlate_dev_kmem_ptr(p) p
191
192#endif /* __KERNEL__ */
193
194#endif /* _M68KNOMMU_IO_H */
diff --git a/arch/m68knommu/include/asm/ioctl.h b/arch/m68knommu/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/m68knommu/include/asm/ioctl.h
@@ -0,0 +1 @@
#include <asm-generic/ioctl.h>
diff --git a/arch/m68knommu/include/asm/ioctls.h b/arch/m68knommu/include/asm/ioctls.h
new file mode 100644
index 000000000000..0b1eb4d85059
--- /dev/null
+++ b/arch/m68knommu/include/asm/ioctls.h
@@ -0,0 +1 @@
#include <asm-m68k/ioctls.h>
diff --git a/arch/m68knommu/include/asm/ipcbuf.h b/arch/m68knommu/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..e4a7be6dd706
--- /dev/null
+++ b/arch/m68knommu/include/asm/ipcbuf.h
@@ -0,0 +1 @@
#include <asm-m68k/ipcbuf.h>
diff --git a/arch/m68knommu/include/asm/irq.h b/arch/m68knommu/include/asm/irq.h
new file mode 100644
index 000000000000..9373c31ac87d
--- /dev/null
+++ b/arch/m68knommu/include/asm/irq.h
@@ -0,0 +1,26 @@
1#ifndef _M68KNOMMU_IRQ_H_
2#define _M68KNOMMU_IRQ_H_
3
4#ifdef CONFIG_COLDFIRE
5/*
6 * On the ColdFire we keep track of all vectors. That way drivers
7 * can register whatever vector number they wish, and we can deal
8 * with it.
9 */
10#define SYS_IRQS 256
11#define NR_IRQS SYS_IRQS
12
13#else
14
15/*
16 * # of m68k interrupts
17 */
18#define SYS_IRQS 8
19#define NR_IRQS (24 + SYS_IRQS)
20
21#endif /* CONFIG_COLDFIRE */
22
23
24#define irq_canonicalize(irq) (irq)
25
26#endif /* _M68KNOMMU_IRQ_H_ */
diff --git a/arch/m68knommu/include/asm/irq_regs.h b/arch/m68knommu/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/m68knommu/include/asm/irq_regs.h
@@ -0,0 +1 @@
#include <asm-generic/irq_regs.h>
diff --git a/arch/m68knommu/include/asm/kdebug.h b/arch/m68knommu/include/asm/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/arch/m68knommu/include/asm/kdebug.h
@@ -0,0 +1 @@
#include <asm-generic/kdebug.h>
diff --git a/arch/m68knommu/include/asm/kmap_types.h b/arch/m68knommu/include/asm/kmap_types.h
new file mode 100644
index 000000000000..bfb6707575d1
--- /dev/null
+++ b/arch/m68knommu/include/asm/kmap_types.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_M68K_KMAP_TYPES_H
2#define __ASM_M68K_KMAP_TYPES_H
3
4enum km_type {
5 KM_BOUNCE_READ,
6 KM_SKB_SUNRPC_DATA,
7 KM_SKB_DATA_SOFTIRQ,
8 KM_USER0,
9 KM_USER1,
10 KM_BIO_SRC_IRQ,
11 KM_BIO_DST_IRQ,
12 KM_PTE0,
13 KM_PTE1,
14 KM_IRQ0,
15 KM_IRQ1,
16 KM_SOFTIRQ0,
17 KM_SOFTIRQ1,
18 KM_TYPE_NR
19};
20
21#endif
diff --git a/arch/m68knommu/include/asm/linkage.h b/arch/m68knommu/include/asm/linkage.h
new file mode 100644
index 000000000000..c288a19ff489
--- /dev/null
+++ b/arch/m68knommu/include/asm/linkage.h
@@ -0,0 +1 @@
#include <asm-m68k/linkage.h>
diff --git a/arch/m68knommu/include/asm/local.h b/arch/m68knommu/include/asm/local.h
new file mode 100644
index 000000000000..84a39c1b86f8
--- /dev/null
+++ b/arch/m68knommu/include/asm/local.h
@@ -0,0 +1,6 @@
1#ifndef __M68KNOMMU_LOCAL_H
2#define __M68KNOMMU_LOCAL_H
3
4#include <asm-generic/local.h>
5
6#endif /* __M68KNOMMU_LOCAL_H */
diff --git a/arch/m68knommu/include/asm/m5206sim.h b/arch/m68knommu/include/asm/m5206sim.h
new file mode 100644
index 000000000000..7e3594dea88b
--- /dev/null
+++ b/arch/m68knommu/include/asm/m5206sim.h
@@ -0,0 +1,131 @@
1/****************************************************************************/
2
3/*
4 * m5206sim.h -- ColdFire 5206 System Integration Module support.
5 *
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef m5206sim_h
12#define m5206sim_h
13/****************************************************************************/
14
15
16/*
17 * Define the 5206 SIM register set addresses.
18 */
19#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
20#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
21#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
22#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
23#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
24#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
25#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
26#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
27#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
28#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
29#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
30#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
31#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
32#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
33#ifdef CONFIG_M5206e
34#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
35#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
36#endif
37
38#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */
39#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */
40
41#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
42#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
43
44#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
45#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
46
47#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
48#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
49#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */
50#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */
51#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */
52#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */
53#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */
54#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */
55
56#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
57#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
58#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
59#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
60#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
61#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
62#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
63#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
64#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
65#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
66#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
67#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
68#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
69#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
70#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
71#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
72#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
73#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
74#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
75#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
76#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
77#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
78#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
79#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
80#define MCFSIM_DMCR 0xc6 /* Default control */
81
82#ifdef CONFIG_M5206e
83#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */
84#else
85#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
86#endif
87
88#define MCFSIM_PADDR 0x1c5 /* Parallel Direction (r/w) */
89#define MCFSIM_PADAT 0x1c9 /* Parallel Port Value (r/w) */
90
91/*
92 * Some symbol defines for the Parallel Port Pin Assignment Register
93 */
94#ifdef CONFIG_M5206e
95#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
96 /* Clear to select T0 input */
97#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
98 /* Clear to select T0 output */
99#endif
100
101/*
102 * Some symbol defines for the Interrupt Control Register
103 */
104#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
105#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
106#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
107#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
108#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
109#ifdef CONFIG_M5206e
110#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
111#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
112#endif
113
114#if defined(CONFIG_M5206e)
115#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */
116#endif
117
118/*
119 * Macro to get and set IMR register. It is 16 bits on the 5206.
120 */
121#define mcf_getimr() \
122 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
123
124#define mcf_setimr(imr) \
125 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
126
127#define mcf_getipr() \
128 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
129
130/****************************************************************************/
131#endif /* m5206sim_h */
diff --git a/arch/m68knommu/include/asm/m520xsim.h b/arch/m68knommu/include/asm/m520xsim.h
new file mode 100644
index 000000000000..49d016e6391a
--- /dev/null
+++ b/arch/m68knommu/include/asm/m520xsim.h
@@ -0,0 +1,63 @@
1/****************************************************************************/
2
3/*
4 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
5 *
6 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
7 */
8
9/****************************************************************************/
10#ifndef m520xsim_h
11#define m520xsim_h
12/****************************************************************************/
13
14
15/*
16 * Define the 5282 SIM register set addresses.
17 */
18#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
19#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
20#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
21#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
22#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
23#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
24#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
25#define MCFINTC_ICR0 0x40 /* Base ICR register */
26
27#define MCFINT_VECBASE 64
28#define MCFINT_UART0 26 /* Interrupt number for UART0 */
29#define MCFINT_UART1 27 /* Interrupt number for UART1 */
30#define MCFINT_UART2 28 /* Interrupt number for UART2 */
31#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
32#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
33
34/*
35 * SDRAM configuration registers.
36 */
37#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
38#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
39#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
40#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
41#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
42#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
43
44
45#define MCF_GPIO_PAR_UART (0xA4036)
46#define MCF_GPIO_PAR_FECI2C (0xA4033)
47#define MCF_GPIO_PAR_FEC (0xA4038)
48
49#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
50#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
51
52#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
53#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
54
55#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
56#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
57
58#define ICR_INTRCONF 0x05
59#define MCFPIT_IMR MCFINTC_IMRL
60#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
61
62/****************************************************************************/
63#endif /* m520xsim_h */
diff --git a/arch/m68knommu/include/asm/m523xsim.h b/arch/m68knommu/include/asm/m523xsim.h
new file mode 100644
index 000000000000..bf397313e93f
--- /dev/null
+++ b/arch/m68knommu/include/asm/m523xsim.h
@@ -0,0 +1,45 @@
1/****************************************************************************/
2
3/*
4 * m523xsim.h -- ColdFire 523x System Integration Module support.
5 *
6 * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
7 */
8
9/****************************************************************************/
10#ifndef m523xsim_h
11#define m523xsim_h
12/****************************************************************************/
13
14
15/*
16 * Define the 523x SIM register set addresses.
17 */
18#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
19#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
20#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
21#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
22#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
23#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
24#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
25#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
26#define MCFINTC_IRLR 0x18 /* */
27#define MCFINTC_IACKL 0x19 /* */
28#define MCFINTC_ICR0 0x40 /* Base ICR register */
29
30#define MCFINT_VECBASE 64 /* Vector base number */
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
33#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
34
35/*
36 * SDRAM configuration registers.
37 */
38#define MCFSIM_DCR 0x44 /* SDRAM control */
39#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
40#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
41#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
42#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
43
44/****************************************************************************/
45#endif /* m523xsim_h */
diff --git a/arch/m68knommu/include/asm/m5249sim.h b/arch/m68knommu/include/asm/m5249sim.h
new file mode 100644
index 000000000000..366eb8602d2f
--- /dev/null
+++ b/arch/m68knommu/include/asm/m5249sim.h
@@ -0,0 +1,209 @@
1/****************************************************************************/
2
3/*
4 * m5249sim.h -- ColdFire 5249 System Integration Module support.
5 *
6 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m5249sim_h
11#define m5249sim_h
12/****************************************************************************/
13
14/*
15 * Define the 5249 SIM register set addresses.
16 */
17#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
18#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
19#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
20#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
21#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
22#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
23#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
24#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
25#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
26#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
27#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
28#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
29#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
30#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
31#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
32#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
33#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
34#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
35#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
36#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
37#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
38#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
39
40#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
41#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
42#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
43#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
44#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
45#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
46#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
47#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
48#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
49#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
50#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
51#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
52
53#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
54#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
55#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
56#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
57#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
58
59
60/*
61 * Some symbol defines for the above...
62 */
63#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
64#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
65#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
66#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
67#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
68#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
69#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
70#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
72
73/*
74 * General purpose IO registers (in MBAR2).
75 */
76#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */
77#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */
78#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */
79#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */
80#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */
81#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */
82#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */
83#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */
84
85#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
86#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
87#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */
88
89#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */
90#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */
91#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */
92#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */
93#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */
94#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */
95#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */
96#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */
97
98#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */
99
100#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
101#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
102
103
104/*
105 * Macro to set IMR register. It is 32 bits on the 5249.
106 */
107#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */
108
109#define mcf_getimr() \
110 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
111
112#define mcf_setimr(imr) \
113 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
114
115#define mcf_getipr() \
116 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
117
118/****************************************************************************/
119
120#ifdef __ASSEMBLER__
121
122/*
123 * The M5249C3 board needs a little help getting all its SIM devices
124 * initialized at kernel start time. dBUG doesn't set much up, so
125 * we need to do it manually.
126 */
127.macro m5249c3_setup
128 /*
129 * Set MBAR1 and MBAR2, just incase they are not set.
130 */
131 movel #0x10000001,%a0
132 movec %a0,%MBAR /* map MBAR region */
133 subql #1,%a0 /* get MBAR address in a0 */
134
135 movel #0x80000001,%a1
136 movec %a1,#3086 /* map MBAR2 region */
137 subql #1,%a1 /* get MBAR2 address in a1 */
138
139 /*
140 * Move secondary interrupts to base at 128.
141 */
142 moveb #0x80,%d0
143 moveb %d0,0x16b(%a1) /* interrupt base register */
144
145 /*
146 * Work around broken CSMR0/DRAM vector problem.
147 */
148 movel #0x001F0021,%d0 /* disable C/I bit */
149 movel %d0,0x84(%a0) /* set CSMR0 */
150
151 /*
152 * Disable the PLL firstly. (Who knows what state it is
153 * in here!).
154 */
155 movel 0x180(%a1),%d0 /* get current PLL value */
156 andl #0xfffffffe,%d0 /* PLL bypass first */
157 movel %d0,0x180(%a1) /* set PLL register */
158 nop
159
160#if CONFIG_CLOCK_FREQ == 140000000
161 /*
162 * Set initial clock frequency. This assumes M5249C3 board
163 * is fitted with 11.2896MHz crystal. It will program the
164 * PLL for 140MHz. Lets go fast :-)
165 */
166 movel #0x125a40f0,%d0 /* set for 140MHz */
167 movel %d0,0x180(%a1) /* set PLL register */
168 orl #0x1,%d0
169 movel %d0,0x180(%a1) /* set PLL register */
170#endif
171
172 /*
173 * Setup CS1 for ethernet controller.
174 * (Setup as per M5249C3 doco).
175 */
176 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
177 movel %d0,0x8c(%a0)
178 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
179 movel %d0,0x90(%a0)
180 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
181 movew %d0,0x96(%a0)
182
183 /*
184 * Setup CS2 for IDE interface.
185 */
186 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
187 movel %d0,0x98(%a0)
188 movel #0x001f0001,%d0 /* CS2 size of 1MB */
189 movel %d0,0x9c(%a0)
190 movew #0x0080,%d0 /* CS2 = 16bit, TA */
191 movew %d0,0xa2(%a0)
192
193 movel #0x00107000,%d0 /* IDEconfig1 */
194 movel %d0,0x18c(%a1)
195 movel #0x000c0400,%d0 /* IDEconfig2 */
196 movel %d0,0x190(%a1)
197
198 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
199 orl %d0,0xc(%a1) /* function GPIO19 */
200 orl %d0,0x8(%a1) /* enable GPIO19 as output */
201 orl %d0,0x4(%a1) /* de-assert IDE reset */
202.endm
203
204#define PLATFORM_SETUP m5249c3_setup
205
206#endif /* __ASSEMBLER__ */
207
208/****************************************************************************/
209#endif /* m5249sim_h */
diff --git a/arch/m68knommu/include/asm/m5272sim.h b/arch/m68knommu/include/asm/m5272sim.h
new file mode 100644
index 000000000000..6217edc21139
--- /dev/null
+++ b/arch/m68knommu/include/asm/m5272sim.h
@@ -0,0 +1,78 @@
1/****************************************************************************/
2
3/*
4 * m5272sim.h -- ColdFire 5272 System Integration Module support.
5 *
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef m5272sim_h
12#define m5272sim_h
13/****************************************************************************/
14
15
16/*
17 * Define the 5272 SIM register set addresses.
18 */
19#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
20#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
21#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
22#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
23#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
24
25#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
26#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
27#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
28#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
29
30#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
31#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
32#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
33#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
34
35#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
36#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
37#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
38#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
39
40#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
41#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
42#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
43#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
44#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
45#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
46#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
47#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
48#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
49#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
50#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
51#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
52#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
53#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
54#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
55#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
56
57#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
58#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
59#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
60#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
61#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
62#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
63#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
64#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
65
66#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
67#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
68#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
69#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
70#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
71#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
72#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
73#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
74#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
75
76
77/****************************************************************************/
78#endif /* m5272sim_h */
diff --git a/arch/m68knommu/include/asm/m527xsim.h b/arch/m68knommu/include/asm/m527xsim.h
new file mode 100644
index 000000000000..1f63ab3fb3e6
--- /dev/null
+++ b/arch/m68knommu/include/asm/m527xsim.h
@@ -0,0 +1,74 @@
1/****************************************************************************/
2
3/*
4 * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m527xsim_h
11#define m527xsim_h
12/****************************************************************************/
13
14
15/*
16 * Define the 5270/5271 SIM register set addresses.
17 */
18#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
19#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
20#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
21#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
22#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
23#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
24#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
25#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
26#define MCFINTC_IRLR 0x18 /* */
27#define MCFINTC_IACKL 0x19 /* */
28#define MCFINTC_ICR0 0x40 /* Base ICR register */
29
30#define MCFINT_VECBASE 64 /* Vector base number */
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_UART1 14 /* Interrupt number for UART1 */
33#define MCFINT_UART2 15 /* Interrupt number for UART2 */
34#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
35
36/*
37 * SDRAM configuration registers.
38 */
39#ifdef CONFIG_M5271
40#define MCFSIM_DCR 0x40 /* SDRAM control */
41#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
42#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
43#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
44#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
45#endif
46#ifdef CONFIG_M5275
47#define MCFSIM_DMR 0x40 /* SDRAM mode */
48#define MCFSIM_DCR 0x44 /* SDRAM control */
49#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
50#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
51#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
52#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
53#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
54#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
55#endif
56
57/*
58 * GPIO pins setups to enable the UARTs.
59 */
60#ifdef CONFIG_M5271
61#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
62#define UART0_ENABLE_MASK 0x000f
63#define UART1_ENABLE_MASK 0x0ff0
64#define UART2_ENABLE_MASK 0x3000
65#endif
66#ifdef CONFIG_M5275
67#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
68#define UART0_ENABLE_MASK 0x000f
69#define UART1_ENABLE_MASK 0x00f0
70#define UART2_ENABLE_MASK 0x3f00
71#endif
72
73/****************************************************************************/
74#endif /* m527xsim_h */
diff --git a/arch/m68knommu/include/asm/m528xsim.h b/arch/m68knommu/include/asm/m528xsim.h
new file mode 100644
index 000000000000..28bf783a5d6d
--- /dev/null
+++ b/arch/m68knommu/include/asm/m528xsim.h
@@ -0,0 +1,159 @@
1/****************************************************************************/
2
3/*
4 * m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
5 *
6 * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m528xsim_h
11#define m528xsim_h
12/****************************************************************************/
13
14
15/*
16 * Define the 5280/5282 SIM register set addresses.
17 */
18#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
19#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
20#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
21#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
22#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
23#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
24#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
25#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
26#define MCFINTC_IRLR 0x18 /* */
27#define MCFINTC_IACKL 0x19 /* */
28#define MCFINTC_ICR0 0x40 /* Base ICR register */
29
30#define MCFINT_VECBASE 64 /* Vector base number */
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
33
34/*
35 * SDRAM configuration registers.
36 */
37#define MCFSIM_DCR 0x44 /* SDRAM control */
38#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
39#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
40#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
41#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
42
43/*
44 * Derek Cheung - 6 Feb 2005
45 * add I2C and QSPI register definition using Freescale's MCF5282
46 */
47/* set Port AS pin for I2C or UART */
48#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
49
50/* Port UA Pin Assignment Register (8 Bit) */
51#define MCF5282_GPIO_PUAPAR 0x10005C
52
53/* Interrupt Mask Register Register Low */
54#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
55/* Interrupt Control Register 7 */
56#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
57
58
59
60/*********************************************************************
61*
62* Inter-IC (I2C) Module
63*
64*********************************************************************/
65/* Read/Write access macros for general use */
66#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
67#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
68#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
69#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
70#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
71
72/* Bit level definitions and macros */
73#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
74
75#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
76
77#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
78#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
79#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
80#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
81#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
82#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
83
84#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
85#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
86#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
87#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
88#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
89#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
90#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
91
92
93
94/*********************************************************************
95*
96* Queued Serial Peripheral Interface (QSPI) Module
97*
98*********************************************************************/
99/* Derek - 21 Feb 2005 */
100/* change to the format used in I2C */
101/* Read/Write access macros for general use */
102#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340
103#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344
104#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348
105#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C
106#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350
107#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354
108#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354
109
110/* Bit level definitions and macros */
111#define MCF5282_QSPI_QMR_MSTR (0x8000)
112#define MCF5282_QSPI_QMR_DOHIE (0x4000)
113#define MCF5282_QSPI_QMR_BITS_16 (0x0000)
114#define MCF5282_QSPI_QMR_BITS_8 (0x2000)
115#define MCF5282_QSPI_QMR_BITS_9 (0x2400)
116#define MCF5282_QSPI_QMR_BITS_10 (0x2800)
117#define MCF5282_QSPI_QMR_BITS_11 (0x2C00)
118#define MCF5282_QSPI_QMR_BITS_12 (0x3000)
119#define MCF5282_QSPI_QMR_BITS_13 (0x3400)
120#define MCF5282_QSPI_QMR_BITS_14 (0x3800)
121#define MCF5282_QSPI_QMR_BITS_15 (0x3C00)
122#define MCF5282_QSPI_QMR_CPOL (0x0200)
123#define MCF5282_QSPI_QMR_CPHA (0x0100)
124#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF))
125
126#define MCF5282_QSPI_QDLYR_SPE (0x80)
127#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
128#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
129
130#define MCF5282_QSPI_QWR_HALT (0x8000)
131#define MCF5282_QSPI_QWR_WREN (0x4000)
132#define MCF5282_QSPI_QWR_WRTO (0x2000)
133#define MCF5282_QSPI_QWR_CSIV (0x1000)
134#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
135#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
136#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F))
137
138#define MCF5282_QSPI_QIR_WCEFB (0x8000)
139#define MCF5282_QSPI_QIR_ABRTB (0x4000)
140#define MCF5282_QSPI_QIR_ABRTL (0x1000)
141#define MCF5282_QSPI_QIR_WCEFE (0x0800)
142#define MCF5282_QSPI_QIR_ABRTE (0x0400)
143#define MCF5282_QSPI_QIR_SPIFE (0x0100)
144#define MCF5282_QSPI_QIR_WCEF (0x0008)
145#define MCF5282_QSPI_QIR_ABRT (0x0004)
146#define MCF5282_QSPI_QIR_SPIF (0x0001)
147
148#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F))
149
150#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00))
151#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
152#define MCF5282_QSPI_QCR_CONT (0x8000)
153#define MCF5282_QSPI_QCR_BITSE (0x4000)
154#define MCF5282_QSPI_QCR_DT (0x2000)
155#define MCF5282_QSPI_QCR_DSCK (0x1000)
156#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8)
157
158/****************************************************************************/
159#endif /* m528xsim_h */
diff --git a/arch/m68knommu/include/asm/m5307sim.h b/arch/m68knommu/include/asm/m5307sim.h
new file mode 100644
index 000000000000..5886728409c0
--- /dev/null
+++ b/arch/m68knommu/include/asm/m5307sim.h
@@ -0,0 +1,181 @@
1/****************************************************************************/
2
3/*
4 * m5307sim.h -- ColdFire 5307 System Integration Module support.
5 *
6 * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
7 * (C) Copyright 1999, Lineo (www.lineo.com)
8 *
9 * Modified by David W. Miller for the MCF5307 Eval Board.
10 */
11
12/****************************************************************************/
13#ifndef m5307sim_h
14#define m5307sim_h
15/****************************************************************************/
16
17/*
18 * Define the 5307 SIM register set addresses.
19 */
20#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
21#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
22#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
23#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
24#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
25#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
26#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
27#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
28#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
29#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
30#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
31#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
32#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
33#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
34#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
35#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
36#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
37#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
38#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
39#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
40#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
41#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
42#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
43
44#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
45#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
46#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
47#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
48#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
49#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
50
51#ifdef CONFIG_OLDMASK
52#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */
53#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */
54#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */
55#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
56#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */
57#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
58#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */
59#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
60#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */
61#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
62#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */
63#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
64#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
65#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
66#else
67#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
68#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
69#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
70#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
71#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
72#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
73#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
74#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
75#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
76#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
77#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
78#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
79#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
80#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
81#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
82#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
83#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
84#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
85#endif /* CONFIG_OLDMASK */
86
87#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
88#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
89#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
90#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
91#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
92
93#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */
94#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */
95
96
97/* Definition offset address for CS2-7 -- old mask 5307 */
98
99#define MCF5307_CS2 (0x400000)
100#define MCF5307_CS3 (0x600000)
101#define MCF5307_CS4 (0x800000)
102#define MCF5307_CS5 (0xA00000)
103#define MCF5307_CS6 (0xC00000)
104#define MCF5307_CS7 (0xE00000)
105
106
107/*
108 * Some symbol defines for the above...
109 */
110#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
111#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
112#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
113#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
114#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
115#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
116#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
117#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
118#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
119
120#if defined(CONFIG_M5307)
121#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */
122#endif
123
124/*
125 * Macro to set IMR register. It is 32 bits on the 5307.
126 */
127#define mcf_getimr() \
128 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
129
130#define mcf_setimr(imr) \
131 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
132
133#define mcf_getipr() \
134 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
135
136
137/*
138 * Some symbol defines for the Parallel Port Pin Assignment Register
139 */
140#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
141 /* Clear to select par I/O */
142#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
143 /* Clear to select par I/O */
144
145/*
146 * Defines for the IRQPAR Register
147 */
148#define IRQ5_LEVEL4 0x80
149#define IRQ3_LEVEL6 0x40
150#define IRQ1_LEVEL2 0x20
151
152
153/*
154 * Define the Cache register flags.
155 */
156#define CACR_EC (1<<31)
157#define CACR_ESB (1<<29)
158#define CACR_DPI (1<<28)
159#define CACR_HLCK (1<<27)
160#define CACR_CINVA (1<<24)
161#define CACR_DNFB (1<<10)
162#define CACR_DCM_WTHRU (0<<8)
163#define CACR_DCM_WBACK (1<<8)
164#define CACR_DCM_OFF_PRE (2<<8)
165#define CACR_DCM_OFF_IMP (3<<8)
166#define CACR_DW (1<<5)
167
168#define ACR_BASE_POS 24
169#define ACR_MASK_POS 16
170#define ACR_ENABLE (1<<15)
171#define ACR_USER (0<<13)
172#define ACR_SUPER (1<<13)
173#define ACR_ANY (2<<13)
174#define ACR_CM_WTHRU (0<<5)
175#define ACR_CM_WBACK (1<<5)
176#define ACR_CM_OFF_PRE (2<<5)
177#define ACR_CM_OFF_IMP (3<<5)
178#define ACR_WPROTECT (1<<2)
179
180/****************************************************************************/
181#endif /* m5307sim_h */
diff --git a/arch/m68knommu/include/asm/m532xsim.h b/arch/m68knommu/include/asm/m532xsim.h
new file mode 100644
index 000000000000..1835fd20a82c
--- /dev/null
+++ b/arch/m68knommu/include/asm/m532xsim.h
@@ -0,0 +1,2238 @@
1/****************************************************************************/
2
3/*
4 * m532xsim.h -- ColdFire 5329 registers
5 */
6
7/****************************************************************************/
8#ifndef m532xsim_h
9#define m532xsim_h
10/****************************************************************************/
11
12#define MCF_REG32(x) (*(volatile unsigned long *)(x))
13#define MCF_REG16(x) (*(volatile unsigned short *)(x))
14#define MCF_REG08(x) (*(volatile unsigned char *)(x))
15
16#define MCFINT_VECBASE 64
17#define MCFINT_UART0 26 /* Interrupt number for UART0 */
18#define MCFINT_UART1 27 /* Interrupt number for UART1 */
19
20#define MCF_WTM_WCR MCF_REG16(0xFC098000)
21
22/*
23 * Define the 532x SIM register set addresses.
24 */
25#define MCFSIM_IPRL 0xFC048004
26#define MCFSIM_IPRH 0xFC048000
27#define MCFSIM_IPR MCFSIM_IPRL
28#define MCFSIM_IMRL 0xFC04800C
29#define MCFSIM_IMRH 0xFC048008
30#define MCFSIM_IMR MCFSIM_IMRL
31#define MCFSIM_ICR0 0xFC048040
32#define MCFSIM_ICR1 0xFC048041
33#define MCFSIM_ICR2 0xFC048042
34#define MCFSIM_ICR3 0xFC048043
35#define MCFSIM_ICR4 0xFC048044
36#define MCFSIM_ICR5 0xFC048045
37#define MCFSIM_ICR6 0xFC048046
38#define MCFSIM_ICR7 0xFC048047
39#define MCFSIM_ICR8 0xFC048048
40#define MCFSIM_ICR9 0xFC048049
41#define MCFSIM_ICR10 0xFC04804A
42#define MCFSIM_ICR11 0xFC04804B
43
44/*
45 * Some symbol defines for the above...
46 */
47#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
48#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
49#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
50#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
51#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
52#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
53#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
54#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
55#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
56
57
58#define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */
59
60#define MCFSIM_IMR_SIMR0 0xFC04801C
61#define MCFSIM_IMR_SIMR1 0xFC04C01C
62#define MCFSIM_IMR_CIMR0 0xFC04801D
63#define MCFSIM_IMR_CIMR1 0xFC04C01D
64
65#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
66#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
67
68
69/*
70 * Macro to set IMR register. It is 32 bits on the 5307.
71 */
72#define mcf_getimr() \
73 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
74
75#define mcf_setimr(imr) \
76 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
77
78#define mcf_getipr() \
79 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
80
81#define mcf_getiprl() \
82 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL))
83
84#define mcf_getiprh() \
85 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH))
86
87
88#define mcf_enable_irq0(irq) \
89 *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq);
90
91#define mcf_enable_irq1(irq) \
92 *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq);
93
94#define mcf_disable_irq0(irq) \
95 *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq);
96
97#define mcf_disable_irq1(irq) \
98 *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq);
99
100/*
101 * Define the Cache register flags.
102 */
103#define CACR_EC (1<<31)
104#define CACR_ESB (1<<29)
105#define CACR_DPI (1<<28)
106#define CACR_HLCK (1<<27)
107#define CACR_CINVA (1<<24)
108#define CACR_DNFB (1<<10)
109#define CACR_DCM_WTHRU (0<<8)
110#define CACR_DCM_WBACK (1<<8)
111#define CACR_DCM_OFF_PRE (2<<8)
112#define CACR_DCM_OFF_IMP (3<<8)
113#define CACR_DW (1<<5)
114
115#define ACR_BASE_POS 24
116#define ACR_MASK_POS 16
117#define ACR_ENABLE (1<<15)
118#define ACR_USER (0<<13)
119#define ACR_SUPER (1<<13)
120#define ACR_ANY (2<<13)
121#define ACR_CM_WTHRU (0<<5)
122#define ACR_CM_WBACK (1<<5)
123#define ACR_CM_OFF_PRE (2<<5)
124#define ACR_CM_OFF_IMP (3<<5)
125#define ACR_WPROTECT (1<<2)
126
127/*********************************************************************
128 *
129 * Inter-IC (I2C) Module
130 *
131 *********************************************************************/
132
133/* Read/Write access macros for general use */
134#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
135#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
136#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
137#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
138#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
139
140/* Bit level definitions and macros */
141#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
142
143#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
144
145#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
146#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
147#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
148#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
149#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
150#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
151
152#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
153#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
154#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
155#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
156#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
157#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
158#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
159
160#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
161
162
163/*
164 * The M5329EVB board needs a help getting its devices initialized
165 * at kernel start time if dBUG doesn't set it up (for example
166 * it is not used), so we need to do it manually.
167 */
168#ifdef __ASSEMBLER__
169.macro m5329EVB_setup
170 movel #0xFC098000, %a7
171 movel #0x0, (%a7)
172#define CORE_SRAM 0x80000000
173#define CORE_SRAM_SIZE 0x8000
174 movel #CORE_SRAM, %d0
175 addl #0x221, %d0
176 movec %d0,%RAMBAR1
177 movel #CORE_SRAM, %sp
178 addl #CORE_SRAM_SIZE, %sp
179 jsr sysinit
180.endm
181#define PLATFORM_SETUP m5329EVB_setup
182
183#endif /* __ASSEMBLER__ */
184
185/*********************************************************************
186 *
187 * Chip Configuration Module (CCM)
188 *
189 *********************************************************************/
190
191/* Register read/write macros */
192#define MCF_CCM_CCR MCF_REG16(0xFC0A0004)
193#define MCF_CCM_RCON MCF_REG16(0xFC0A0008)
194#define MCF_CCM_CIR MCF_REG16(0xFC0A000A)
195#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010)
196#define MCF_CCM_CDR MCF_REG16(0xFC0A0012)
197#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014)
198#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016)
199
200/* Bit definitions and macros for MCF_CCM_CCR */
201#define MCF_CCM_CCR_RESERVED (0x0001)
202#define MCF_CCM_CCR_PLL_MODE (0x0003)
203#define MCF_CCM_CCR_OSC_MODE (0x0005)
204#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
205#define MCF_CCM_CCR_LOAD (0x0021)
206#define MCF_CCM_CCR_LIMP (0x0041)
207#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
208
209/* Bit definitions and macros for MCF_CCM_RCON */
210#define MCF_CCM_RCON_RESERVED (0x0001)
211#define MCF_CCM_RCON_PLL_MODE (0x0003)
212#define MCF_CCM_RCON_OSC_MODE (0x0005)
213#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
214#define MCF_CCM_RCON_LOAD (0x0021)
215#define MCF_CCM_RCON_LIMP (0x0041)
216#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
217
218/* Bit definitions and macros for MCF_CCM_CIR */
219#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
220#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
221
222/* Bit definitions and macros for MCF_CCM_MISCCR */
223#define MCF_CCM_MISCCR_USBSRC (0x0001)
224#define MCF_CCM_MISCCR_USBDIV (0x0002)
225#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
226#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
227#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
228#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
229#define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
230#define MCF_CCM_MISCCR_LIMP (0x1000)
231#define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
232
233/* Bit definitions and macros for MCF_CCM_CDR */
234#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
235#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
236
237/* Bit definitions and macros for MCF_CCM_UHCSR */
238#define MCF_CCM_UHCSR_XPDE (0x0001)
239#define MCF_CCM_UHCSR_UHMIE (0x0002)
240#define MCF_CCM_UHCSR_WKUP (0x0004)
241#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
242
243/* Bit definitions and macros for MCF_CCM_UOCSR */
244#define MCF_CCM_UOCSR_XPDE (0x0001)
245#define MCF_CCM_UOCSR_UOMIE (0x0002)
246#define MCF_CCM_UOCSR_WKUP (0x0004)
247#define MCF_CCM_UOCSR_PWRFLT (0x0008)
248#define MCF_CCM_UOCSR_SEND (0x0010)
249#define MCF_CCM_UOCSR_VVLD (0x0020)
250#define MCF_CCM_UOCSR_BVLD (0x0040)
251#define MCF_CCM_UOCSR_AVLD (0x0080)
252#define MCF_CCM_UOCSR_DPPU (0x0100)
253#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
254#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
255#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
256#define MCF_CCM_UOCSR_DMPD (0x1000)
257#define MCF_CCM_UOCSR_DPPD (0x2000)
258#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
259
260/*********************************************************************
261 *
262 * DMA Timers (DTIM)
263 *
264 *********************************************************************/
265
266/* Register read/write macros */
267#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
268#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
269#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
270#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
271#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
272#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
273#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
274#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
275#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
276#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
277#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
278#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
279#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
280#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
281#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
282#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
283#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
284#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
285#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
286#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
287#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
288#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
289#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
290#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
291#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
292#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
293#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
294#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
295#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
296#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
297
298/* Bit definitions and macros for MCF_DTIM_DTMR */
299#define MCF_DTIM_DTMR_RST (0x0001)
300#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
301#define MCF_DTIM_DTMR_FRR (0x0008)
302#define MCF_DTIM_DTMR_ORRI (0x0010)
303#define MCF_DTIM_DTMR_OM (0x0020)
304#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
305#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
306#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
307#define MCF_DTIM_DTMR_CE_FALL (0x0080)
308#define MCF_DTIM_DTMR_CE_RISE (0x0040)
309#define MCF_DTIM_DTMR_CE_NONE (0x0000)
310#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
311#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
312#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
313#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
314
315/* Bit definitions and macros for MCF_DTIM_DTXMR */
316#define MCF_DTIM_DTXMR_MODE16 (0x01)
317#define MCF_DTIM_DTXMR_DMAEN (0x80)
318
319/* Bit definitions and macros for MCF_DTIM_DTER */
320#define MCF_DTIM_DTER_CAP (0x01)
321#define MCF_DTIM_DTER_REF (0x02)
322
323/* Bit definitions and macros for MCF_DTIM_DTRR */
324#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
325
326/* Bit definitions and macros for MCF_DTIM_DTCR */
327#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
328
329/* Bit definitions and macros for MCF_DTIM_DTCN */
330#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
331
332/*********************************************************************
333 *
334 * FlexBus Chip Selects (FBCS)
335 *
336 *********************************************************************/
337
338/* Register read/write macros */
339#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000)
340#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004)
341#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008)
342#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C)
343#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010)
344#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014)
345#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018)
346#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C)
347#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020)
348#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024)
349#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028)
350#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C)
351#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030)
352#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034)
353#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038)
354#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C)
355#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040)
356#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044)
357#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
358#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
359#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
360
361/* Bit definitions and macros for MCF_FBCS_CSAR */
362#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
363
364/* Bit definitions and macros for MCF_FBCS_CSMR */
365#define MCF_FBCS_CSMR_V (0x00000001)
366#define MCF_FBCS_CSMR_WP (0x00000100)
367#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
368#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
369#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
370#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
371#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
372#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
373#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
374#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
375#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
376#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
377#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
378#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
379#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
380#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
381#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
382#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
383#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
384#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
385#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
386#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
387
388/* Bit definitions and macros for MCF_FBCS_CSCR */
389#define MCF_FBCS_CSCR_BSTW (0x00000008)
390#define MCF_FBCS_CSCR_BSTR (0x00000010)
391#define MCF_FBCS_CSCR_BEM (0x00000020)
392#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
393#define MCF_FBCS_CSCR_AA (0x00000100)
394#define MCF_FBCS_CSCR_SBM (0x00000200)
395#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
396#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
397#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
398#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
399#define MCF_FBCS_CSCR_SWSEN (0x00800000)
400#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
401#define MCF_FBCS_CSCR_PS_8 (0x0040)
402#define MCF_FBCS_CSCR_PS_16 (0x0080)
403#define MCF_FBCS_CSCR_PS_32 (0x0000)
404
405/*********************************************************************
406 *
407 * General Purpose I/O (GPIO)
408 *
409 *********************************************************************/
410
411/* Register read/write macros */
412#define MCF_GPIO_PODR_FECH MCF_REG08(0xFC0A4000)
413#define MCF_GPIO_PODR_FECL MCF_REG08(0xFC0A4001)
414#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002)
415#define MCF_GPIO_PODR_BUSCTL MCF_REG08(0xFC0A4003)
416#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004)
417#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005)
418#define MCF_GPIO_PODR_PWM MCF_REG08(0xFC0A4006)
419#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007)
420#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009)
421#define MCF_GPIO_PODR_QSPI MCF_REG08(0xFC0A400A)
422#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B)
423#define MCF_GPIO_PODR_LCDDATAH MCF_REG08(0xFC0A400D)
424#define MCF_GPIO_PODR_LCDDATAM MCF_REG08(0xFC0A400E)
425#define MCF_GPIO_PODR_LCDDATAL MCF_REG08(0xFC0A400F)
426#define MCF_GPIO_PODR_LCDCTLH MCF_REG08(0xFC0A4010)
427#define MCF_GPIO_PODR_LCDCTLL MCF_REG08(0xFC0A4011)
428#define MCF_GPIO_PDDR_FECH MCF_REG08(0xFC0A4014)
429#define MCF_GPIO_PDDR_FECL MCF_REG08(0xFC0A4015)
430#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A4016)
431#define MCF_GPIO_PDDR_BUSCTL MCF_REG08(0xFC0A4017)
432#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A4018)
433#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A4019)
434#define MCF_GPIO_PDDR_PWM MCF_REG08(0xFC0A401A)
435#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401B)
436#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A401C)
437#define MCF_GPIO_PDDR_QSPI MCF_REG08(0xFC0A401E)
438#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A401F)
439#define MCF_GPIO_PDDR_LCDDATAH MCF_REG08(0xFC0A4021)
440#define MCF_GPIO_PDDR_LCDDATAM MCF_REG08(0xFC0A4022)
441#define MCF_GPIO_PDDR_LCDDATAL MCF_REG08(0xFC0A4023)
442#define MCF_GPIO_PDDR_LCDCTLH MCF_REG08(0xFC0A4024)
443#define MCF_GPIO_PDDR_LCDCTLL MCF_REG08(0xFC0A4025)
444#define MCF_GPIO_PPDSDR_FECH MCF_REG08(0xFC0A4028)
445#define MCF_GPIO_PPDSDR_FECL MCF_REG08(0xFC0A4029)
446#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A402A)
447#define MCF_GPIO_PPDSDR_BUSCTL MCF_REG08(0xFC0A402B)
448#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A402C)
449#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A402D)
450#define MCF_GPIO_PPDSDR_PWM MCF_REG08(0xFC0A402E)
451#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A402F)
452#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4031)
453#define MCF_GPIO_PPDSDR_QSPI MCF_REG08(0xFC0A4032)
454#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A4033)
455#define MCF_GPIO_PPDSDR_LCDDATAH MCF_REG08(0xFC0A4035)
456#define MCF_GPIO_PPDSDR_LCDDATAM MCF_REG08(0xFC0A4036)
457#define MCF_GPIO_PPDSDR_LCDDATAL MCF_REG08(0xFC0A4037)
458#define MCF_GPIO_PPDSDR_LCDCTLH MCF_REG08(0xFC0A4038)
459#define MCF_GPIO_PPDSDR_LCDCTLL MCF_REG08(0xFC0A4039)
460#define MCF_GPIO_PCLRR_FECH MCF_REG08(0xFC0A403C)
461#define MCF_GPIO_PCLRR_FECL MCF_REG08(0xFC0A403D)
462#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A403E)
463#define MCF_GPIO_PCLRR_BUSCTL MCF_REG08(0xFC0A403F)
464#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A4040)
465#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A4041)
466#define MCF_GPIO_PCLRR_PWM MCF_REG08(0xFC0A4042)
467#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A4043)
468#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4045)
469#define MCF_GPIO_PCLRR_QSPI MCF_REG08(0xFC0A4046)
470#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4047)
471#define MCF_GPIO_PCLRR_LCDDATAH MCF_REG08(0xFC0A4049)
472#define MCF_GPIO_PCLRR_LCDDATAM MCF_REG08(0xFC0A404A)
473#define MCF_GPIO_PCLRR_LCDDATAL MCF_REG08(0xFC0A404B)
474#define MCF_GPIO_PCLRR_LCDCTLH MCF_REG08(0xFC0A404C)
475#define MCF_GPIO_PCLRR_LCDCTLL MCF_REG08(0xFC0A404D)
476#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050)
477#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051)
478#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052)
479#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053)
480#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054)
481#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055)
482#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056)
483#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058)
484#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A)
485#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C)
486#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D)
487#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E)
488#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060)
489#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064)
490#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065)
491#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068)
492#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069)
493#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A)
494#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B)
495#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C)
496#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D)
497#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E)
498#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F)
499#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070)
500#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071)
501#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072)
502
503/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
504#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
505#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
506#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
507#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
508#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
509#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
510#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
511#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
512
513/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
514#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
515#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
516#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
517#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
518#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
519#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
520#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
521#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
522
523/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
524#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
525#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
526#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
527#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
528#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
529
530/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
531#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
532#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
533#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
534#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
535
536/* Bit definitions and macros for MCF_GPIO_PODR_BE */
537#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
538#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
539#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
540#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
541
542/* Bit definitions and macros for MCF_GPIO_PODR_CS */
543#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
544#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
545#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
546#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
547#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
548
549/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
550#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
551#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
552#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
553#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
554
555/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
556#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
557#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
558#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
559#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
560
561/* Bit definitions and macros for MCF_GPIO_PODR_UART */
562#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
563#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
564#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
565#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
566#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
567#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
568#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
569#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
570
571/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
572#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
573#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
574#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
575#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
576#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
577#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
578
579/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
580#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
581#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
582#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
583#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
584
585/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
586#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
587#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
588
589/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
590#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
591#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
592#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
593#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
594#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
595#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
596#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
597#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
598
599/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
600#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
601#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
602#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
603#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
604#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
605#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
606#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
607#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
608
609/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
610#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
611
612/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
613#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
614#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
615#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
616#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
617#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
618#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
619#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
620#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
621
622/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
623#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
624#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
625#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
626#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
627#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
628#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
629#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
630#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
631
632/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
633#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
634#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
635#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
636#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
637#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
638#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
639#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
640#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
641
642/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
643#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
644#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
645#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
646#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
647#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
648
649/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
650#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
651#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
652#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
653#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
654
655/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
656#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
657#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
658#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
659#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
660
661/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
662#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
663#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
664#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
665#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
666#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
667
668/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
669#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
670#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
671#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
672#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
673
674/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
675#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
676#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
677#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
678#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
679
680/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
681#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
682#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
683#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
684#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
685#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
686#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
687#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
688#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
689
690/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
691#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
692#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
693#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
694#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
695#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
696#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
697
698/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
699#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
700#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
701#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
702#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
703
704/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
705#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
706#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
707
708/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
709#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
710#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
711#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
712#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
713#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
714#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
715#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
716#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
717
718/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
719#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
720#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
721#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
722#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
723#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
724#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
725#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
726#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
727
728/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
729#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
730
731/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
732#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
733#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
734#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
735#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
736#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
737#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
738#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
739#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
740
741/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
742#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
743#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
744#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
745#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
746#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
747#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
748#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
749#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
750
751/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
752#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
753#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
754#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
755#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
756#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
757#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
758#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
759#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
760
761/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
762#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
763#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
764#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
765#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
766#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
767
768/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
769#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
770#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
771#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
772#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
773
774/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
775#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
776#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
777#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
778#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
779
780/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
781#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
782#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
783#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
784#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
785#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
786
787/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
788#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
789#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
790#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
791#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
792
793/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
794#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
795#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
796#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
797#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
798
799/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
800#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
801#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
802#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
803#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
804#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
805#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
806#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
807#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
808
809/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
810#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
811#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
812#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
813#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
814#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
815#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
816
817/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
818#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
819#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
820#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
821#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
822
823/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
824#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
825#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
826
827/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
828#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
829#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
830#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
831#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
832#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
833#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
834#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
835#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
836
837/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
838#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
839#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
840#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
841#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
842#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
843#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
844#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
845#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
846
847/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
848#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
849
850/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
851#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
852#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
853#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
854#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
855#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
856#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
857#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
858#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
859
860/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
861#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
862#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
863#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
864#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
865#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
866#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
867#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
868#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
869
870/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
871#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
872#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
873#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
874#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
875#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
876#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
877#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
878#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
879
880/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
881#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
882#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
883#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
884#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
885#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
886
887/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
888#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
889#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
890#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
891#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
892
893/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
894#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
895#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
896#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
897#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
898
899/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
900#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
901#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
902#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
903#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
904#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
905
906/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
907#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
908#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
909#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
910#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
911
912/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
913#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
914#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
915#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
916#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
917
918/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
919#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
920#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
921#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
922#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
923#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
924#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
925#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
926#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
927
928/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
929#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
930#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
931#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
932#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
933#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
934#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
935
936/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
937#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
938#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
939#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
940#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
941
942/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
943#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
944#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
945
946/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
947#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
948#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
949#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
950#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
951#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
952#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
953#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
954#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
955
956/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
957#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
958#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
959#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
960#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
961#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
962#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
963#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
964#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
965
966/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
967#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
968
969/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
970#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
971#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
972#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
973#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
974#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
975#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
976#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
977#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
978
979/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
980#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
981#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
982#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
983#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
984#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
985#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
986#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
987#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
988
989/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
990#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
991#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
992#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
993#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
994
995/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
996#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
997#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
998#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
999#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
1000#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
1001#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
1002#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
1003#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
1004#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
1005#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
1006#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
1007#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
1008#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
1009
1010/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
1011#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
1012#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
1013#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
1014#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
1015#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
1016#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
1017#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
1018#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
1019#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
1020#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
1021#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
1022#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
1023#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
1024#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
1025#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
1026#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
1027#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
1028#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
1029
1030/* Bit definitions and macros for MCF_GPIO_PAR_BE */
1031#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
1032#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
1033#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
1034#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
1035
1036/* Bit definitions and macros for MCF_GPIO_PAR_CS */
1037#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
1038#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
1039#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
1040#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
1041#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
1042#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
1043#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
1044#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
1045
1046/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
1047#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
1048#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
1049#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
1050#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
1051#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
1052
1053/* Bit definitions and macros for MCF_GPIO_PAR_UART */
1054#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
1055#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
1056#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
1057#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
1058#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
1059#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
1060#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
1061#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
1062#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
1063#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
1064#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
1065#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
1066#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
1067#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
1068#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
1069#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
1070#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
1071#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
1072#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
1073#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
1074#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
1075#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
1076#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
1077#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
1078
1079/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
1080#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
1081#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
1082#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
1083#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
1084#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
1085#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
1086
1087/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
1088#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
1089#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
1090#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
1091#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
1092#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
1093#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
1094#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
1095#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
1096#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
1097#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
1098#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
1099#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
1100#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
1101#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
1102#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
1103#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
1104#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
1105#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
1106#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
1107#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
1108
1109/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
1110#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
1111#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
1112#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
1113#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
1114
1115/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
1116#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
1117#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
1118#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
1119#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
1120#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
1121#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
1122#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
1123#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
1124#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
1125
1126/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
1127#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
1128#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
1129#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
1130#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
1131#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
1132
1133/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
1134#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
1135#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
1136#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
1137
1138/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
1139#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
1140#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
1141#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
1142
1143/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
1144#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
1145
1146/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
1147#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
1148
1149/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
1150#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
1151
1152/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
1153#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
1154#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
1155
1156/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
1157#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
1158
1159/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
1160#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
1161
1162/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
1163#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
1164
1165/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
1166#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
1167
1168/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
1169#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
1170
1171/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
1172#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
1173
1174/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
1175#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
1176
1177/*********************************************************************
1178 *
1179 * Interrupt Controller (INTC)
1180 *
1181 *********************************************************************/
1182
1183/* Register read/write macros */
1184#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
1185#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
1186#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
1187#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
1188#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
1189#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
1190#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
1191#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
1192#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
1193#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
1194#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
1195#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
1196#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
1197#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
1198#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
1199#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
1200#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
1201#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
1202#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
1203#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
1204#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
1205#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
1206#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
1207#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
1208#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
1209#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
1210#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
1211#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
1212#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
1213#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
1214#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
1215#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
1216#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
1217#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
1218#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
1219#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
1220#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
1221#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
1222#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
1223#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
1224#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
1225#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
1226#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
1227#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
1228#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
1229#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
1230#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
1231#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
1232#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
1233#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
1234#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
1235#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
1236#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
1237#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
1238#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
1239#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
1240#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
1241#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
1242#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
1243#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
1244#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
1245#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
1246#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
1247#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
1248#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
1249#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
1250#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
1251#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
1252#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
1253#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
1254#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
1255#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
1256#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
1257#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
1258#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
1259#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
1260#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
1261#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
1262#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
1263#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
1264#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
1265#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
1266#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
1267#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
1268#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
1269#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
1270#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
1271#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
1272#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
1273#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
1274#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
1275#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
1276#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
1277#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
1278#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
1279#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
1280#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
1281#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
1282#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
1283#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
1284#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
1285#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
1286#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
1287#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
1288#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
1289#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
1290#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
1291#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
1292#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
1293#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
1294#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
1295#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
1296#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
1297#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
1298#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
1299#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
1300#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
1301#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
1302#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
1303#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
1304#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
1305#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
1306#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
1307#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
1308#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
1309#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
1310#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
1311#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
1312#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
1313#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
1314#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
1315#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
1316#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
1317#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
1318#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
1319#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
1320#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
1321#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
1322#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
1323#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
1324#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
1325#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
1326#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
1327#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
1328#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
1329#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
1330#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
1331#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
1332#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
1333#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
1334#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
1335#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
1336#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
1337#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
1338#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
1339#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
1340#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
1341#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
1342#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
1343#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
1344#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
1345#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
1346#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
1347#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
1348#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
1349#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
1350#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
1351#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
1352#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
1353#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
1354#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
1355#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
1356#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
1357#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
1358#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
1359#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
1360#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
1361#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
1362#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
1363#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
1364#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
1365#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
1366#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
1367#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
1368#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
1369#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
1370#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
1371#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
1372#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
1373#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
1374#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
1375#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
1376#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
1377#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
1378#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
1379#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
1380#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
1381#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
1382#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
1383#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
1384#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
1385#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
1386#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
1387#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
1388#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
1389#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
1390#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
1391#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
1392#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
1393#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
1394#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
1395#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
1396#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
1397#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
1398#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
1399#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
1400#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
1401#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
1402#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
1403#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
1404#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
1405#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
1406#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
1407#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
1408#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
1409#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
1410#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
1411#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
1412#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
1413#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
1414#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
1415#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
1416#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
1417#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
1418#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
1419#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
1420#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
1421#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
1422#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
1423#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
1424#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
1425#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
1426#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
1427#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
1428#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
1429#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
1430#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
1431#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
1432#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
1433#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
1434#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
1435#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
1436#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
1437
1438/* Bit definitions and macros for MCF_INTC_IPRH */
1439#define MCF_INTC_IPRH_INT32 (0x00000001)
1440#define MCF_INTC_IPRH_INT33 (0x00000002)
1441#define MCF_INTC_IPRH_INT34 (0x00000004)
1442#define MCF_INTC_IPRH_INT35 (0x00000008)
1443#define MCF_INTC_IPRH_INT36 (0x00000010)
1444#define MCF_INTC_IPRH_INT37 (0x00000020)
1445#define MCF_INTC_IPRH_INT38 (0x00000040)
1446#define MCF_INTC_IPRH_INT39 (0x00000080)
1447#define MCF_INTC_IPRH_INT40 (0x00000100)
1448#define MCF_INTC_IPRH_INT41 (0x00000200)
1449#define MCF_INTC_IPRH_INT42 (0x00000400)
1450#define MCF_INTC_IPRH_INT43 (0x00000800)
1451#define MCF_INTC_IPRH_INT44 (0x00001000)
1452#define MCF_INTC_IPRH_INT45 (0x00002000)
1453#define MCF_INTC_IPRH_INT46 (0x00004000)
1454#define MCF_INTC_IPRH_INT47 (0x00008000)
1455#define MCF_INTC_IPRH_INT48 (0x00010000)
1456#define MCF_INTC_IPRH_INT49 (0x00020000)
1457#define MCF_INTC_IPRH_INT50 (0x00040000)
1458#define MCF_INTC_IPRH_INT51 (0x00080000)
1459#define MCF_INTC_IPRH_INT52 (0x00100000)
1460#define MCF_INTC_IPRH_INT53 (0x00200000)
1461#define MCF_INTC_IPRH_INT54 (0x00400000)
1462#define MCF_INTC_IPRH_INT55 (0x00800000)
1463#define MCF_INTC_IPRH_INT56 (0x01000000)
1464#define MCF_INTC_IPRH_INT57 (0x02000000)
1465#define MCF_INTC_IPRH_INT58 (0x04000000)
1466#define MCF_INTC_IPRH_INT59 (0x08000000)
1467#define MCF_INTC_IPRH_INT60 (0x10000000)
1468#define MCF_INTC_IPRH_INT61 (0x20000000)
1469#define MCF_INTC_IPRH_INT62 (0x40000000)
1470#define MCF_INTC_IPRH_INT63 (0x80000000)
1471
1472/* Bit definitions and macros for MCF_INTC_IPRL */
1473#define MCF_INTC_IPRL_INT0 (0x00000001)
1474#define MCF_INTC_IPRL_INT1 (0x00000002)
1475#define MCF_INTC_IPRL_INT2 (0x00000004)
1476#define MCF_INTC_IPRL_INT3 (0x00000008)
1477#define MCF_INTC_IPRL_INT4 (0x00000010)
1478#define MCF_INTC_IPRL_INT5 (0x00000020)
1479#define MCF_INTC_IPRL_INT6 (0x00000040)
1480#define MCF_INTC_IPRL_INT7 (0x00000080)
1481#define MCF_INTC_IPRL_INT8 (0x00000100)
1482#define MCF_INTC_IPRL_INT9 (0x00000200)
1483#define MCF_INTC_IPRL_INT10 (0x00000400)
1484#define MCF_INTC_IPRL_INT11 (0x00000800)
1485#define MCF_INTC_IPRL_INT12 (0x00001000)
1486#define MCF_INTC_IPRL_INT13 (0x00002000)
1487#define MCF_INTC_IPRL_INT14 (0x00004000)
1488#define MCF_INTC_IPRL_INT15 (0x00008000)
1489#define MCF_INTC_IPRL_INT16 (0x00010000)
1490#define MCF_INTC_IPRL_INT17 (0x00020000)
1491#define MCF_INTC_IPRL_INT18 (0x00040000)
1492#define MCF_INTC_IPRL_INT19 (0x00080000)
1493#define MCF_INTC_IPRL_INT20 (0x00100000)
1494#define MCF_INTC_IPRL_INT21 (0x00200000)
1495#define MCF_INTC_IPRL_INT22 (0x00400000)
1496#define MCF_INTC_IPRL_INT23 (0x00800000)
1497#define MCF_INTC_IPRL_INT24 (0x01000000)
1498#define MCF_INTC_IPRL_INT25 (0x02000000)
1499#define MCF_INTC_IPRL_INT26 (0x04000000)
1500#define MCF_INTC_IPRL_INT27 (0x08000000)
1501#define MCF_INTC_IPRL_INT28 (0x10000000)
1502#define MCF_INTC_IPRL_INT29 (0x20000000)
1503#define MCF_INTC_IPRL_INT30 (0x40000000)
1504#define MCF_INTC_IPRL_INT31 (0x80000000)
1505
1506/* Bit definitions and macros for MCF_INTC_IMRH */
1507#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
1508#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
1509#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
1510#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
1511#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
1512#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
1513#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
1514#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
1515#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
1516#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
1517#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
1518#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
1519#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
1520#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
1521#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
1522#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
1523#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
1524#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
1525#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
1526#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
1527#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
1528#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
1529#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
1530#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
1531#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
1532#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
1533#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
1534#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
1535#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
1536#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
1537#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
1538#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
1539
1540/* Bit definitions and macros for MCF_INTC_IMRL */
1541#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
1542#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
1543#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
1544#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
1545#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
1546#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
1547#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
1548#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
1549#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
1550#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
1551#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
1552#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
1553#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
1554#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
1555#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
1556#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
1557#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
1558#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
1559#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
1560#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
1561#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
1562#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
1563#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
1564#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
1565#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
1566#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
1567#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
1568#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
1569#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
1570#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
1571#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
1572#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
1573
1574/* Bit definitions and macros for MCF_INTC_INTFRCH */
1575#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
1576#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
1577#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
1578#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
1579#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
1580#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
1581#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
1582#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
1583#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
1584#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
1585#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
1586#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
1587#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
1588#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
1589#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
1590#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
1591#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
1592#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
1593#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
1594#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
1595#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
1596#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
1597#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
1598#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
1599#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
1600#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
1601#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
1602#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
1603#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
1604#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
1605#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
1606#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
1607
1608/* Bit definitions and macros for MCF_INTC_INTFRCL */
1609#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
1610#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
1611#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
1612#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
1613#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
1614#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
1615#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
1616#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
1617#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
1618#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
1619#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
1620#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
1621#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
1622#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
1623#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
1624#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
1625#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
1626#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
1627#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
1628#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
1629#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
1630#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
1631#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
1632#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
1633#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
1634#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
1635#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
1636#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
1637#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
1638#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
1639#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
1640#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
1641
1642/* Bit definitions and macros for MCF_INTC_ICONFIG */
1643#define MCF_INTC_ICONFIG_EMASK (0x0020)
1644#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
1645#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
1646#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
1647#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
1648#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
1649#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
1650#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
1651
1652/* Bit definitions and macros for MCF_INTC_SIMR */
1653#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
1654
1655/* Bit definitions and macros for MCF_INTC_CIMR */
1656#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
1657
1658/* Bit definitions and macros for MCF_INTC_CLMASK */
1659#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
1660
1661/* Bit definitions and macros for MCF_INTC_SLMASK */
1662#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
1663
1664/* Bit definitions and macros for MCF_INTC_ICR */
1665#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
1666
1667/* Bit definitions and macros for MCF_INTC_SWIACK */
1668#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
1669
1670/* Bit definitions and macros for MCF_INTC_LIACK */
1671#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
1672
1673/********************************************************************/
1674/*********************************************************************
1675*
1676* LCD Controller (LCDC)
1677*
1678*********************************************************************/
1679
1680/* Register read/write macros */
1681#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
1682#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
1683#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
1684#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
1685#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
1686#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
1687#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
1688#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
1689#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
1690#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
1691#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
1692#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
1693#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
1694#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
1695#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
1696#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
1697#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
1698#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
1699#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
1700#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
1701#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
1702#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
1703#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
1704#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
1705#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
1706#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
1707
1708/* Bit definitions and macros for MCF_LCDC_LSSAR */
1709#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
1710
1711/* Bit definitions and macros for MCF_LCDC_LSR */
1712#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
1713#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
1714
1715/* Bit definitions and macros for MCF_LCDC_LVPWR */
1716#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
1717
1718/* Bit definitions and macros for MCF_LCDC_LCPR */
1719#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
1720#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
1721#define MCF_LCDC_LCPR_OP (0x10000000)
1722#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
1723#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
1724#define MCF_LCDC_LCPR_CC_OR (0x40000000)
1725#define MCF_LCDC_LCPR_CC_XOR (0x80000000)
1726#define MCF_LCDC_LCPR_CC_AND (0xC0000000)
1727#define MCF_LCDC_LCPR_OP_ON (0x10000000)
1728#define MCF_LCDC_LCPR_OP_OFF (0x00000000)
1729
1730/* Bit definitions and macros for MCF_LCDC_LCWHBR */
1731#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
1732#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
1733#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
1734#define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
1735#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
1736#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
1737
1738/* Bit definitions and macros for MCF_LCDC_LCCMR */
1739#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
1740#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
1741#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
1742
1743/* Bit definitions and macros for MCF_LCDC_LPCR */
1744#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
1745#define MCF_LCDC_LPCR_SHARP (0x00000040)
1746#define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
1747#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
1748#define MCF_LCDC_LPCR_ACDSEL (0x00008000)
1749#define MCF_LCDC_LPCR_REV_VS (0x00010000)
1750#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
1751#define MCF_LCDC_LPCR_ENDSEL (0x00040000)
1752#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
1753#define MCF_LCDC_LPCR_OEPOL (0x00100000)
1754#define MCF_LCDC_LPCR_CLKPOL (0x00200000)
1755#define MCF_LCDC_LPCR_LPPOL (0x00400000)
1756#define MCF_LCDC_LPCR_FLM (0x00800000)
1757#define MCF_LCDC_LPCR_PIXPOL (0x01000000)
1758#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
1759#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
1760#define MCF_LCDC_LPCR_COLOR (0x40000000)
1761#define MCF_LCDC_LPCR_TFT (0x80000000)
1762#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
1763#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
1764#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
1765#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
1766#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
1767#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
1768#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
1769#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
1770#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
1771#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
1772#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
1773#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
1774#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
1775#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
1776
1777#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
1778
1779/* Bit definitions and macros for MCF_LCDC_LHCR */
1780#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
1781#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
1782#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
1783
1784/* Bit definitions and macros for MCF_LCDC_LVCR */
1785#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
1786#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
1787#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
1788
1789/* Bit definitions and macros for MCF_LCDC_LPOR */
1790#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
1791
1792/* Bit definitions and macros for MCF_LCDC_LPCCR */
1793#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
1794#define MCF_LCDC_LPCCR_CC_EN (0x00000100)
1795#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
1796#define MCF_LCDC_LPCCR_LDMSK (0x00008000)
1797#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
1798#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
1799#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
1800#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
1801
1802/* Bit definitions and macros for MCF_LCDC_LDCR */
1803#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
1804#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
1805#define MCF_LCDC_LDCR_BURST (0x80000000)
1806
1807/* Bit definitions and macros for MCF_LCDC_LRMCR */
1808#define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
1809
1810/* Bit definitions and macros for MCF_LCDC_LICR */
1811#define MCF_LCDC_LICR_INTCON (0x00000001)
1812#define MCF_LCDC_LICR_INTSYN (0x00000004)
1813#define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
1814
1815/* Bit definitions and macros for MCF_LCDC_LIER */
1816#define MCF_LCDC_LIER_BOF_EN (0x00000001)
1817#define MCF_LCDC_LIER_EOF_EN (0x00000002)
1818#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
1819#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
1820#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
1821#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
1822#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
1823#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
1824
1825/* Bit definitions and macros for MCF_LCDC_LISR */
1826#define MCF_LCDC_LISR_BOF (0x00000001)
1827#define MCF_LCDC_LISR_EOF (0x00000002)
1828#define MCF_LCDC_LISR_ERR_RES (0x00000004)
1829#define MCF_LCDC_LISR_UDR_ERR (0x00000008)
1830#define MCF_LCDC_LISR_GW_BOF (0x00000010)
1831#define MCF_LCDC_LISR_GW_EOF (0x00000020)
1832#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
1833#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
1834
1835/* Bit definitions and macros for MCF_LCDC_LGWSAR */
1836#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
1837
1838/* Bit definitions and macros for MCF_LCDC_LGWSR */
1839#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
1840#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
1841
1842/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
1843#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
1844
1845/* Bit definitions and macros for MCF_LCDC_LGWPOR */
1846#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
1847
1848/* Bit definitions and macros for MCF_LCDC_LGWPR */
1849#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
1850#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
1851
1852/* Bit definitions and macros for MCF_LCDC_LGWCR */
1853#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
1854#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
1855#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
1856#define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
1857#define MCF_LCDC_LGWCR_GWE (0x00400000)
1858#define MCF_LCDC_LGWCR_GWCKE (0x00800000)
1859#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
1860
1861/* Bit definitions and macros for MCF_LCDC_LGWDCR */
1862#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
1863#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
1864#define MCF_LCDC_LGWDCR_GWBT (0x80000000)
1865
1866/* Bit definitions and macros for MCF_LCDC_LSCR */
1867#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
1868#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
1869#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
1870#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
1871#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
1872
1873/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
1874#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1875
1876/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
1877#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1878
1879/*********************************************************************
1880 *
1881 * Phase Locked Loop (PLL)
1882 *
1883 *********************************************************************/
1884
1885/* Register read/write macros */
1886#define MCF_PLL_PODR MCF_REG08(0xFC0C0000)
1887#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004)
1888#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008)
1889#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C)
1890
1891/* Bit definitions and macros for MCF_PLL_PODR */
1892#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
1893#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
1894
1895/* Bit definitions and macros for MCF_PLL_PLLCR */
1896#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
1897#define MCF_PLL_PLLCR_DITHEN (0x80)
1898
1899/* Bit definitions and macros for MCF_PLL_PMDR */
1900#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
1901
1902/* Bit definitions and macros for MCF_PLL_PFDR */
1903#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
1904
1905/*********************************************************************
1906 *
1907 * System Control Module Registers (SCM)
1908 *
1909 *********************************************************************/
1910
1911/* Register read/write macros */
1912#define MCF_SCM_MPR MCF_REG32(0xFC000000)
1913#define MCF_SCM_PACRA MCF_REG32(0xFC000020)
1914#define MCF_SCM_PACRB MCF_REG32(0xFC000024)
1915#define MCF_SCM_PACRC MCF_REG32(0xFC000028)
1916#define MCF_SCM_PACRD MCF_REG32(0xFC00002C)
1917#define MCF_SCM_PACRE MCF_REG32(0xFC000040)
1918#define MCF_SCM_PACRF MCF_REG32(0xFC000044)
1919
1920#define MCF_SCM_BCR MCF_REG32(0xFC040024)
1921
1922/*********************************************************************
1923 *
1924 * SDRAM Controller (SDRAMC)
1925 *
1926 *********************************************************************/
1927
1928/* Register read/write macros */
1929#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000)
1930#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004)
1931#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008)
1932#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C)
1933#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080)
1934#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100)
1935#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110)
1936#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114)
1937#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118)
1938#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C)
1939#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004))
1940
1941/* Bit definitions and macros for MCF_SDRAMC_SDMR */
1942#define MCF_SDRAMC_SDMR_CMD (0x00010000)
1943#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
1944#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
1945#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
1946#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
1947
1948/* Bit definitions and macros for MCF_SDRAMC_SDCR */
1949#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
1950#define MCF_SDRAMC_SDCR_IREF (0x00000004)
1951#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
1952#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
1953#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
1954#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
1955#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
1956#define MCF_SDRAMC_SDCR_REF (0x10000000)
1957#define MCF_SDRAMC_SDCR_DDR (0x20000000)
1958#define MCF_SDRAMC_SDCR_CKE (0x40000000)
1959#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
1960#define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
1961#define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
1962
1963/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
1964#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
1965#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
1966#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
1967#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
1968#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
1969#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
1970#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
1971
1972/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
1973#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
1974#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
1975#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
1976#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
1977
1978/* Device Errata - LIMP mode work around */
1979#define MCF_SDRAMC_REFRESH (0x40000000)
1980
1981/* Bit definitions and macros for MCF_SDRAMC_SDDS */
1982#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
1983#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
1984#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
1985#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
1986#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
1987
1988/* Bit definitions and macros for MCF_SDRAMC_SDCS */
1989#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
1990#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
1991#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
1992#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
1993#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
1994#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
1995#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
1996#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
1997#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
1998#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
1999#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
2000#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
2001#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
2002#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
2003#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
2004#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
2005#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
2006
2007/*********************************************************************
2008 *
2009 * FlexCAN module registers
2010 *
2011 *********************************************************************/
2012#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
2013#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
2014#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
2015#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
2016#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
2017#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
2018#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
2019#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
2020#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
2021#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
2022#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
2023
2024#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
2025#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
2026#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
2027
2028/*
2029 * FlexCAN Module Configuration Register
2030 */
2031#define CANMCR_MDIS (0x80000000)
2032#define CANMCR_FRZ (0x40000000)
2033#define CANMCR_HALT (0x10000000)
2034#define CANMCR_SOFTRST (0x02000000)
2035#define CANMCR_FRZACK (0x01000000)
2036#define CANMCR_SUPV (0x00800000)
2037#define CANMCR_MAXMB(x) ((x)&0x0F)
2038
2039/*
2040 * FlexCAN Control Register
2041 */
2042#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
2043#define CANCTRL_RJW(x) (((x)&0x03)<<22)
2044#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
2045#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
2046#define CANCTRL_BOFFMSK (0x00008000)
2047#define CANCTRL_ERRMSK (0x00004000)
2048#define CANCTRL_CLKSRC (0x00002000)
2049#define CANCTRL_LPB (0x00001000)
2050#define CANCTRL_SAMP (0x00000080)
2051#define CANCTRL_BOFFREC (0x00000040)
2052#define CANCTRL_TSYNC (0x00000020)
2053#define CANCTRL_LBUF (0x00000010)
2054#define CANCTRL_LOM (0x00000008)
2055#define CANCTRL_PROPSEG(x) ((x)&0x07)
2056
2057/*
2058 * FlexCAN Error Counter Register
2059 */
2060#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
2061#define ERRCNT_TXECTR(x) ((x)&0xFF)
2062
2063/*
2064 * FlexCAN Error and Status Register
2065 */
2066#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
2067#define ERRSTAT_ACKERR (0x00002000)
2068#define ERRSTAT_CRCERR (0x00001000)
2069#define ERRSTAT_FRMERR (0x00000800)
2070#define ERRSTAT_STFERR (0x00000400)
2071#define ERRSTAT_TXWRN (0x00000200)
2072#define ERRSTAT_RXWRN (0x00000100)
2073#define ERRSTAT_IDLE (0x00000080)
2074#define ERRSTAT_TXRX (0x00000040)
2075#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
2076#define ERRSTAT_BOFFINT (0x00000004)
2077#define ERRSTAT_ERRINT (0x00000002)
2078
2079/*
2080 * Interrupt Mask Register
2081 */
2082#define IMASK_BUF15M (0x8000)
2083#define IMASK_BUF14M (0x4000)
2084#define IMASK_BUF13M (0x2000)
2085#define IMASK_BUF12M (0x1000)
2086#define IMASK_BUF11M (0x0800)
2087#define IMASK_BUF10M (0x0400)
2088#define IMASK_BUF9M (0x0200)
2089#define IMASK_BUF8M (0x0100)
2090#define IMASK_BUF7M (0x0080)
2091#define IMASK_BUF6M (0x0040)
2092#define IMASK_BUF5M (0x0020)
2093#define IMASK_BUF4M (0x0010)
2094#define IMASK_BUF3M (0x0008)
2095#define IMASK_BUF2M (0x0004)
2096#define IMASK_BUF1M (0x0002)
2097#define IMASK_BUF0M (0x0001)
2098#define IMASK_BUFnM(x) (0x1<<(x))
2099#define IMASK_BUFF_ENABLE_ALL (0x1111)
2100#define IMASK_BUFF_DISABLE_ALL (0x0000)
2101
2102/*
2103 * Interrupt Flag Register
2104 */
2105#define IFLAG_BUF15M (0x8000)
2106#define IFLAG_BUF14M (0x4000)
2107#define IFLAG_BUF13M (0x2000)
2108#define IFLAG_BUF12M (0x1000)
2109#define IFLAG_BUF11M (0x0800)
2110#define IFLAG_BUF10M (0x0400)
2111#define IFLAG_BUF9M (0x0200)
2112#define IFLAG_BUF8M (0x0100)
2113#define IFLAG_BUF7M (0x0080)
2114#define IFLAG_BUF6M (0x0040)
2115#define IFLAG_BUF5M (0x0020)
2116#define IFLAG_BUF4M (0x0010)
2117#define IFLAG_BUF3M (0x0008)
2118#define IFLAG_BUF2M (0x0004)
2119#define IFLAG_BUF1M (0x0002)
2120#define IFLAG_BUF0M (0x0001)
2121#define IFLAG_BUFF_SET_ALL (0xFFFF)
2122#define IFLAG_BUFF_CLEAR_ALL (0x0000)
2123#define IFLAG_BUFnM(x) (0x1<<(x))
2124
2125/*
2126 * Message Buffers
2127 */
2128#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
2129#define MB_CNT_SRR (0x00400000)
2130#define MB_CNT_IDE (0x00200000)
2131#define MB_CNT_RTR (0x00100000)
2132#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
2133#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
2134#define MB_ID_STD(x) (((x)&0x07FF)<<18)
2135#define MB_ID_EXT(x) ((x)&0x3FFFF)
2136
2137/*********************************************************************
2138 *
2139 * Edge Port Module (EPORT)
2140 *
2141 *********************************************************************/
2142
2143/* Register read/write macros */
2144#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000)
2145#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002)
2146#define MCF_EPORT_EPIER MCF_REG08(0xFC094003)
2147#define MCF_EPORT_EPDR MCF_REG08(0xFC094004)
2148#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005)
2149#define MCF_EPORT_EPFR MCF_REG08(0xFC094006)
2150
2151/* Bit definitions and macros for MCF_EPORT_EPPAR */
2152#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2153#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2154#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2155#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2156#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2157#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2158#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2159#define MCF_EPORT_EPPAR_LEVEL (0)
2160#define MCF_EPORT_EPPAR_RISING (1)
2161#define MCF_EPORT_EPPAR_FALLING (2)
2162#define MCF_EPORT_EPPAR_BOTH (3)
2163#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2164#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2165#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2166#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2167#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2168#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2169#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2170#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2171#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2172#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2173#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2174#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2175#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2176#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2177#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2178#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2179#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2180#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2181#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2182#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2183#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2184#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2185#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2186#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2187#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2188#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2189#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2190#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2191
2192/* Bit definitions and macros for MCF_EPORT_EPDDR */
2193#define MCF_EPORT_EPDDR_EPDD1 (0x02)
2194#define MCF_EPORT_EPDDR_EPDD2 (0x04)
2195#define MCF_EPORT_EPDDR_EPDD3 (0x08)
2196#define MCF_EPORT_EPDDR_EPDD4 (0x10)
2197#define MCF_EPORT_EPDDR_EPDD5 (0x20)
2198#define MCF_EPORT_EPDDR_EPDD6 (0x40)
2199#define MCF_EPORT_EPDDR_EPDD7 (0x80)
2200
2201/* Bit definitions and macros for MCF_EPORT_EPIER */
2202#define MCF_EPORT_EPIER_EPIE1 (0x02)
2203#define MCF_EPORT_EPIER_EPIE2 (0x04)
2204#define MCF_EPORT_EPIER_EPIE3 (0x08)
2205#define MCF_EPORT_EPIER_EPIE4 (0x10)
2206#define MCF_EPORT_EPIER_EPIE5 (0x20)
2207#define MCF_EPORT_EPIER_EPIE6 (0x40)
2208#define MCF_EPORT_EPIER_EPIE7 (0x80)
2209
2210/* Bit definitions and macros for MCF_EPORT_EPDR */
2211#define MCF_EPORT_EPDR_EPD1 (0x02)
2212#define MCF_EPORT_EPDR_EPD2 (0x04)
2213#define MCF_EPORT_EPDR_EPD3 (0x08)
2214#define MCF_EPORT_EPDR_EPD4 (0x10)
2215#define MCF_EPORT_EPDR_EPD5 (0x20)
2216#define MCF_EPORT_EPDR_EPD6 (0x40)
2217#define MCF_EPORT_EPDR_EPD7 (0x80)
2218
2219/* Bit definitions and macros for MCF_EPORT_EPPDR */
2220#define MCF_EPORT_EPPDR_EPPD1 (0x02)
2221#define MCF_EPORT_EPPDR_EPPD2 (0x04)
2222#define MCF_EPORT_EPPDR_EPPD3 (0x08)
2223#define MCF_EPORT_EPPDR_EPPD4 (0x10)
2224#define MCF_EPORT_EPPDR_EPPD5 (0x20)
2225#define MCF_EPORT_EPPDR_EPPD6 (0x40)
2226#define MCF_EPORT_EPPDR_EPPD7 (0x80)
2227
2228/* Bit definitions and macros for MCF_EPORT_EPFR */
2229#define MCF_EPORT_EPFR_EPF1 (0x02)
2230#define MCF_EPORT_EPFR_EPF2 (0x04)
2231#define MCF_EPORT_EPFR_EPF3 (0x08)
2232#define MCF_EPORT_EPFR_EPF4 (0x10)
2233#define MCF_EPORT_EPFR_EPF5 (0x20)
2234#define MCF_EPORT_EPFR_EPF6 (0x40)
2235#define MCF_EPORT_EPFR_EPF7 (0x80)
2236
2237/********************************************************************/
2238#endif /* m532xsim_h */
diff --git a/arch/m68knommu/include/asm/m5407sim.h b/arch/m68knommu/include/asm/m5407sim.h
new file mode 100644
index 000000000000..cc22c4a53005
--- /dev/null
+++ b/arch/m68knommu/include/asm/m5407sim.h
@@ -0,0 +1,157 @@
1/****************************************************************************/
2
3/*
4 * m5407sim.h -- ColdFire 5407 System Integration Module support.
5 *
6 * (C) Copyright 2000, Lineo (www.lineo.com)
7 * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
8 *
9 * Modified by David W. Miller for the MCF5307 Eval Board.
10 */
11
12/****************************************************************************/
13#ifndef m5407sim_h
14#define m5407sim_h
15/****************************************************************************/
16
17/*
18 * Define the 5407 SIM register set addresses.
19 */
20#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
21#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
22#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
23#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
24#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
25#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
26#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
27#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
28#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
29#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
30#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
31#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
32#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
33#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
34#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
35#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
36#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
37#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
38#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
39#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
40#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
41#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
42#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
43
44#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
45#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
46#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
47#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
48#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
49#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
50
51#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
52#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
53#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
54#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
55#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
56#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
57#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
58#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
59#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
60#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
61#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
62#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
63#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
64#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
65#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
66#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
67#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
68#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
69
70#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
71#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
72#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
73#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
74#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
75
76#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */
77#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */
78
79
80/*
81 * Some symbol defines for the above...
82 */
83#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
84#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
85#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
86#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
87#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
88#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
89#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
90#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
91#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
92
93/*
94 * Macro to set IMR register. It is 32 bits on the 5407.
95 */
96#define mcf_getimr() \
97 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
98
99#define mcf_setimr(imr) \
100 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
101
102#define mcf_getipr() \
103 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
104
105
106/*
107 * Some symbol defines for the Parallel Port Pin Assignment Register
108 */
109#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
110 /* Clear to select par I/O */
111#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
112 /* Clear to select par I/O */
113
114/*
115 * Defines for the IRQPAR Register
116 */
117#define IRQ5_LEVEL4 0x80
118#define IRQ3_LEVEL6 0x40
119#define IRQ1_LEVEL2 0x20
120
121
122/*
123 * Define the Cache register flags.
124 */
125#define CACR_DEC 0x80000000 /* Enable data cache */
126#define CACR_DWP 0x40000000 /* Data write protection */
127#define CACR_DESB 0x20000000 /* Enable data store buffer */
128#define CACR_DDPI 0x10000000 /* Disable CPUSHL */
129#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
130#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
131#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
132#define CACR_DDCM_P 0x04000000 /* No cache, precise */
133#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
134#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
135#define CACR_BEC 0x00080000 /* Enable branch cache */
136#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
137#define CACR_IEC 0x00008000 /* Enable instruction cache */
138#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
139#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
140#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
141#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
142#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
143
144#define ACR_BASE_POS 24 /* Address Base */
145#define ACR_MASK_POS 16 /* Address Mask */
146#define ACR_ENABLE 0x00008000 /* Enable address */
147#define ACR_USER 0x00000000 /* User mode access only */
148#define ACR_SUPER 0x00002000 /* Supervisor mode only */
149#define ACR_ANY 0x00004000 /* Match any access mode */
150#define ACR_CM_WT 0x00000000 /* Write through mode */
151#define ACR_CM_CP 0x00000020 /* Copyback mode */
152#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
153#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
154#define ACR_WPROTECT 0x00000004 /* Write protect */
155
156/****************************************************************************/
157#endif /* m5407sim_h */
diff --git a/arch/m68knommu/include/asm/m68360.h b/arch/m68knommu/include/asm/m68360.h
new file mode 100644
index 000000000000..eb7d39ef2855
--- /dev/null
+++ b/arch/m68knommu/include/asm/m68360.h
@@ -0,0 +1,13 @@
1#include "m68360_regs.h"
2#include "m68360_pram.h"
3#include "m68360_quicc.h"
4#include "m68360_enet.h"
5
6#ifdef CONFIG_M68360
7
8#define CPM_INTERRUPT 4
9
10/* see MC68360 User's Manual, p. 7-377 */
11#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */
12
13#endif /* CONFIG_M68360 */
diff --git a/arch/m68knommu/include/asm/m68360_enet.h b/arch/m68knommu/include/asm/m68360_enet.h
new file mode 100644
index 000000000000..c36f4d059203
--- /dev/null
+++ b/arch/m68knommu/include/asm/m68360_enet.h
@@ -0,0 +1,177 @@
1/***********************************
2 * $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions for the ETHERNET controllers
7 ***************************************
8 */
9
10#ifndef __ETHER_H
11#define __ETHER_H
12
13#include "quicc_simple.h"
14
15/*
16 * transmit BD's
17 */
18#define T_R 0x8000 /* ready bit */
19#define E_T_PAD 0x4000 /* short frame padding */
20#define T_W 0x2000 /* wrap bit */
21#define T_I 0x1000 /* interrupt on completion */
22#define T_L 0x0800 /* last in frame */
23#define T_TC 0x0400 /* transmit CRC (when last) */
24
25#define T_DEF 0x0200 /* defer indication */
26#define T_HB 0x0100 /* heartbeat */
27#define T_LC 0x0080 /* error: late collision */
28#define T_RL 0x0040 /* error: retransmission limit */
29#define T_RC 0x003c /* retry count */
30#define T_UN 0x0002 /* error: underrun */
31#define T_CSL 0x0001 /* carier sense lost */
32#define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL)
33
34/*
35 * receive BD's
36 */
37#define R_E 0x8000 /* buffer empty */
38#define R_W 0x2000 /* wrap bit */
39#define R_I 0x1000 /* interrupt on reception */
40#define R_L 0x0800 /* last BD in frame */
41#define R_F 0x0400 /* first BD in frame */
42#define R_M 0x0100 /* received because of promisc. mode */
43
44#define R_LG 0x0020 /* frame too long */
45#define R_NO 0x0010 /* non-octet aligned */
46#define R_SH 0x0008 /* short frame */
47#define R_CR 0x0004 /* receive CRC error */
48#define R_OV 0x0002 /* receive overrun */
49#define R_CL 0x0001 /* collision */
50#define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL)
51
52
53/*
54 * ethernet interrupts
55 */
56#define ETHERNET_GRA 0x0080 /* graceful stop complete */
57#define ETHERNET_TXE 0x0010 /* transmit error */
58#define ETHERNET_RXF 0x0008 /* receive frame */
59#define ETHERNET_BSY 0x0004 /* busy condition */
60#define ETHERNET_TXB 0x0002 /* transmit buffer */
61#define ETHERNET_RXB 0x0001 /* receive buffer */
62
63/*
64 * ethernet protocol specific mode register (PSMR)
65 */
66#define ETHER_HBC 0x8000 /* heartbeat checking */
67#define ETHER_FC 0x4000 /* force collision */
68#define ETHER_RSH 0x2000 /* receive short frames */
69#define ETHER_IAM 0x1000 /* individual address mode */
70#define ETHER_CRC_32 (0x2<<10) /* Enable CRC */
71#define ETHER_PRO 0x0200 /* promiscuous */
72#define ETHER_BRO 0x0100 /* broadcast address */
73#define ETHER_SBT 0x0080 /* stop backoff timer */
74#define ETHER_LPB 0x0040 /* Loop Back Mode */
75#define ETHER_SIP 0x0020 /* sample input pins */
76#define ETHER_LCW 0x0010 /* late collision window */
77#define ETHER_NIB_13 (0x0<<1) /* # of ignored bits 13 */
78#define ETHER_NIB_14 (0x1<<1) /* # of ignored bits 14 */
79#define ETHER_NIB_15 (0x2<<1) /* # of ignored bits 15 */
80#define ETHER_NIB_16 (0x3<<1) /* # of ignored bits 16 */
81#define ETHER_NIB_21 (0x4<<1) /* # of ignored bits 21 */
82#define ETHER_NIB_22 (0x5<<1) /* # of ignored bits 22 */
83#define ETHER_NIB_23 (0x6<<1) /* # of ignored bits 23 */
84#define ETHER_NIB_24 (0x7<<1) /* # of ignored bits 24 */
85
86/*
87 * ethernet specific parameters
88 */
89#define CRC_WORD 4 /* Length in bytes of CRC */
90#define C_PRES 0xffffffff /* preform 32 bit CRC */
91#define C_MASK 0xdebb20e3 /* comply with 32 bit CRC */
92#define CRCEC 0x00000000
93#define ALEC 0x00000000
94#define DISFC 0x00000000
95#define PADS 0x00000000
96#define RET_LIM 0x000f /* retry 15 times to send a frame before interrupt */
97#define ETH_MFLR 0x05ee /* 1518 max frame size */
98#define MINFLR 0x0040 /* Minimum frame size 64 */
99#define MAXD1 0x05ee /* Max dma count 1518 */
100#define MAXD2 0x05ee
101#define GADDR1 0x00000000 /* Clear group address */
102#define GADDR2 0x00000000
103#define GADDR3 0x00000000
104#define GADDR4 0x00000000
105#define P_PER 0x00000000 /*not used */
106#define IADDR1 0x00000000 /* Individual hash table not used */
107#define IADDR2 0x00000000
108#define IADDR3 0x00000000
109#define IADDR4 0x00000000
110#define TADDR_H 0x00000000 /* clear this regs */
111#define TADDR_M 0x00000000
112#define TADDR_L 0x00000000
113
114/* SCC Parameter Ram */
115#define RFCR 0x18 /* normal operation */
116#define TFCR 0x18 /* normal operation */
117#define E_MRBLR 1518 /* Max ethernet frame length */
118
119/*
120 * ethernet specific structure
121 */
122typedef union {
123 unsigned char b[6];
124 struct {
125 unsigned short high;
126 unsigned short middl;
127 unsigned short low;
128 } w;
129} ETHER_ADDR;
130
131typedef struct {
132 int max_frame_length;
133 int promisc_mode;
134 int reject_broadcast;
135 ETHER_ADDR phys_adr;
136} ETHER_SPECIFIC;
137
138typedef struct {
139 ETHER_ADDR dst_addr;
140 ETHER_ADDR src_addr;
141 unsigned short type_or_len;
142 unsigned char data[1];
143} ETHER_FRAME;
144
145#define MAX_DATALEN 1500
146typedef struct {
147 ETHER_ADDR dst_addr;
148 ETHER_ADDR src_addr;
149 unsigned short type_or_len;
150 unsigned char data[MAX_DATALEN];
151 unsigned char fcs[CRC_WORD];
152} ETHER_MAX_FRAME;
153
154
155/*
156 * Internal ethernet function prototypes
157 */
158void ether_interrupt(int scc_num);
159/* mleslie: debug */
160/* static void ethernet_rx_internal(int scc_num); */
161/* static void ethernet_tx_internal(int scc_num); */
162
163/*
164 * User callable routines prototypes (ethernet specific)
165 */
166void ethernet_init(int scc_number,
167 alloc_routine *alloc_buffer,
168 free_routine *free_buffer,
169 store_rx_buffer_routine *store_rx_buffer,
170 handle_tx_error_routine *handle_tx_error,
171 handle_rx_error_routine *handle_rx_error,
172 handle_lost_error_routine *handle_lost_error,
173 ETHER_SPECIFIC *ether_spec);
174int ethernet_tx(int scc_number, void *buf, int length);
175
176#endif
177
diff --git a/arch/m68knommu/include/asm/m68360_pram.h b/arch/m68knommu/include/asm/m68360_pram.h
new file mode 100644
index 000000000000..e6088bbce93d
--- /dev/null
+++ b/arch/m68knommu/include/asm/m68360_pram.h
@@ -0,0 +1,431 @@
1/***********************************
2 * $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions of the parameter area RAM.
7 * Note that different structures are overlaid
8 * at the same offsets for the different modes
9 * of operation.
10 ***************************************
11 */
12
13#ifndef __PRAM_H
14#define __PRAM_H
15
16/* Time slot assignment table */
17#define VALID_SLOT 0x8000
18#define WRAP_SLOT 0x4000
19
20/*****************************************************************
21 Global Multichannel parameter RAM
22*****************************************************************/
23struct global_multi_pram {
24 /*
25 * Global Multichannel parameter RAM
26 */
27 unsigned long mcbase; /* Multichannel Base pointer */
28 unsigned short qmcstate; /* Multichannel Controller state */
29 unsigned short mrblr; /* Maximum Receive Buffer Length */
30 unsigned short tx_s_ptr; /* TSTATx Pointer */
31 unsigned short rxptr; /* Current Time slot entry in TSATRx */
32 unsigned short grfthr; /* Global Receive frame threshold */
33 unsigned short grfcnt; /* Global Receive Frame Count */
34 unsigned long intbase; /* Multichannel Base address */
35 unsigned long iintptr; /* Pointer to interrupt queue */
36 unsigned short rx_s_ptr; /* TSTARx Pointer */
37
38 unsigned short txptr; /* Current Time slot entry in TSATTx */
39 unsigned long c_mask32; /* CRC Constant (debb20e3) */
40 unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */
41 unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */
42 unsigned short c_mask16; /* CRC Constant (f0b8) */
43};
44
45/*****************************************************************
46 Quicc32 HDLC parameter RAM
47*****************************************************************/
48struct quicc32_pram {
49
50 unsigned short tbase; /* Tx Buffer Descriptors Base Address */
51 unsigned short chamr; /* Channel Mode Register */
52 unsigned long tstate; /* Tx Internal State */
53 unsigned long txintr; /* Tx Internal Data Pointer */
54 unsigned short tbptr; /* Tx Buffer Descriptor Pointer */
55 unsigned short txcntr; /* Tx Internal Byte Count */
56 unsigned long tupack; /* (Tx Temp) */
57 unsigned long zistate; /* Zero Insertion machine state */
58 unsigned long tcrc; /* Temp Transmit CRC */
59 unsigned short intmask; /* Channel's interrupt mask flags */
60 unsigned short bdflags;
61 unsigned short rbase; /* Rx Buffer Descriptors Base Address */
62 unsigned short mflr; /* Max Frame Length Register */
63 unsigned long rstate; /* Rx Internal State */
64 unsigned long rxintr; /* Rx Internal Data Pointer */
65 unsigned short rbptr; /* Rx Buffer Descriptor Pointer */
66 unsigned short rxbyc; /* Rx Internal Byte Count */
67 unsigned long rpack; /* (Rx Temp) */
68 unsigned long zdstate; /* Zero Deletion machine state */
69 unsigned long rcrc; /* Temp Transmit CRC */
70 unsigned short maxc; /* Max_length counter */
71 unsigned short tmp_mb; /* Temp */
72};
73
74
75/*****************************************************************
76 HDLC parameter RAM
77*****************************************************************/
78
79struct hdlc_pram {
80 /*
81 * SCC parameter RAM
82 */
83 unsigned short rbase; /* RX BD base address */
84 unsigned short tbase; /* TX BD base address */
85 unsigned char rfcr; /* Rx function code */
86 unsigned char tfcr; /* Tx function code */
87 unsigned short mrblr; /* Rx buffer length */
88 unsigned long rstate; /* Rx internal state */
89 unsigned long rptr; /* Rx internal data pointer */
90 unsigned short rbptr; /* rb BD Pointer */
91 unsigned short rcount; /* Rx internal byte count */
92 unsigned long rtemp; /* Rx temp */
93 unsigned long tstate; /* Tx internal state */
94 unsigned long tptr; /* Tx internal data pointer */
95 unsigned short tbptr; /* Tx BD pointer */
96 unsigned short tcount; /* Tx byte count */
97 unsigned long ttemp; /* Tx temp */
98 unsigned long rcrc; /* temp receive CRC */
99 unsigned long tcrc; /* temp transmit CRC */
100
101 /*
102 * HDLC specific parameter RAM
103 */
104 unsigned char RESERVED1[4]; /* Reserved area */
105 unsigned long c_mask; /* CRC constant */
106 unsigned long c_pres; /* CRC preset */
107 unsigned short disfc; /* discarded frame counter */
108 unsigned short crcec; /* CRC error counter */
109 unsigned short abtsc; /* abort sequence counter */
110 unsigned short nmarc; /* nonmatching address rx cnt */
111 unsigned short retrc; /* frame retransmission cnt */
112 unsigned short mflr; /* maximum frame length reg */
113 unsigned short max_cnt; /* maximum length counter */
114 unsigned short rfthr; /* received frames threshold */
115 unsigned short rfcnt; /* received frames count */
116 unsigned short hmask; /* user defined frm addr mask */
117 unsigned short haddr1; /* user defined frm address 1 */
118 unsigned short haddr2; /* user defined frm address 2 */
119 unsigned short haddr3; /* user defined frm address 3 */
120 unsigned short haddr4; /* user defined frm address 4 */
121 unsigned short tmp; /* temp */
122 unsigned short tmp_mb; /* temp */
123};
124
125
126
127/*****************************************************************
128 UART parameter RAM
129*****************************************************************/
130
131/*
132 * bits in uart control characters table
133 */
134#define CC_INVALID 0x8000 /* control character is valid */
135#define CC_REJ 0x4000 /* don't store char in buffer */
136#define CC_CHAR 0x00ff /* control character */
137
138/* UART */
139struct uart_pram {
140 /*
141 * SCC parameter RAM
142 */
143 unsigned short rbase; /* RX BD base address */
144 unsigned short tbase; /* TX BD base address */
145 unsigned char rfcr; /* Rx function code */
146 unsigned char tfcr; /* Tx function code */
147 unsigned short mrblr; /* Rx buffer length */
148 unsigned long rstate; /* Rx internal state */
149 unsigned long rptr; /* Rx internal data pointer */
150 unsigned short rbptr; /* rb BD Pointer */
151 unsigned short rcount; /* Rx internal byte count */
152 unsigned long rx_temp; /* Rx temp */
153 unsigned long tstate; /* Tx internal state */
154 unsigned long tptr; /* Tx internal data pointer */
155 unsigned short tbptr; /* Tx BD pointer */
156 unsigned short tcount; /* Tx byte count */
157 unsigned long ttemp; /* Tx temp */
158 unsigned long rcrc; /* temp receive CRC */
159 unsigned long tcrc; /* temp transmit CRC */
160
161 /*
162 * UART specific parameter RAM
163 */
164 unsigned char RESERVED1[8]; /* Reserved area */
165 unsigned short max_idl; /* maximum idle characters */
166 unsigned short idlc; /* rx idle counter (internal) */
167 unsigned short brkcr; /* break count register */
168
169 unsigned short parec; /* Rx parity error counter */
170 unsigned short frmer; /* Rx framing error counter */
171 unsigned short nosec; /* Rx noise counter */
172 unsigned short brkec; /* Rx break character counter */
173 unsigned short brkln; /* Reaceive break length */
174
175 unsigned short uaddr1; /* address character 1 */
176 unsigned short uaddr2; /* address character 2 */
177 unsigned short rtemp; /* temp storage */
178 unsigned short toseq; /* Tx out of sequence char */
179 unsigned short cc[8]; /* Rx control characters */
180 unsigned short rccm; /* Rx control char mask */
181 unsigned short rccr; /* Rx control char register */
182 unsigned short rlbc; /* Receive last break char */
183};
184
185
186
187/*****************************************************************
188 BISYNC parameter RAM
189*****************************************************************/
190
191struct bisync_pram {
192 /*
193 * SCC parameter RAM
194 */
195 unsigned short rbase; /* RX BD base address */
196 unsigned short tbase; /* TX BD base address */
197 unsigned char rfcr; /* Rx function code */
198 unsigned char tfcr; /* Tx function code */
199 unsigned short mrblr; /* Rx buffer length */
200 unsigned long rstate; /* Rx internal state */
201 unsigned long rptr; /* Rx internal data pointer */
202 unsigned short rbptr; /* rb BD Pointer */
203 unsigned short rcount; /* Rx internal byte count */
204 unsigned long rtemp; /* Rx temp */
205 unsigned long tstate; /* Tx internal state */
206 unsigned long tptr; /* Tx internal data pointer */
207 unsigned short tbptr; /* Tx BD pointer */
208 unsigned short tcount; /* Tx byte count */
209 unsigned long ttemp; /* Tx temp */
210 unsigned long rcrc; /* temp receive CRC */
211 unsigned long tcrc; /* temp transmit CRC */
212
213 /*
214 * BISYNC specific parameter RAM
215 */
216 unsigned char RESERVED1[4]; /* Reserved area */
217 unsigned long crcc; /* CRC Constant Temp Value */
218 unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
219 unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
220 unsigned short parec; /* Receive Parity Error Counter */
221 unsigned short bsync; /* BISYNC SYNC Character */
222 unsigned short bdle; /* BISYNC DLE Character */
223 unsigned short cc[8]; /* Rx control characters */
224 unsigned short rccm; /* Receive Control Character Mask */
225};
226
227/*****************************************************************
228 IOM2 parameter RAM
229 (overlaid on tx bd[5] of SCC channel[2])
230*****************************************************************/
231struct iom2_pram {
232 unsigned short ci_data; /* ci data */
233 unsigned short monitor_data; /* monitor data */
234 unsigned short tstate; /* transmitter state */
235 unsigned short rstate; /* receiver state */
236};
237
238/*****************************************************************
239 SPI/SMC parameter RAM
240 (overlaid on tx bd[6,7] of SCC channel[2])
241*****************************************************************/
242
243#define SPI_R 0x8000 /* Ready bit in BD */
244
245struct spi_pram {
246 unsigned short rbase; /* Rx BD Base Address */
247 unsigned short tbase; /* Tx BD Base Address */
248 unsigned char rfcr; /* Rx function code */
249 unsigned char tfcr; /* Tx function code */
250 unsigned short mrblr; /* Rx buffer length */
251 unsigned long rstate; /* Rx internal state */
252 unsigned long rptr; /* Rx internal data pointer */
253 unsigned short rbptr; /* rb BD Pointer */
254 unsigned short rcount; /* Rx internal byte count */
255 unsigned long rtemp; /* Rx temp */
256 unsigned long tstate; /* Tx internal state */
257 unsigned long tptr; /* Tx internal data pointer */
258 unsigned short tbptr; /* Tx BD pointer */
259 unsigned short tcount; /* Tx byte count */
260 unsigned long ttemp; /* Tx temp */
261};
262
263struct smc_uart_pram {
264 unsigned short rbase; /* Rx BD Base Address */
265 unsigned short tbase; /* Tx BD Base Address */
266 unsigned char rfcr; /* Rx function code */
267 unsigned char tfcr; /* Tx function code */
268 unsigned short mrblr; /* Rx buffer length */
269 unsigned long rstate; /* Rx internal state */
270 unsigned long rptr; /* Rx internal data pointer */
271 unsigned short rbptr; /* rb BD Pointer */
272 unsigned short rcount; /* Rx internal byte count */
273 unsigned long rtemp; /* Rx temp */
274 unsigned long tstate; /* Tx internal state */
275 unsigned long tptr; /* Tx internal data pointer */
276 unsigned short tbptr; /* Tx BD pointer */
277 unsigned short tcount; /* Tx byte count */
278 unsigned long ttemp; /* Tx temp */
279 unsigned short max_idl; /* Maximum IDLE Characters */
280 unsigned short idlc; /* Temporary IDLE Counter */
281 unsigned short brkln; /* Last Rx Break Length */
282 unsigned short brkec; /* Rx Break Condition Counter */
283 unsigned short brkcr; /* Break Count Register (Tx) */
284 unsigned short r_mask; /* Temporary bit mask */
285};
286
287struct smc_trnsp_pram {
288 unsigned short rbase; /* rx BD Base Address */
289 unsigned short tbase; /* Tx BD Base Address */
290 unsigned char rfcr; /* Rx function code */
291 unsigned char tfcr; /* Tx function code */
292 unsigned short mrblr; /* Rx buffer length */
293 unsigned long rstate; /* Rx internal state */
294 unsigned long rptr; /* Rx internal data pointer */
295 unsigned short rbptr; /* rb BD Pointer */
296 unsigned short rcount; /* Rx internal byte count */
297 unsigned long rtemp; /* Rx temp */
298 unsigned long tstate; /* Tx internal state */
299 unsigned long tptr; /* Tx internal data pointer */
300 unsigned short tbptr; /* Tx BD pointer */
301 unsigned short tcount; /* Tx byte count */
302 unsigned long ttemp; /* Tx temp */
303 unsigned short reserved[5]; /* Reserved */
304};
305
306struct idma_pram {
307 unsigned short ibase; /* IDMA BD Base Address */
308 unsigned short ibptr; /* IDMA buffer descriptor pointer */
309 unsigned long istate; /* IDMA internal state */
310 unsigned long itemp; /* IDMA temp */
311};
312
313struct ethernet_pram {
314 /*
315 * SCC parameter RAM
316 */
317 unsigned short rbase; /* RX BD base address */
318 unsigned short tbase; /* TX BD base address */
319 unsigned char rfcr; /* Rx function code */
320 unsigned char tfcr; /* Tx function code */
321 unsigned short mrblr; /* Rx buffer length */
322 unsigned long rstate; /* Rx internal state */
323 unsigned long rptr; /* Rx internal data pointer */
324 unsigned short rbptr; /* rb BD Pointer */
325 unsigned short rcount; /* Rx internal byte count */
326 unsigned long rtemp; /* Rx temp */
327 unsigned long tstate; /* Tx internal state */
328 unsigned long tptr; /* Tx internal data pointer */
329 unsigned short tbptr; /* Tx BD pointer */
330 unsigned short tcount; /* Tx byte count */
331 unsigned long ttemp; /* Tx temp */
332 unsigned long rcrc; /* temp receive CRC */
333 unsigned long tcrc; /* temp transmit CRC */
334
335 /*
336 * ETHERNET specific parameter RAM
337 */
338 unsigned long c_pres; /* preset CRC */
339 unsigned long c_mask; /* constant mask for CRC */
340 unsigned long crcec; /* CRC error counter */
341 unsigned long alec; /* alighnment error counter */
342 unsigned long disfc; /* discard frame counter */
343 unsigned short pads; /* short frame PAD characters */
344 unsigned short ret_lim; /* retry limit threshold */
345 unsigned short ret_cnt; /* retry limit counter */
346 unsigned short mflr; /* maximum frame length reg */
347 unsigned short minflr; /* minimum frame length reg */
348 unsigned short maxd1; /* maximum DMA1 length reg */
349 unsigned short maxd2; /* maximum DMA2 length reg */
350 unsigned short maxd; /* rx max DMA */
351 unsigned short dma_cnt; /* rx dma counter */
352 unsigned short max_b; /* max bd byte count */
353 unsigned short gaddr1; /* group address filter 1 */
354 unsigned short gaddr2; /* group address filter 2 */
355 unsigned short gaddr3; /* group address filter 3 */
356 unsigned short gaddr4; /* group address filter 4 */
357 unsigned long tbuf0_data0; /* save area 0 - current frm */
358 unsigned long tbuf0_data1; /* save area 1 - current frm */
359 unsigned long tbuf0_rba0;
360 unsigned long tbuf0_crc;
361 unsigned short tbuf0_bcnt;
362 union {
363 unsigned char b[6];
364 struct {
365 unsigned short high;
366 unsigned short middl;
367 unsigned short low;
368 } w;
369 } paddr;
370 unsigned short p_per; /* persistence */
371 unsigned short rfbd_ptr; /* rx first bd pointer */
372 unsigned short tfbd_ptr; /* tx first bd pointer */
373 unsigned short tlbd_ptr; /* tx last bd pointer */
374 unsigned long tbuf1_data0; /* save area 0 - next frame */
375 unsigned long tbuf1_data1; /* save area 1 - next frame */
376 unsigned long tbuf1_rba0;
377 unsigned long tbuf1_crc;
378 unsigned short tbuf1_bcnt;
379 unsigned short tx_len; /* tx frame length counter */
380 unsigned short iaddr1; /* individual address filter 1*/
381 unsigned short iaddr2; /* individual address filter 2*/
382 unsigned short iaddr3; /* individual address filter 3*/
383 unsigned short iaddr4; /* individual address filter 4*/
384 unsigned short boff_cnt; /* back-off counter */
385 unsigned short taddr_h; /* temp address (MSB) */
386 unsigned short taddr_m; /* temp address */
387 unsigned short taddr_l; /* temp address (LSB) */
388};
389
390struct transparent_pram {
391 /*
392 * SCC parameter RAM
393 */
394 unsigned short rbase; /* RX BD base address */
395 unsigned short tbase; /* TX BD base address */
396 unsigned char rfcr; /* Rx function code */
397 unsigned char tfcr; /* Tx function code */
398 unsigned short mrblr; /* Rx buffer length */
399 unsigned long rstate; /* Rx internal state */
400 unsigned long rptr; /* Rx internal data pointer */
401 unsigned short rbptr; /* rb BD Pointer */
402 unsigned short rcount; /* Rx internal byte count */
403 unsigned long rtemp; /* Rx temp */
404 unsigned long tstate; /* Tx internal state */
405 unsigned long tptr; /* Tx internal data pointer */
406 unsigned short tbptr; /* Tx BD pointer */
407 unsigned short tcount; /* Tx byte count */
408 unsigned long ttemp; /* Tx temp */
409 unsigned long rcrc; /* temp receive CRC */
410 unsigned long tcrc; /* temp transmit CRC */
411
412 /*
413 * TRANSPARENT specific parameter RAM
414 */
415 unsigned long crc_p; /* CRC Preset */
416 unsigned long crc_c; /* CRC constant */
417};
418
419struct timer_pram {
420 /*
421 * RISC timers parameter RAM
422 */
423 unsigned short tm_base; /* RISC timer table base adr */
424 unsigned short tm_ptr; /* RISC timer table pointer */
425 unsigned short r_tmr; /* RISC timer mode register */
426 unsigned short r_tmv; /* RISC timer valid register */
427 unsigned long tm_cmd; /* RISC timer cmd register */
428 unsigned long tm_cnt; /* RISC timer internal cnt */
429};
430
431#endif
diff --git a/arch/m68knommu/include/asm/m68360_quicc.h b/arch/m68knommu/include/asm/m68360_quicc.h
new file mode 100644
index 000000000000..6d40f4d18e10
--- /dev/null
+++ b/arch/m68knommu/include/asm/m68360_quicc.h
@@ -0,0 +1,362 @@
1/***********************************
2 * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions of QUICC memory structures
7 ***************************************
8 */
9
10#ifndef __M68360_QUICC_H
11#define __M68360_QUICC_H
12
13/*
14 * include registers and
15 * parameter ram definitions files
16 */
17#include <asm/m68360_regs.h>
18#include <asm/m68360_pram.h>
19
20
21
22/* Buffer Descriptors */
23typedef struct quicc_bd {
24 volatile unsigned short status;
25 volatile unsigned short length;
26 volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */
27} QUICC_BD;
28
29
30#ifdef MOTOROLA_ORIGINAL
31struct user_data {
32 /* BASE + 0x000: user data memory */
33 volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
34 volatile unsigned char udata_bd[0x200]; /*user data Ucode */
35 volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */
36 volatile unsigned char RESERVED1[0x500]; /* Reserved area */
37};
38#else
39struct user_data {
40 /* BASE + 0x000: user data memory */
41 volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/
42 volatile unsigned char udata_bd1[0x200]; /* user, bds */
43 volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */
44 volatile unsigned char udata_bd2[0x100]; /* user, bds */
45 volatile unsigned char RESERVED1[0x400]; /* Reserved area */
46};
47#endif
48
49
50/*
51 * internal ram
52 */
53typedef struct quicc {
54 union {
55 struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */
56 struct user_data u;
57 }ch_or_u; /* multipul or user space */
58
59 /* BASE + 0xc00: PARAMETER RAM */
60 union {
61 struct scc_pram {
62 union {
63 struct hdlc_pram h;
64 struct uart_pram u;
65 struct bisync_pram b;
66 struct transparent_pram t;
67 unsigned char RESERVED66[0x70];
68 } pscc; /* scc parameter area (protocol dependent) */
69 union {
70 struct {
71 unsigned char RESERVED70[0x10];
72 struct spi_pram spi;
73 unsigned char RESERVED72[0x8];
74 struct timer_pram timer;
75 } timer_spi;
76 struct {
77 struct idma_pram idma;
78 unsigned char RESERVED67[0x4];
79 union {
80 struct smc_uart_pram u;
81 struct smc_trnsp_pram t;
82 } psmc;
83 } idma_smc;
84 } pothers;
85 } scc;
86 struct ethernet_pram enet_scc;
87 struct global_multi_pram m;
88 unsigned char pr[0x100];
89 } pram[4];
90
91 /* reserved */
92
93 /* BASE + 0x1000: INTERNAL REGISTERS */
94 /* SIM */
95 volatile unsigned long sim_mcr; /* module configuration reg */
96 volatile unsigned short sim_simtr; /* module test register */
97 volatile unsigned char RESERVED2[0x2]; /* Reserved area */
98 volatile unsigned char sim_avr; /* auto vector reg */
99 volatile unsigned char sim_rsr; /* reset status reg */
100 volatile unsigned char RESERVED3[0x2]; /* Reserved area */
101 volatile unsigned char sim_clkocr; /* CLCO control register */
102 volatile unsigned char RESERVED62[0x3]; /* Reserved area */
103 volatile unsigned short sim_pllcr; /* PLL control register */
104 volatile unsigned char RESERVED63[0x2]; /* Reserved area */
105 volatile unsigned short sim_cdvcr; /* Clock devider control register */
106 volatile unsigned short sim_pepar; /* Port E pin assignment register */
107 volatile unsigned char RESERVED64[0xa]; /* Reserved area */
108 volatile unsigned char sim_sypcr; /* system protection control*/
109 volatile unsigned char sim_swiv; /* software interrupt vector*/
110 volatile unsigned char RESERVED6[0x2]; /* Reserved area */
111 volatile unsigned short sim_picr; /* periodic interrupt control reg */
112 volatile unsigned char RESERVED7[0x2]; /* Reserved area */
113 volatile unsigned short sim_pitr; /* periodic interrupt timing reg */
114 volatile unsigned char RESERVED8[0x3]; /* Reserved area */
115 volatile unsigned char sim_swsr; /* software service */
116 volatile unsigned long sim_bkar; /* breakpoint address register*/
117 volatile unsigned long sim_bkcr; /* breakpoint control register*/
118 volatile unsigned char RESERVED10[0x8]; /* Reserved area */
119 /* MEMC */
120 volatile unsigned long memc_gmr; /* Global memory register */
121 volatile unsigned short memc_mstat; /* MEMC status register */
122 volatile unsigned char RESERVED11[0xa]; /* Reserved area */
123 volatile unsigned long memc_br0; /* base register 0 */
124 volatile unsigned long memc_or0; /* option register 0 */
125 volatile unsigned char RESERVED12[0x8]; /* Reserved area */
126 volatile unsigned long memc_br1; /* base register 1 */
127 volatile unsigned long memc_or1; /* option register 1 */
128 volatile unsigned char RESERVED13[0x8]; /* Reserved area */
129 volatile unsigned long memc_br2; /* base register 2 */
130 volatile unsigned long memc_or2; /* option register 2 */
131 volatile unsigned char RESERVED14[0x8]; /* Reserved area */
132 volatile unsigned long memc_br3; /* base register 3 */
133 volatile unsigned long memc_or3; /* option register 3 */
134 volatile unsigned char RESERVED15[0x8]; /* Reserved area */
135 volatile unsigned long memc_br4; /* base register 3 */
136 volatile unsigned long memc_or4; /* option register 3 */
137 volatile unsigned char RESERVED16[0x8]; /* Reserved area */
138 volatile unsigned long memc_br5; /* base register 3 */
139 volatile unsigned long memc_or5; /* option register 3 */
140 volatile unsigned char RESERVED17[0x8]; /* Reserved area */
141 volatile unsigned long memc_br6; /* base register 3 */
142 volatile unsigned long memc_or6; /* option register 3 */
143 volatile unsigned char RESERVED18[0x8]; /* Reserved area */
144 volatile unsigned long memc_br7; /* base register 3 */
145 volatile unsigned long memc_or7; /* option register 3 */
146 volatile unsigned char RESERVED9[0x28]; /* Reserved area */
147 /* TEST */
148 volatile unsigned short test_tstmra; /* master shift a */
149 volatile unsigned short test_tstmrb; /* master shift b */
150 volatile unsigned short test_tstsc; /* shift count */
151 volatile unsigned short test_tstrc; /* repetition counter */
152 volatile unsigned short test_creg; /* control */
153 volatile unsigned short test_dreg; /* destributed register */
154 volatile unsigned char RESERVED58[0x404]; /* Reserved area */
155 /* IDMA1 */
156 volatile unsigned short idma_iccr; /* channel configuration reg*/
157 volatile unsigned char RESERVED19[0x2]; /* Reserved area */
158 volatile unsigned short idma1_cmr; /* dma mode reg */
159 volatile unsigned char RESERVED68[0x2]; /* Reserved area */
160 volatile unsigned long idma1_sapr; /* dma source addr ptr */
161 volatile unsigned long idma1_dapr; /* dma destination addr ptr */
162 volatile unsigned long idma1_bcr; /* dma byte count reg */
163 volatile unsigned char idma1_fcr; /* function code reg */
164 volatile unsigned char RESERVED20; /* Reserved area */
165 volatile unsigned char idma1_cmar; /* channel mask reg */
166 volatile unsigned char RESERVED21; /* Reserved area */
167 volatile unsigned char idma1_csr; /* channel status reg */
168 volatile unsigned char RESERVED22[0x3]; /* Reserved area */
169 /* SDMA */
170 volatile unsigned char sdma_sdsr; /* status reg */
171 volatile unsigned char RESERVED23; /* Reserved area */
172 volatile unsigned short sdma_sdcr; /* configuration reg */
173 volatile unsigned long sdma_sdar; /* address reg */
174 /* IDMA2 */
175 volatile unsigned char RESERVED69[0x2]; /* Reserved area */
176 volatile unsigned short idma2_cmr; /* dma mode reg */
177 volatile unsigned long idma2_sapr; /* dma source addr ptr */
178 volatile unsigned long idma2_dapr; /* dma destination addr ptr */
179 volatile unsigned long idma2_bcr; /* dma byte count reg */
180 volatile unsigned char idma2_fcr; /* function code reg */
181 volatile unsigned char RESERVED24; /* Reserved area */
182 volatile unsigned char idma2_cmar; /* channel mask reg */
183 volatile unsigned char RESERVED25; /* Reserved area */
184 volatile unsigned char idma2_csr; /* channel status reg */
185 volatile unsigned char RESERVED26[0x7]; /* Reserved area */
186 /* Interrupt Controller */
187 volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
188 volatile unsigned long intr_cipr; /* CP interrupt pending reg */
189 volatile unsigned long intr_cimr; /* CP interrupt mask reg */
190 volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
191 /* Parallel I/O */
192 volatile unsigned short pio_padir; /* port A data direction reg */
193 volatile unsigned short pio_papar; /* port A pin assignment reg */
194 volatile unsigned short pio_paodr; /* port A open drain reg */
195 volatile unsigned short pio_padat; /* port A data register */
196 volatile unsigned char RESERVED28[0x8]; /* Reserved area */
197 volatile unsigned short pio_pcdir; /* port C data direction reg*/
198 volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
199 volatile unsigned short pio_pcso; /* port C special options */
200 volatile unsigned short pio_pcdat; /* port C data register */
201 volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
202 volatile unsigned char RESERVED29[0x16]; /* Reserved area */
203 /* Timer */
204 volatile unsigned short timer_tgcr; /* timer global configuration reg */
205 volatile unsigned char RESERVED30[0xe]; /* Reserved area */
206 volatile unsigned short timer_tmr1; /* timer 1 mode reg */
207 volatile unsigned short timer_tmr2; /* timer 2 mode reg */
208 volatile unsigned short timer_trr1; /* timer 1 referance reg */
209 volatile unsigned short timer_trr2; /* timer 2 referance reg */
210 volatile unsigned short timer_tcr1; /* timer 1 capture reg */
211 volatile unsigned short timer_tcr2; /* timer 2 capture reg */
212 volatile unsigned short timer_tcn1; /* timer 1 counter reg */
213 volatile unsigned short timer_tcn2; /* timer 2 counter reg */
214 volatile unsigned short timer_tmr3; /* timer 3 mode reg */
215 volatile unsigned short timer_tmr4; /* timer 4 mode reg */
216 volatile unsigned short timer_trr3; /* timer 3 referance reg */
217 volatile unsigned short timer_trr4; /* timer 4 referance reg */
218 volatile unsigned short timer_tcr3; /* timer 3 capture reg */
219 volatile unsigned short timer_tcr4; /* timer 4 capture reg */
220 volatile unsigned short timer_tcn3; /* timer 3 counter reg */
221 volatile unsigned short timer_tcn4; /* timer 4 counter reg */
222 volatile unsigned short timer_ter1; /* timer 1 event reg */
223 volatile unsigned short timer_ter2; /* timer 2 event reg */
224 volatile unsigned short timer_ter3; /* timer 3 event reg */
225 volatile unsigned short timer_ter4; /* timer 4 event reg */
226 volatile unsigned char RESERVED34[0x8]; /* Reserved area */
227 /* CP */
228 volatile unsigned short cp_cr; /* command register */
229 volatile unsigned char RESERVED35[0x2]; /* Reserved area */
230 volatile unsigned short cp_rccr; /* main configuration reg */
231 volatile unsigned char RESERVED37; /* Reserved area */
232 volatile unsigned char cp_rmds; /* development support status reg */
233 volatile unsigned long cp_rmdr; /* development support control reg */
234 volatile unsigned short cp_rctr1; /* ram break register 1 */
235 volatile unsigned short cp_rctr2; /* ram break register 2 */
236 volatile unsigned short cp_rctr3; /* ram break register 3 */
237 volatile unsigned short cp_rctr4; /* ram break register 4 */
238 volatile unsigned char RESERVED59[0x2]; /* Reserved area */
239 volatile unsigned short cp_rter; /* RISC timers event reg */
240 volatile unsigned char RESERVED38[0x2]; /* Reserved area */
241 volatile unsigned short cp_rtmr; /* RISC timers mask reg */
242 volatile unsigned char RESERVED39[0x14]; /* Reserved area */
243 /* BRG */
244 union {
245 volatile unsigned long l;
246 struct {
247 volatile unsigned short BRGC_RESERV:14;
248 volatile unsigned short rst:1;
249 volatile unsigned short en:1;
250 volatile unsigned short extc:2;
251 volatile unsigned short atb:1;
252 volatile unsigned short cd:12;
253 volatile unsigned short div16:1;
254 } b;
255 } brgc[4]; /* BRG1-BRG4 configuration regs*/
256 /* SCC registers */
257 struct scc_regs {
258 union {
259 struct {
260 /* Low word. */
261 volatile unsigned short GSMR_RESERV2:1;
262 volatile unsigned short edge:2;
263 volatile unsigned short tci:1;
264 volatile unsigned short tsnc:2;
265 volatile unsigned short rinv:1;
266 volatile unsigned short tinv:1;
267 volatile unsigned short tpl:3;
268 volatile unsigned short tpp:2;
269 volatile unsigned short tend:1;
270 volatile unsigned short tdcr:2;
271 volatile unsigned short rdcr:2;
272 volatile unsigned short renc:3;
273 volatile unsigned short tenc:3;
274 volatile unsigned short diag:2;
275 volatile unsigned short enr:1;
276 volatile unsigned short ent:1;
277 volatile unsigned short mode:4;
278 /* High word. */
279 volatile unsigned short GSMR_RESERV1:14;
280 volatile unsigned short pri:1;
281 volatile unsigned short gde:1;
282 volatile unsigned short tcrc:2;
283 volatile unsigned short revd:1;
284 volatile unsigned short trx:1;
285 volatile unsigned short ttx:1;
286 volatile unsigned short cdp:1;
287 volatile unsigned short ctsp:1;
288 volatile unsigned short cds:1;
289 volatile unsigned short ctss:1;
290 volatile unsigned short tfl:1;
291 volatile unsigned short rfw:1;
292 volatile unsigned short txsy:1;
293 volatile unsigned short synl:2;
294 volatile unsigned short rtsm:1;
295 volatile unsigned short rsyn:1;
296 } b;
297 struct {
298 volatile unsigned long low;
299 volatile unsigned long high;
300 } w;
301 } scc_gsmr; /* SCC general mode reg */
302 volatile unsigned short scc_psmr; /* protocol specific mode reg */
303 volatile unsigned char RESERVED42[0x2]; /* Reserved area */
304 volatile unsigned short scc_todr; /* SCC transmit on demand */
305 volatile unsigned short scc_dsr; /* SCC data sync reg */
306 volatile unsigned short scc_scce; /* SCC event reg */
307 volatile unsigned char RESERVED43[0x2];/* Reserved area */
308 volatile unsigned short scc_sccm; /* SCC mask reg */
309 volatile unsigned char RESERVED44[0x1];/* Reserved area */
310 volatile unsigned char scc_sccs; /* SCC status reg */
311 volatile unsigned char RESERVED45[0x8]; /* Reserved area */
312 } scc_regs[4];
313 /* SMC */
314 struct smc_regs {
315 volatile unsigned char RESERVED46[0x2]; /* Reserved area */
316 volatile unsigned short smc_smcmr; /* SMC mode reg */
317 volatile unsigned char RESERVED60[0x2]; /* Reserved area */
318 volatile unsigned char smc_smce; /* SMC event reg */
319 volatile unsigned char RESERVED47[0x3]; /* Reserved area */
320 volatile unsigned char smc_smcm; /* SMC mask reg */
321 volatile unsigned char RESERVED48[0x5]; /* Reserved area */
322 } smc_regs[2];
323 /* SPI */
324 volatile unsigned short spi_spmode; /* SPI mode reg */
325 volatile unsigned char RESERVED51[0x4]; /* Reserved area */
326 volatile unsigned char spi_spie; /* SPI event reg */
327 volatile unsigned char RESERVED52[0x3]; /* Reserved area */
328 volatile unsigned char spi_spim; /* SPI mask reg */
329 volatile unsigned char RESERVED53[0x2]; /* Reserved area */
330 volatile unsigned char spi_spcom; /* SPI command reg */
331 volatile unsigned char RESERVED54[0x4]; /* Reserved area */
332 /* PIP */
333 volatile unsigned short pip_pipc; /* pip configuration reg */
334 volatile unsigned char RESERVED65[0x2]; /* Reserved area */
335 volatile unsigned short pip_ptpr; /* pip timing parameters reg */
336 volatile unsigned long pip_pbdir; /* port b data direction reg */
337 volatile unsigned long pip_pbpar; /* port b pin assignment reg */
338 volatile unsigned long pip_pbodr; /* port b open drain reg */
339 volatile unsigned long pip_pbdat; /* port b data reg */
340 volatile unsigned char RESERVED71[0x18]; /* Reserved area */
341 /* Serial Interface */
342 volatile unsigned long si_simode; /* SI mode register */
343 volatile unsigned char si_sigmr; /* SI global mode register */
344 volatile unsigned char RESERVED55; /* Reserved area */
345 volatile unsigned char si_sistr; /* SI status register */
346 volatile unsigned char si_sicmr; /* SI command register */
347 volatile unsigned char RESERVED56[0x4]; /* Reserved area */
348 volatile unsigned long si_sicr; /* SI clock routing */
349 volatile unsigned long si_sirp; /* SI ram pointers */
350 volatile unsigned char RESERVED57[0xc]; /* Reserved area */
351 volatile unsigned short si_siram[0x80]; /* SI routing ram */
352} QUICC;
353
354#endif
355
356/*
357 * Local variables:
358 * c-indent-level: 4
359 * c-basic-offset: 4
360 * tab-width: 4
361 * End:
362 */
diff --git a/arch/m68knommu/include/asm/m68360_regs.h b/arch/m68knommu/include/asm/m68360_regs.h
new file mode 100644
index 000000000000..d57217ca4f27
--- /dev/null
+++ b/arch/m68knommu/include/asm/m68360_regs.h
@@ -0,0 +1,408 @@
1/***********************************
2 * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions of the QUICC registers
7 ***************************************
8 */
9
10#ifndef __REGISTERS_H
11#define __REGISTERS_H
12
13#define CLEAR_BIT(x, bit) x =bit
14
15/*****************************************************************
16 Command Register
17*****************************************************************/
18
19/* bit fields within command register */
20#define SOFTWARE_RESET 0x8000
21#define CMD_OPCODE 0x0f00
22#define CMD_CHANNEL 0x00f0
23#define CMD_FLAG 0x0001
24
25/* general command opcodes */
26#define INIT_RXTX_PARAMS 0x0000
27#define INIT_RX_PARAMS 0x0100
28#define INIT_TX_PARAMS 0x0200
29#define ENTER_HUNT_MODE 0x0300
30#define STOP_TX 0x0400
31#define GR_STOP_TX 0x0500
32#define RESTART_TX 0x0600
33#define CLOSE_RX_BD 0x0700
34#define SET_ENET_GROUP 0x0800
35#define RESET_ENET_GROUP 0x0900
36
37/* quicc32 CP commands */
38#define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */
39#define ENTER_HUNT_MODE_32 0x1e00
40
41/* quicc32 mask/event SCC register */
42#define GOV 0x01
43#define GUN 0x02
44#define GINT 0x04
45#define IQOV 0x08
46
47
48/* Timer commands */
49#define SET_TIMER 0x0800
50
51/* Multi channel Interrupt structure */
52#define INTR_VALID 0x8000 /* Valid interrupt entry */
53#define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */
54#define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */
55#define INTR_MASK_BITS 0x383f
56
57/*
58 * General SCC mode register (GSMR)
59 */
60
61#define MODE_HDLC 0x0
62#define MODE_APPLE_TALK 0x2
63#define MODE_SS7 0x3
64#define MODE_UART 0x4
65#define MODE_PROFIBUS 0x5
66#define MODE_ASYNC_HDLC 0x6
67#define MODE_V14 0x7
68#define MODE_BISYNC 0x8
69#define MODE_DDCMP 0x9
70#define MODE_MULTI_CHANNEL 0xa
71#define MODE_ETHERNET 0xc
72
73#define DIAG_NORMAL 0x0
74#define DIAG_LOCAL_LPB 0x1
75#define DIAG_AUTO_ECHO 0x2
76#define DIAG_LBP_ECHO 0x3
77
78/* For RENC and TENC fields in GSMR */
79#define ENC_NRZ 0x0
80#define ENC_NRZI 0x1
81#define ENC_FM0 0x2
82#define ENC_MANCH 0x4
83#define ENC_DIFF_MANC 0x6
84
85/* For TDCR and RDCR fields in GSMR */
86#define CLOCK_RATE_1 0x0
87#define CLOCK_RATE_8 0x1
88#define CLOCK_RATE_16 0x2
89#define CLOCK_RATE_32 0x3
90
91#define TPP_00 0x0
92#define TPP_10 0x1
93#define TPP_01 0x2
94#define TPP_11 0x3
95
96#define TPL_NO 0x0
97#define TPL_8 0x1
98#define TPL_16 0x2
99#define TPL_32 0x3
100#define TPL_48 0x4
101#define TPL_64 0x5
102#define TPL_128 0x6
103
104#define TSNC_INFINITE 0x0
105#define TSNC_14_65 0x1
106#define TSNC_4_15 0x2
107#define TSNC_3_1 0x3
108
109#define EDGE_BOTH 0x0
110#define EDGE_POS 0x1
111#define EDGE_NEG 0x2
112#define EDGE_NO 0x3
113
114#define SYNL_NO 0x0
115#define SYNL_4 0x1
116#define SYNL_8 0x2
117#define SYNL_16 0x3
118
119#define TCRC_CCITT16 0x0
120#define TCRC_CRC16 0x1
121#define TCRC_CCITT32 0x2
122
123
124/*****************************************************************
125 TODR (Transmit on demand) Register
126*****************************************************************/
127#define TODR_TOD 0x8000 /* Transmit on demand */
128
129
130/*****************************************************************
131 CICR register settings
132*****************************************************************/
133
134/* note that relative irq priorities of the SCCs can be reordered
135 * if desired - see p. 7-377 of the MC68360UM */
136#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
137#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
138#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
139#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
140
141#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
142#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
143#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */
144#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
145
146
147/*****************************************************************
148 Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379)
149*****************************************************************/
150
151#define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */
152#define INTR_SCC1 0x40000000 /* SCC port 1 */
153#define INTR_SCC2 0x20000000 /* SCC port 2 */
154#define INTR_SCC3 0x10000000 /* SCC port 3 */
155#define INTR_SCC4 0x08000000 /* SCC port 4 */
156#define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */
157#define INTR_TIMER1 0x02000000 /* timer 1 */
158#define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */
159#define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */
160#define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */
161#define INTR_DMA1 0x00200000 /* idma 1 */
162#define INTR_DMA2 0x00100000 /* idma 2 */
163#define INTR_TIMER2 0x00040000 /* timer 2 */
164#define INTR_CP_TIMER 0x00020000 /* CP timer */
165#define INTR_PIP_STATUS 0x00010000 /* PIP status */
166#define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */
167#define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */
168#define INTR_TIMER3 0x00001000 /* timer 3 */
169#define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */
170#define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */
171#define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */
172#define INTR_TIMER4 0x00000080 /* timer 4 */
173#define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */
174#define INTR_SCP 0x00000020 /* SCP */
175#define INTR_SMC1 0x00000010 /* SMC 1 */
176#define INTR_SMC2 0x00000008 /* SMC 2 */
177#define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */
178#define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */
179#define INTR_ERR 0x00000001 /* error */
180
181
182/*****************************************************************
183 CPM Interrupt vector encodings (MC68360UM p. 7-376)
184*****************************************************************/
185
186#define CPMVEC_NR 32
187#define CPMVEC_PIO_PC0 0x1f
188#define CPMVEC_SCC1 0x1e
189#define CPMVEC_SCC2 0x1d
190#define CPMVEC_SCC3 0x1c
191#define CPMVEC_SCC4 0x1b
192#define CPMVEC_PIO_PC1 0x1a
193#define CPMVEC_TIMER1 0x19
194#define CPMVEC_PIO_PC2 0x18
195#define CPMVEC_PIO_PC3 0x17
196#define CPMVEC_SDMA_CB_ERR 0x16
197#define CPMVEC_IDMA1 0x15
198#define CPMVEC_IDMA2 0x14
199#define CPMVEC_RESERVED3 0x13
200#define CPMVEC_TIMER2 0x12
201#define CPMVEC_RISCTIMER 0x11
202#define CPMVEC_RESERVED2 0x10
203#define CPMVEC_PIO_PC4 0x0f
204#define CPMVEC_PIO_PC5 0x0e
205#define CPMVEC_TIMER3 0x0c
206#define CPMVEC_PIO_PC6 0x0b
207#define CPMVEC_PIO_PC7 0x0a
208#define CPMVEC_PIO_PC8 0x09
209#define CPMVEC_RESERVED1 0x08
210#define CPMVEC_TIMER4 0x07
211#define CPMVEC_PIO_PC9 0x06
212#define CPMVEC_SPI 0x05
213#define CPMVEC_SMC1 0x04
214#define CPMVEC_SMC2 0x03
215#define CPMVEC_PIO_PC10 0x02
216#define CPMVEC_PIO_PC11 0x01
217#define CPMVEC_ERROR 0x00
218
219/* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */
220/* #define CPMVEC_SCC1 ((ushort)0x1e) */
221/* #define CPMVEC_SCC2 ((ushort)0x1d) */
222/* #define CPMVEC_SCC3 ((ushort)0x1c) */
223/* #define CPMVEC_SCC4 ((ushort)0x1b) */
224/* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */
225/* #define CPMVEC_TIMER1 ((ushort)0x19) */
226/* #define CPMVEC_PIO_PC2 ((ushort)0x18) */
227/* #define CPMVEC_PIO_PC3 ((ushort)0x17) */
228/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
229/* #define CPMVEC_IDMA1 ((ushort)0x15) */
230/* #define CPMVEC_IDMA2 ((ushort)0x14) */
231/* #define CPMVEC_RESERVED3 ((ushort)0x13) */
232/* #define CPMVEC_TIMER2 ((ushort)0x12) */
233/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
234/* #define CPMVEC_RESERVED2 ((ushort)0x10) */
235/* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */
236/* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */
237/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
238/* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */
239/* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */
240/* #define CPMVEC_PIO_PC8 ((ushort)0x09) */
241/* #define CPMVEC_RESERVED1 ((ushort)0x08) */
242/* #define CPMVEC_TIMER4 ((ushort)0x07) */
243/* #define CPMVEC_PIO_PC9 ((ushort)0x06) */
244/* #define CPMVEC_SPI ((ushort)0x05) */
245/* #define CPMVEC_SMC1 ((ushort)0x04) */
246/* #define CPMVEC_SMC2 ((ushort)0x03) */
247/* #define CPMVEC_PIO_PC10 ((ushort)0x02) */
248/* #define CPMVEC_PIO_PC11 ((ushort)0x01) */
249/* #define CPMVEC_ERROR ((ushort)0x00) */
250
251
252/*****************************************************************
253 * PIO control registers
254 *****************************************************************/
255
256/* Port A - See 360UM p. 7-358
257 *
258 * Note that most of these pins have alternate functions
259 */
260
261
262/* The macros are nice, but there are all sorts of references to 1-indexed
263 * facilities on the 68360... */
264/* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */
265/* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */
266
267#define PA_RXD1 ((ushort)0x0001)
268#define PA_TXD1 ((ushort)0x0002)
269#define PA_RXD2 ((ushort)0x0004)
270#define PA_TXD2 ((ushort)0x0008)
271#define PA_RXD3 ((ushort)0x0010)
272#define PA_TXD3 ((ushort)0x0020)
273#define PA_RXD4 ((ushort)0x0040)
274#define PA_TXD4 ((ushort)0x0080)
275
276#define PA_CLK1 ((ushort)0x0100)
277#define PA_CLK2 ((ushort)0x0200)
278#define PA_CLK3 ((ushort)0x0400)
279#define PA_CLK4 ((ushort)0x0800)
280#define PA_CLK5 ((ushort)0x1000)
281#define PA_CLK6 ((ushort)0x2000)
282#define PA_CLK7 ((ushort)0x4000)
283#define PA_CLK8 ((ushort)0x8000)
284
285
286/* Port B - See 360UM p. 7-362
287 */
288
289
290/* Port C - See 360UM p. 7-365
291 */
292
293#define PC_RTS1 ((ushort)0x0001)
294#define PC_RTS2 ((ushort)0x0002)
295#define PC__RTS3 ((ushort)0x0004) /* !RTS3 */
296#define PC__RTS4 ((ushort)0x0008) /* !RTS4 */
297
298#define PC_CTS1 ((ushort)0x0010)
299#define PC_CD1 ((ushort)0x0020)
300#define PC_CTS2 ((ushort)0x0040)
301#define PC_CD2 ((ushort)0x0080)
302#define PC_CTS3 ((ushort)0x0100)
303#define PC_CD3 ((ushort)0x0200)
304#define PC_CTS4 ((ushort)0x0400)
305#define PC_CD4 ((ushort)0x0800)
306
307
308
309/*****************************************************************
310 chip select option register
311*****************************************************************/
312#define DTACK 0xe000
313#define ADR_MASK 0x1ffc
314#define RDWR_MASK 0x0002
315#define FC_MASK 0x0001
316
317/*****************************************************************
318 tbase and rbase registers
319*****************************************************************/
320#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \
321 (quicc->ch_or_u.u.udata_bd_ucode + pram->tbase))
322#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \
323 (quicc->ch_or_u.u.udata_bd_ucode + pram->rbase))
324#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
325 (quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr))
326#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
327 (quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr))
328#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \
329 ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
330#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \
331 ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
332#define INCREASE_TBD(bd,quicc,pram) { \
333 if((bd)->status & T_W) \
334 (bd) = TBD_ADDR(quicc,pram); \
335 else \
336 (bd)++; \
337}
338#define DECREASE_TBD(bd,quicc,pram) { \
339 if ((bd) == TBD_ADDR(quicc, pram)) \
340 while (!((bd)->status & T_W)) \
341 (bd)++; \
342 else \
343 (bd)--; \
344}
345#define INCREASE_RBD(bd,quicc,pram) { \
346 if((bd)->status & R_W) \
347 (bd) = RBD_ADDR(quicc,pram); \
348 else \
349 (bd)++; \
350}
351#define DECREASE_RBD(bd,quicc,pram) { \
352 if ((bd) == RBD_ADDR(quicc, pram)) \
353 while (!((bd)->status & T_W)) \
354 (bd)++; \
355 else \
356 (bd)--; \
357}
358
359/*****************************************************************
360 Macros for Multi channel
361*****************************************************************/
362#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page])
363#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase)
364#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \
365 (&(quicc->ch_or_u.ch_pram_tbl[channel])))
366#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
367 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase)))
368#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
369 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase)))
370#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
371 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr)))
372#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
373 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr)))
374#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
375 CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \
376 ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
377#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
378 CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \
379 ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
380
381#define INCREASE_TBD_32(bd,quicc,page,channel) { \
382 if((bd)->status & T_W) \
383 (bd) = TBD_32_ADDR(quicc,page,channel); \
384 else \
385 (bd)++; \
386}
387#define DECREASE_TBD_32(bd,quicc,page,channel) { \
388 if ((bd) == TBD_32_ADDR(quicc, page,channel)) \
389 while (!((bd)->status & T_W)) \
390 (bd)++; \
391 else \
392 (bd)--; \
393}
394#define INCREASE_RBD_32(bd,quicc,page,channel) { \
395 if((bd)->status & R_W) \
396 (bd) = RBD_32_ADDR(quicc,page,channel); \
397 else \
398 (bd)++; \
399}
400#define DECREASE_RBD_32(bd,quicc,page,channel) { \
401 if ((bd) == RBD_32_ADDR(quicc, page,channel)) \
402 while (!((bd)->status & T_W)) \
403 (bd)++; \
404 else \
405 (bd)--; \
406}
407
408#endif
diff --git a/arch/m68knommu/include/asm/machdep.h b/arch/m68knommu/include/asm/machdep.h
new file mode 100644
index 000000000000..de9f47a51cc2
--- /dev/null
+++ b/arch/m68knommu/include/asm/machdep.h
@@ -0,0 +1,26 @@
1#ifndef _M68KNOMMU_MACHDEP_H
2#define _M68KNOMMU_MACHDEP_H
3
4#include <linux/interrupt.h>
5
6/* Hardware clock functions */
7extern void hw_timer_init(void);
8extern unsigned long hw_timer_offset(void);
9
10extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
11
12/* Machine dependent time handling */
13extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
14 int *min, int *sec);
15extern int (*mach_set_clock_mmss)(unsigned long);
16
17/* machine dependent power off functions */
18extern void (*mach_reset)( void );
19extern void (*mach_halt)( void );
20extern void (*mach_power_off)( void );
21
22extern void config_BSP(char *command, int len);
23
24extern void do_IRQ(int irq, struct pt_regs *fp);
25
26#endif /* _M68KNOMMU_MACHDEP_H */
diff --git a/arch/m68knommu/include/asm/math-emu.h b/arch/m68knommu/include/asm/math-emu.h
new file mode 100644
index 000000000000..7e7090517b72
--- /dev/null
+++ b/arch/m68knommu/include/asm/math-emu.h
@@ -0,0 +1 @@
#include <asm-m68k/math-emu.h>
diff --git a/arch/m68knommu/include/asm/mc146818rtc.h b/arch/m68knommu/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..907a0481a140
--- /dev/null
+++ b/arch/m68knommu/include/asm/mc146818rtc.h
@@ -0,0 +1,9 @@
1/*
2 * Machine dependent access functions for RTC registers.
3 */
4#ifndef _M68KNOMMU_MC146818RTC_H
5#define _M68KNOMMU_MC146818RTC_H
6
7/* empty include file to satisfy the include in genrtc.c/ide-geometry.c */
8
9#endif /* _M68KNOMMU_MC146818RTC_H */
diff --git a/arch/m68knommu/include/asm/mcfcache.h b/arch/m68knommu/include/asm/mcfcache.h
new file mode 100644
index 000000000000..c042634fadaa
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfcache.h
@@ -0,0 +1,150 @@
1/****************************************************************************/
2
3/*
4 * mcfcache.h -- ColdFire CPU cache support code
5 *
6 * (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
7 */
8
9/****************************************************************************/
10#ifndef __M68KNOMMU_MCFCACHE_H
11#define __M68KNOMMU_MCFCACHE_H
12/****************************************************************************/
13
14
15/*
16 * The different ColdFire families have different cache arrangments.
17 * Everything from a small instruction only cache, to configurable
18 * data and/or instruction cache, to unified instruction/data, to
19 * harvard style separate instruction and data caches.
20 */
21
22#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
23/*
24 * Simple version 2 core cache. These have instruction cache only,
25 * we just need to invalidate it and enable it.
26 */
27.macro CACHE_ENABLE
28 movel #0x01000000,%d0 /* invalidate cache cmd */
29 movec %d0,%CACR /* do invalidate cache */
30 movel #0x80000100,%d0 /* setup cache mask */
31 movec %d0,%CACR /* enable cache */
32.endm
33#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
34
35#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
36/*
37 * New version 2 cores have a configurable split cache arrangement.
38 * For now I am just enabling instruction cache - but ultimately I
39 * think a split instruction/data cache would be better.
40 */
41.macro CACHE_ENABLE
42 movel #0x01400000,%d0
43 movec %d0,%CACR /* invalidate cache */
44 nop
45 movel #0x0000c000,%d0 /* set SDRAM cached only */
46 movec %d0,%ACR0
47 movel #0x00000000,%d0 /* no other regions cached */
48 movec %d0,%ACR1
49 movel #0x80400100,%d0 /* configure cache */
50 movec %d0,%CACR /* enable cache */
51 nop
52.endm
53#endif /* CONFIG_M523x || CONFIG_M527x */
54
55#if defined(CONFIG_M528x)
56.macro CACHE_ENABLE
57 nop
58 movel #0x01000000, %d0
59 movec %d0, %CACR /* Invalidate cache */
60 nop
61 movel #0x0000c020, %d0 /* Set SDRAM cached only */
62 movec %d0, %ACR0
63 movel #0x00000000, %d0 /* No other regions cached */
64 movec %d0, %ACR1
65 movel #0x80000200, %d0 /* Setup cache mask */
66 movec %d0, %CACR /* Enable cache */
67 nop
68.endm
69#endif /* CONFIG_M528x */
70
71#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
72/*
73 * The version 3 core cache. Oddly enough the version 2 core 5249
74 * has the same SDRAM and cache setup as the version 3 cores.
75 * This is a single unified instruction/data cache.
76 */
77.macro CACHE_ENABLE
78 movel #0x01000000,%d0 /* invalidate whole cache */
79 movec %d0,%CACR
80 nop
81#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
82 movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
83#else
84 movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */
85#endif
86 movec %d0,%ACR0
87 movel #0x00000000,%d0 /* no other regions cached */
88 movec %d0,%ACR1
89 movel #0xa0000200,%d0 /* enable cache */
90 movec %d0,%CACR
91 nop
92.endm
93#endif /* CONFIG_M5249 || CONFIG_M5307 */
94
95#if defined(CONFIG_M532x)
96.macro CACHE_ENABLE
97 movel #0x01000000,%d0 /* invalidate cache cmd */
98 movec %d0,%CACR /* do invalidate cache */
99 nop
100 movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
101 movec %d0,%ACR0
102 movel #0x00000000,%d0 /* no other regions cached */
103 movec %d0,%ACR1
104 movel #0x80000200,%d0 /* setup cache mask */
105 movec %d0,%CACR /* enable cache */
106 nop
107.endm
108#endif /* CONFIG_M532x */
109
110#if defined(CONFIG_M5407)
111/*
112 * Version 4 cores have a true harvard style separate instruction
113 * and data cache. Invalidate and enable cache, also enable write
114 * buffers and branch accelerator.
115 */
116.macro CACHE_ENABLE
117 movel #0x01040100,%d0 /* invalidate whole cache */
118 movec %d0,%CACR
119 nop
120 movel #0x000fc000,%d0 /* set SDRAM cached only */
121 movec %d0, %ACR0
122 movel #0x00000000,%d0 /* no other regions cached */
123 movec %d0, %ACR1
124 movel #0x000fc000,%d0 /* set SDRAM cached only */
125 movec %d0, %ACR2
126 movel #0x00000000,%d0 /* no other regions cached */
127 movec %d0, %ACR3
128 movel #0xb6088400,%d0 /* enable caches */
129 movec %d0,%CACR
130 nop
131.endm
132#endif /* CONFIG_M5407 */
133
134#if defined(CONFIG_M520x)
135.macro CACHE_ENABLE
136 move.l #0x01000000,%d0 /* invalidate whole cache */
137 movec %d0,%CACR
138 nop
139 move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
140 movec %d0,%ACR0
141 move.l #0x00000000,%d0 /* no other regions cached */
142 movec %d0,%ACR1
143 move.l #0x80400000,%d0 /* enable 8K instruction cache */
144 movec %d0,%CACR
145 nop
146.endm
147#endif /* CONFIG_M520x */
148
149/****************************************************************************/
150#endif /* __M68KNOMMU_MCFCACHE_H */
diff --git a/arch/m68knommu/include/asm/mcfdma.h b/arch/m68knommu/include/asm/mcfdma.h
new file mode 100644
index 000000000000..705c52c79cd8
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfdma.h
@@ -0,0 +1,144 @@
1/****************************************************************************/
2
3/*
4 * mcfdma.h -- Coldfire internal DMA support defines.
5 *
6 * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org)
7 */
8
9/****************************************************************************/
10#ifndef mcfdma_h
11#define mcfdma_h
12/****************************************************************************/
13
14
15/*
16 * Get address specific defines for this Coldfire member.
17 */
18#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
19#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
20#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
21#elif defined(CONFIG_M5272)
22#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */
23#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
24/* These are relative to the IPSBAR, not MBAR */
25#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */
26#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */
27#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */
28#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */
29#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
30#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
31#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
32#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
33#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
34#endif
35
36
37#if !defined(CONFIG_M5272)
38
39/*
40 * Define the DMA register set addresses.
41 * Note: these are longword registers, use unsigned long as data type
42 */
43#define MCFDMA_SAR 0x00 /* DMA source address (r/w) */
44#define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */
45/* these are word registers, use unsigned short data type */
46#define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */
47#define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */
48/* these are byte registers, use unsiged char data type */
49#define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */
50#define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
51
52/*
53 * Bit definitions for the DMA Control Register (DCR).
54 */
55#define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */
56#define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */
57#define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */
58#define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */
59#define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */
60#define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */
61#define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */
62#define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */
63#define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */
64#define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */
65#define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */
66#define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */
67#define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */
68#define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */
69#define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */
70#define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */
71#define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */
72#define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */
73#define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */
74#define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */
75#define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */
76#define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */
77#define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */
78#define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */
79#define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */
80#define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */
81#define MCFDMA_DCR_START 0x0001 /* Start transfer */
82
83/*
84 * Bit definitions for the DMA Status Register (DSR).
85 */
86#define MCFDMA_DSR_CE 0x40 /* Config error */
87#define MCFDMA_DSR_BES 0x20 /* Bus Error on source */
88#define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */
89#define MCFDMA_DSR_REQ 0x04 /* Requests remaining */
90#define MCFDMA_DSR_BSY 0x02 /* Busy */
91#define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */
92
93#else /* This is an MCF5272 */
94
95#define MCFDMA_DMR 0x00 /* Mode Register (r/w) */
96#define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */
97#define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */
98#define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */
99#define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */
100
101/* Bit definitions for the DMA Mode Register (DMR) */
102#define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */
103#define MCFDMA_DMR_EN 0x40000000L /* DMA enable */
104#define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */
105#define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */
106#define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */
107#define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */
108#define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */
109#define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */
110#define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */
111#define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
112#define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
113#define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */
114#define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */
115#define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */
116#define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */
117#define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */
118#define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */
119#define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */
120#define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */
121#define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */
122#define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */
123#define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
124#define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
125#define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */
126#define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */
127#define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */
128#define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */
129#define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */
130
131/* Bit definitions for the DMA interrupt register (DIR) */
132#define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */
133#define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */
134#define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */
135#define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */
136#define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */
137#define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */
138#define MCFDMA_DIR_TE 0x0002 /* Transfer Error */
139#define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */
140
141#endif /* !defined(CONFIG_M5272) */
142
143/****************************************************************************/
144#endif /* mcfdma_h */
diff --git a/arch/m68knommu/include/asm/mcfmbus.h b/arch/m68knommu/include/asm/mcfmbus.h
new file mode 100644
index 000000000000..319899c47a2c
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfmbus.h
@@ -0,0 +1,77 @@
1/****************************************************************************/
2
3/*
4 * mcfmbus.h -- Coldfire MBUS support defines.
5 *
6 * (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de)
7 */
8
9/****************************************************************************/
10
11
12#ifndef mcfmbus_h
13#define mcfmbus_h
14
15
16#define MCFMBUS_BASE 0x280
17#define MCFMBUS_IRQ_VECTOR 0x19
18#define MCFMBUS_IRQ 0x1
19#define MCFMBUS_CLK 0x3f
20#define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/
21#define MCFMBUS_ADDRESS 0x01
22
23
24/*
25* Define the 5307 MBUS register set addresses
26*/
27
28#define MCFMBUS_MADR 0x00
29#define MCFMBUS_MFDR 0x04
30#define MCFMBUS_MBCR 0x08
31#define MCFMBUS_MBSR 0x0C
32#define MCFMBUS_MBDR 0x10
33
34
35#define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/
36
37#define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/
38
39/*
40* Define bit flags in Control Register
41*/
42
43#define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */
44#define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */
45#define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */
46#define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */
47#define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */
48#define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */
49
50/*
51* Define bit flags in Status Register
52*/
53
54#define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */
55#define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */
56#define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */
57#define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */
58#define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */
59#define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */
60#define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */
61
62/*
63* Define bit flags in DATA I/O Register
64*/
65
66#define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */
67
68#define MBUSIOCSCLOCK 1
69#define MBUSIOCGCLOCK 2
70#define MBUSIOCSADDR 3
71#define MBUSIOCGADDR 4
72#define MBUSIOCSSLADDR 5
73#define MBUSIOCGSLADDR 6
74#define MBUSIOCSSUBADDR 7
75#define MBUSIOCGSUBADDR 8
76
77#endif
diff --git a/arch/m68knommu/include/asm/mcfne.h b/arch/m68knommu/include/asm/mcfne.h
new file mode 100644
index 000000000000..431f63aadd0e
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfne.h
@@ -0,0 +1,325 @@
1/****************************************************************************/
2
3/*
4 * mcfne.h -- NE2000 in ColdFire eval boards.
5 *
6 * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo (www.lineo.com)
8 * (C) Copyright 2001, SnapGear (www.snapgear.com)
9 *
10 * 19990409 David W. Miller Converted from m5206ne.h for 5307 eval board
11 *
12 * Hacked support for m5206e Cadre III evaluation board
13 * Fred Stevens (fred.stevens@pemstar.com) 13 April 1999
14 */
15
16/****************************************************************************/
17#ifndef mcfne_h
18#define mcfne_h
19/****************************************************************************/
20
21
22/*
23 * Support for NE2000 clones devices in ColdFire based boards.
24 * Not all boards address these parts the same way, some use a
25 * direct addressing method, others use a side-band address space
26 * to access odd address registers, some require byte swapping
27 * others do not.
28 */
29#define BSWAP(w) (((w) << 8) | ((w) >> 8))
30#define RSWAP(w) (w)
31
32
33/*
34 * Define the basic hardware resources of NE2000 boards.
35 */
36
37#if defined(CONFIG_ARN5206)
38#define NE2000_ADDR 0x40000300
39#define NE2000_ODDOFFSET 0x00010000
40#define NE2000_IRQ_VECTOR 0xf0
41#define NE2000_IRQ_PRIORITY 2
42#define NE2000_IRQ_LEVEL 4
43#define NE2000_BYTE volatile unsigned short
44#endif
45
46#if defined(CONFIG_M5206eC3)
47#define NE2000_ADDR 0x40000300
48#define NE2000_ODDOFFSET 0x00010000
49#define NE2000_IRQ_VECTOR 0x1c
50#define NE2000_IRQ_PRIORITY 2
51#define NE2000_IRQ_LEVEL 4
52#define NE2000_BYTE volatile unsigned short
53#endif
54
55#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
56#define NE2000_ADDR 0x30000300
57#define NE2000_IRQ_VECTOR 25
58#define NE2000_IRQ_PRIORITY 1
59#define NE2000_IRQ_LEVEL 3
60#define NE2000_BYTE volatile unsigned char
61#endif
62
63#if defined(CONFIG_M5307C3)
64#define NE2000_ADDR 0x40000300
65#define NE2000_ODDOFFSET 0x00010000
66#define NE2000_IRQ_VECTOR 0x1b
67#define NE2000_BYTE volatile unsigned short
68#endif
69
70#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
71#define NE2000_ADDR 0x30600300
72#define NE2000_ODDOFFSET 0x00008000
73#define NE2000_IRQ_VECTOR 67
74#undef BSWAP
75#define BSWAP(w) (w)
76#define NE2000_BYTE volatile unsigned short
77#undef RSWAP
78#define RSWAP(w) (((w) << 8) | ((w) >> 8))
79#endif
80
81#if defined(CONFIG_M5307) && defined(CONFIG_NETtel)
82#define NE2000_ADDR0 0x30600300
83#define NE2000_ADDR1 0x30800300
84#define NE2000_ODDOFFSET 0x00008000
85#define NE2000_IRQ_VECTOR0 27
86#define NE2000_IRQ_VECTOR1 29
87#undef BSWAP
88#define BSWAP(w) (w)
89#define NE2000_BYTE volatile unsigned short
90#undef RSWAP
91#define RSWAP(w) (((w) << 8) | ((w) >> 8))
92#endif
93
94#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
95#define NE2000_ADDR 0x30600300
96#define NE2000_ODDOFFSET 0x00008000
97#define NE2000_IRQ_VECTOR 27
98#undef BSWAP
99#define BSWAP(w) (w)
100#define NE2000_BYTE volatile unsigned short
101#undef RSWAP
102#define RSWAP(w) (((w) << 8) | ((w) >> 8))
103#endif
104
105#if defined(CONFIG_ARN5307)
106#define NE2000_ADDR 0xfe600300
107#define NE2000_ODDOFFSET 0x00010000
108#define NE2000_IRQ_VECTOR 0x1b
109#define NE2000_IRQ_PRIORITY 2
110#define NE2000_IRQ_LEVEL 3
111#define NE2000_BYTE volatile unsigned short
112#endif
113
114#if defined(CONFIG_M5407C3)
115#define NE2000_ADDR 0x40000300
116#define NE2000_ODDOFFSET 0x00010000
117#define NE2000_IRQ_VECTOR 0x1b
118#define NE2000_BYTE volatile unsigned short
119#endif
120
121/****************************************************************************/
122
123/*
124 * Side-band address space for odd address requires re-mapping
125 * many of the standard ISA access functions.
126 */
127#ifdef NE2000_ODDOFFSET
128
129#undef outb
130#undef outb_p
131#undef inb
132#undef inb_p
133#undef outsb
134#undef outsw
135#undef insb
136#undef insw
137
138#define outb ne2000_outb
139#define inb ne2000_inb
140#define outb_p ne2000_outb
141#define inb_p ne2000_inb
142#define outsb ne2000_outsb
143#define outsw ne2000_outsw
144#define insb ne2000_insb
145#define insw ne2000_insw
146
147
148#ifndef COLDFIRE_NE2000_FUNCS
149
150void ne2000_outb(unsigned int val, unsigned int addr);
151int ne2000_inb(unsigned int addr);
152void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len);
153void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len);
154void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len);
155void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len);
156
157#else
158
159/*
160 * This macro converts a conventional register address into the
161 * real memory pointer of the mapped NE2000 device.
162 * On most NE2000 implementations on ColdFire boards the chip is
163 * mapped in kinda funny, due to its ISA heritage.
164 */
165#define NE2000_PTR(addr) ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr))
166#define NE2000_DATA_PTR(addr) (addr)
167
168
169void ne2000_outb(unsigned int val, unsigned int addr)
170{
171 NE2000_BYTE *rp;
172
173 rp = (NE2000_BYTE *) NE2000_PTR(addr);
174 *rp = RSWAP(val);
175}
176
177int ne2000_inb(unsigned int addr)
178{
179 NE2000_BYTE *rp, val;
180
181 rp = (NE2000_BYTE *) NE2000_PTR(addr);
182 val = *rp;
183 return((int) ((NE2000_BYTE) RSWAP(val)));
184}
185
186void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len)
187{
188 NE2000_BYTE *rp, val;
189 unsigned char *buf;
190
191 buf = (unsigned char *) vbuf;
192 rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
193 for (; (len > 0); len--) {
194 val = *rp;
195 *buf++ = RSWAP(val);
196 }
197}
198
199void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len)
200{
201 volatile unsigned short *rp;
202 unsigned short w, *buf;
203
204 buf = (unsigned short *) vbuf;
205 rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
206 for (; (len > 0); len--) {
207 w = *rp;
208 *buf++ = BSWAP(w);
209 }
210}
211
212void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len)
213{
214 NE2000_BYTE *rp, val;
215 unsigned char *buf;
216
217 buf = (unsigned char *) vbuf;
218 rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
219 for (; (len > 0); len--) {
220 val = *buf++;
221 *rp = RSWAP(val);
222 }
223}
224
225void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
226{
227 volatile unsigned short *rp;
228 unsigned short w, *buf;
229
230 buf = (unsigned short *) vbuf;
231 rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
232 for (; (len > 0); len--) {
233 w = *buf++;
234 *rp = BSWAP(w);
235 }
236}
237
238#endif /* COLDFIRE_NE2000_FUNCS */
239#endif /* NE2000_OFFOFFSET */
240
241/****************************************************************************/
242
243#ifdef COLDFIRE_NE2000_FUNCS
244
245/*
246 * Lastly the interrupt set up code...
247 * Minor differences between the different board types.
248 */
249
250#if defined(CONFIG_ARN5206)
251void ne2000_irqsetup(int irq)
252{
253 volatile unsigned char *icrp;
254
255 icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
256 *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2;
257 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
258}
259#endif
260
261#if defined(CONFIG_M5206eC3)
262void ne2000_irqsetup(int irq)
263{
264 volatile unsigned char *icrp;
265
266 icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
267 *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2 | MCFSIM_ICR_AUTOVEC;
268 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
269}
270#endif
271
272#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
273void ne2000_irqsetup(int irq)
274{
275 mcf_autovector(irq);
276}
277#endif
278
279#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
280void ne2000_irqsetup(int irq)
281{
282 volatile unsigned long *icrp;
283 volatile unsigned long *pitr;
284
285 /* The NE2000 device uses external IRQ3 */
286 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
287 *icrp = (*icrp & 0x77077777) | 0x00d00000;
288
289 pitr = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PITR);
290 *pitr = *pitr | 0x20000000;
291}
292
293void ne2000_irqack(int irq)
294{
295 volatile unsigned long *icrp;
296
297 /* The NE2000 device uses external IRQ3 */
298 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
299 *icrp = (*icrp & 0x77777777) | 0x00800000;
300}
301#endif
302
303#if defined(CONFIG_M5307) || defined(CONFIG_M5407)
304#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
305
306void ne2000_irqsetup(int irq)
307{
308 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3);
309 mcf_autovector(irq);
310}
311
312#else
313
314void ne2000_irqsetup(int irq)
315{
316 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3);
317}
318
319#endif /* ! CONFIG_NETtel || CONFIG_SECUREEDGEMP3 */
320#endif /* CONFIG_M5307 || CONFIG_M5407 */
321
322#endif /* COLDFIRE_NE2000_FUNCS */
323
324/****************************************************************************/
325#endif /* mcfne_h */
diff --git a/arch/m68knommu/include/asm/mcfpci.h b/arch/m68knommu/include/asm/mcfpci.h
new file mode 100644
index 000000000000..f1507dd06ec6
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfpci.h
@@ -0,0 +1,119 @@
1/****************************************************************************/
2
3/*
4 * mcfpci.h -- PCI bridge on ColdFire eval boards.
5 *
6 * (C) Copyright 2000, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef mcfpci_h
12#define mcfpci_h
13/****************************************************************************/
14
15
16#ifdef CONFIG_PCI
17
18/*
19 * Address regions in the PCI address space are not mapped into the
20 * normal memory space of the ColdFire. They must be accessed via
21 * handler routines. This is easy for I/O space (inb/outb/etc) but
22 * needs some code changes to support ordinary memory. Interrupts
23 * also need to be vectored through the PCI handler first, then it
24 * will call the actual driver sub-handlers.
25 */
26
27/*
28 * Un-define all the standard I/O access routines.
29 */
30#undef inb
31#undef inw
32#undef inl
33#undef inb_p
34#undef inw_p
35#undef insb
36#undef insw
37#undef insl
38#undef outb
39#undef outw
40#undef outl
41#undef outb_p
42#undef outw_p
43#undef outsb
44#undef outsw
45#undef outsl
46
47#undef request_irq
48#undef free_irq
49
50#undef bus_to_virt
51#undef virt_to_bus
52
53
54/*
55 * Re-direct all I/O memory accesses functions to PCI specific ones.
56 */
57#define inb pci_inb
58#define inw pci_inw
59#define inl pci_inl
60#define inb_p pci_inb
61#define inw_p pci_inw
62#define insb pci_insb
63#define insw pci_insw
64#define insl pci_insl
65
66#define outb pci_outb
67#define outw pci_outw
68#define outl pci_outl
69#define outb_p pci_outb
70#define outw_p pci_outw
71#define outsb pci_outsb
72#define outsw pci_outsw
73#define outsl pci_outsl
74
75#define request_irq pci_request_irq
76#define free_irq pci_free_irq
77
78#define virt_to_bus pci_virt_to_bus
79#define bus_to_virt pci_bus_to_virt
80
81#define CONFIG_COMEMPCI 1
82
83
84/*
85 * Prototypes of the real PCI functions (defined in bios32.c).
86 */
87unsigned char pci_inb(unsigned int addr);
88unsigned short pci_inw(unsigned int addr);
89unsigned int pci_inl(unsigned int addr);
90void pci_insb(void *addr, void *buf, int len);
91void pci_insw(void *addr, void *buf, int len);
92void pci_insl(void *addr, void *buf, int len);
93
94void pci_outb(unsigned char val, unsigned int addr);
95void pci_outw(unsigned short val, unsigned int addr);
96void pci_outl(unsigned int val, unsigned int addr);
97void pci_outsb(void *addr, void *buf, int len);
98void pci_outsw(void *addr, void *buf, int len);
99void pci_outsl(void *addr, void *buf, int len);
100
101int pci_request_irq(unsigned int irq,
102 void (*handler)(int, void *, struct pt_regs *),
103 unsigned long flags,
104 const char *device,
105 void *dev_id);
106void pci_free_irq(unsigned int irq, void *dev_id);
107
108void *pci_bmalloc(int size);
109void pci_bmfree(void *bmp, int len);
110void pci_copytoshmem(unsigned long bmp, void *src, int size);
111void pci_copyfromshmem(void *dst, unsigned long bmp, int size);
112unsigned long pci_virt_to_bus(volatile void *address);
113void *pci_bus_to_virt(unsigned long address);
114void pci_bmcpyto(void *dst, void *src, int len);
115void pci_bmcpyfrom(void *dst, void *src, int len);
116
117#endif /* CONFIG_PCI */
118/****************************************************************************/
119#endif /* mcfpci_h */
diff --git a/arch/m68knommu/include/asm/mcfpit.h b/arch/m68knommu/include/asm/mcfpit.h
new file mode 100644
index 000000000000..f570cf64fd29
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfpit.h
@@ -0,0 +1,64 @@
1/****************************************************************************/
2
3/*
4 * mcfpit.h -- ColdFire internal PIT timer support defines.
5 *
6 * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef mcfpit_h
11#define mcfpit_h
12/****************************************************************************/
13
14
15/*
16 * Get address specific defines for the 5270/5271, 5280/5282, and 5208.
17 */
18#if defined(CONFIG_M520x)
19#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
20#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
21#else
22#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
23#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
24#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
25#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
26#endif
27
28/*
29 * Define the PIT timer register set addresses.
30 */
31#define MCFPIT_PCSR 0x0 /* PIT control register */
32#define MCFPIT_PMR 0x2 /* PIT modulus register */
33#define MCFPIT_PCNTR 0x4 /* PIT count register */
34
35/*
36 * Bit definitions for the PIT Control and Status register.
37 */
38#define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
39#define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
40#define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
41#define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
42#define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
43#define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
44#define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
45#define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */
46#define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */
47#define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */
48#define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */
49#define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */
50#define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */
51#define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */
52#define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */
53#define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */
54#define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */
55#define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */
56#define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */
57#define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */
58#define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */
59#define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */
60#define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */
61#define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */
62
63/****************************************************************************/
64#endif /* mcfpit_h */
diff --git a/arch/m68knommu/include/asm/mcfsim.h b/arch/m68knommu/include/asm/mcfsim.h
new file mode 100644
index 000000000000..da3f2ceff3a4
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfsim.h
@@ -0,0 +1,126 @@
1/****************************************************************************/
2
3/*
4 * mcfsim.h -- ColdFire System Integration Module support.
5 *
6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef mcfsim_h
12#define mcfsim_h
13/****************************************************************************/
14
15
16/*
17 * Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282,
18 * 5307 or 5407 specific addresses.
19 */
20#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
21#include <asm/m5206sim.h>
22#elif defined(CONFIG_M520x)
23#include <asm/m520xsim.h>
24#elif defined(CONFIG_M523x)
25#include <asm/m523xsim.h>
26#elif defined(CONFIG_M5249)
27#include <asm/m5249sim.h>
28#elif defined(CONFIG_M527x)
29#include <asm/m527xsim.h>
30#elif defined(CONFIG_M5272)
31#include <asm/m5272sim.h>
32#elif defined(CONFIG_M528x)
33#include <asm/m528xsim.h>
34#elif defined(CONFIG_M5307)
35#include <asm/m5307sim.h>
36#elif defined(CONFIG_M532x)
37#include <asm/m532xsim.h>
38#elif defined(CONFIG_M5407)
39#include <asm/m5407sim.h>
40#endif
41
42
43/*
44 * Define the base address of the SIM within the MBAR address space.
45 */
46#define MCFSIM_BASE 0x0 /* Base address of SIM */
47
48
49/*
50 * Bit definitions for the ICR family of registers.
51 */
52#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
53#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
54#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
55#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
56#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
57#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
58#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
59#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
60#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
61
62#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
63#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
64#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
65#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
66
67/*
68 * Bit definitions for the Interrupt Mask register (IMR).
69 */
70#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
71#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
72#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
73#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
74#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
75#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
76#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
77
78#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
79#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
80#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
81#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
82#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
83#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
84
85#if defined(CONFIG_M5206e)
86#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
87#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
88#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
89#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
90#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
91#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
92#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
93#endif
94
95/*
96 * Mask for all of the SIM devices. Some parts have more or less
97 * SIM devices. This is a catchall for the sandard set.
98 */
99#ifndef MCFSIM_IMR_MASKALL
100#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
101#endif
102
103
104/*
105 * PIT interrupt settings, if not found in mXXXXsim.h file.
106 */
107#ifndef ICR_INTRCONF
108#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
109#endif
110#ifndef MCFPIT_IMR
111#define MCFPIT_IMR MCFINTC_IMRH
112#endif
113#ifndef MCFPIT_IMR_IBIT
114#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
115#endif
116
117
118#ifndef __ASSEMBLY__
119/*
120 * Definition for the interrupt auto-vectoring support.
121 */
122extern void mcf_autovector(unsigned int vec);
123#endif /* __ASSEMBLY__ */
124
125/****************************************************************************/
126#endif /* mcfsim_h */
diff --git a/arch/m68knommu/include/asm/mcfsmc.h b/arch/m68knommu/include/asm/mcfsmc.h
new file mode 100644
index 000000000000..2d7a4dbd9683
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfsmc.h
@@ -0,0 +1,187 @@
1/****************************************************************************/
2
3/*
4 * mcfsmc.h -- SMC ethernet support for ColdFire environments.
5 *
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef mcfsmc_h
12#define mcfsmc_h
13/****************************************************************************/
14
15/*
16 * None of the current ColdFire targets that use the SMC91x111
17 * allow 8 bit accesses. So this code is 16bit access only.
18 */
19
20
21#undef outb
22#undef inb
23#undef outw
24#undef outwd
25#undef inw
26#undef outl
27#undef inl
28
29#undef outsb
30#undef outsw
31#undef outsl
32#undef insb
33#undef insw
34#undef insl
35
36/*
37 * Re-defines for ColdFire environment... The SMC part is
38 * mapped into memory space, so remap the PC-style in/out
39 * routines to handle that.
40 */
41#define outb smc_outb
42#define inb smc_inb
43#define outw smc_outw
44#define outwd smc_outwd
45#define inw smc_inw
46#define outl smc_outl
47#define inl smc_inl
48
49#define outsb smc_outsb
50#define outsw smc_outsw
51#define outsl smc_outsl
52#define insb smc_insb
53#define insw smc_insw
54#define insl smc_insl
55
56
57static inline int smc_inb(unsigned int addr)
58{
59 register unsigned short w;
60 w = *((volatile unsigned short *) (addr & ~0x1));
61 return(((addr & 0x1) ? w : (w >> 8)) & 0xff);
62}
63
64static inline void smc_outw(unsigned int val, unsigned int addr)
65{
66 *((volatile unsigned short *) addr) = (val << 8) | (val >> 8);
67}
68
69static inline int smc_inw(unsigned int addr)
70{
71 register unsigned short w;
72 w = *((volatile unsigned short *) addr);
73 return(((w << 8) | (w >> 8)) & 0xffff);
74}
75
76static inline void smc_outl(unsigned long val, unsigned int addr)
77{
78 *((volatile unsigned long *) addr) =
79 ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) |
80 ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff);
81}
82
83static inline void smc_outwd(unsigned int val, unsigned int addr)
84{
85 *((volatile unsigned short *) addr) = val;
86}
87
88
89/*
90 * The rep* functions are used to feed the data port with
91 * raw data. So we do not byte swap them when copying.
92 */
93
94static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len)
95{
96 volatile unsigned short *rp;
97 unsigned short *buf, *ebuf;
98
99 buf = (unsigned short *) vbuf;
100 rp = (volatile unsigned short *) addr;
101
102 /* Copy as words for as long as possible */
103 for (ebuf = buf + (len >> 1); (buf < ebuf); )
104 *buf++ = *rp;
105
106 /* Lastly, handle left over byte */
107 if (len & 0x1)
108 *((unsigned char *) buf) = (*rp >> 8) & 0xff;
109}
110
111static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len)
112{
113 volatile unsigned short *rp;
114 unsigned short *buf, *ebuf;
115
116 buf = (unsigned short *) vbuf;
117 rp = (volatile unsigned short *) addr;
118 for (ebuf = buf + len; (buf < ebuf); )
119 *buf++ = *rp;
120}
121
122static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len)
123{
124 volatile unsigned long *rp;
125 unsigned long *buf, *ebuf;
126
127 buf = (unsigned long *) vbuf;
128 rp = (volatile unsigned long *) addr;
129 for (ebuf = buf + len; (buf < ebuf); )
130 *buf++ = *rp;
131}
132
133static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len)
134{
135 volatile unsigned short *rp;
136 unsigned short *buf, *ebuf;
137
138 buf = (unsigned short *) vbuf;
139 rp = (volatile unsigned short *) addr;
140 for (ebuf = buf + len; (buf < ebuf); )
141 *rp = *buf++;
142}
143
144static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len)
145{
146 volatile unsigned long *rp;
147 unsigned long *buf, *ebuf;
148
149 buf = (unsigned long *) vbuf;
150 rp = (volatile unsigned long *) addr;
151 for (ebuf = buf + len; (buf < ebuf); )
152 *rp = *buf++;
153}
154
155
156#ifdef CONFIG_NETtel
157/*
158 * Re-map the address space of at least one of the SMC ethernet
159 * parts. Both parts power up decoding the same address, so we
160 * need to move one of them first, before doing enything else.
161 *
162 * We also increase the number of wait states for this part by one.
163 */
164
165void smc_remap(unsigned int ioaddr)
166{
167 static int once = 0;
168 extern unsigned short ppdata;
169 if (once++ == 0) {
170 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADDR)) = 0x00ec;
171 ppdata |= 0x0080;
172 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata;
173 outw(0x0001, ioaddr + BANK_SELECT);
174 outw(0x0001, ioaddr + BANK_SELECT);
175 outw(0x0067, ioaddr + BASE);
176
177 ppdata &= ~0x0080;
178 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata;
179 }
180
181 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180;
182}
183
184#endif
185
186/****************************************************************************/
187#endif /* mcfsmc_h */
diff --git a/arch/m68knommu/include/asm/mcftimer.h b/arch/m68knommu/include/asm/mcftimer.h
new file mode 100644
index 000000000000..0f90f6d2227a
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcftimer.h
@@ -0,0 +1,80 @@
1/****************************************************************************/
2
3/*
4 * mcftimer.h -- ColdFire internal TIMER support defines.
5 *
6 * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef mcftimer_h
12#define mcftimer_h
13/****************************************************************************/
14
15
16/*
17 * Get address specific defines for this ColdFire member.
18 */
19#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
20#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
21#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
22#elif defined(CONFIG_M5272)
23#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
24#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
25#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
26#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
27#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
28#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
29#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
30#elif defined(CONFIG_M532x)
31#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */
32#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */
33#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */
34#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */
35#endif
36
37
38/*
39 * Define the TIMER register set addresses.
40 */
41#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
42#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
43#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
44#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
45#if defined(CONFIG_M532x)
46#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
47#else
48#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
49#endif
50
51/*
52 * Bit definitions for the Timer Mode Register (TMR).
53 * Register bit flags are common accross ColdFires.
54 */
55#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
56#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
57#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
58#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
59#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
60#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
61#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
62#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
63#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
64#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
65#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
66#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
67#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
68#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
69#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
70#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
71#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
72
73/*
74 * Bit definitions for the Timer Event Registers (TER).
75 */
76#define MCFTIMER_TER_CAP 0x01 /* Capture event */
77#define MCFTIMER_TER_REF 0x02 /* Refernece event */
78
79/****************************************************************************/
80#endif /* mcftimer_h */
diff --git a/arch/m68knommu/include/asm/mcfuart.h b/arch/m68knommu/include/asm/mcfuart.h
new file mode 100644
index 000000000000..ef2293873612
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfuart.h
@@ -0,0 +1,216 @@
1/****************************************************************************/
2
3/*
4 * mcfuart.h -- ColdFire internal UART support defines.
5 *
6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef mcfuart_h
12#define mcfuart_h
13/****************************************************************************/
14
15/*
16 * Define the base address of the UARTS within the MBAR address
17 * space.
18 */
19#if defined(CONFIG_M5272)
20#define MCFUART_BASE1 0x100 /* Base address of UART1 */
21#define MCFUART_BASE2 0x140 /* Base address of UART2 */
22#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
23#if defined(CONFIG_NETtel)
24#define MCFUART_BASE1 0x180 /* Base address of UART1 */
25#define MCFUART_BASE2 0x140 /* Base address of UART2 */
26#else
27#define MCFUART_BASE1 0x140 /* Base address of UART1 */
28#define MCFUART_BASE2 0x180 /* Base address of UART2 */
29#endif
30#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
31#define MCFUART_BASE1 0x200 /* Base address of UART1 */
32#define MCFUART_BASE2 0x240 /* Base address of UART2 */
33#define MCFUART_BASE3 0x280 /* Base address of UART3 */
34#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
35#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
36#define MCFUART_BASE1 0x200 /* Base address of UART1 */
37#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
38#else
39#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
40#define MCFUART_BASE2 0x200 /* Base address of UART2 */
41#endif
42#elif defined(CONFIG_M520x)
43#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
44#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
45#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
46#elif defined(CONFIG_M532x)
47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
50#endif
51
52
53#include <linux/serial_core.h>
54#include <linux/platform_device.h>
55
56struct mcf_platform_uart {
57 unsigned long mapbase; /* Physical address base */
58 void __iomem *membase; /* Virtual address if mapped */
59 unsigned int irq; /* Interrupt vector */
60 unsigned int uartclk; /* UART clock rate */
61};
62
63/*
64 * Define the ColdFire UART register set addresses.
65 */
66#define MCFUART_UMR 0x00 /* Mode register (r/w) */
67#define MCFUART_USR 0x04 /* Status register (r) */
68#define MCFUART_UCSR 0x04 /* Clock Select (w) */
69#define MCFUART_UCR 0x08 /* Command register (w) */
70#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
71#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
72#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
73#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
74#define MCFUART_UISR 0x14 /* Interrupt Status (r) */
75#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
76#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
77#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
78#ifdef CONFIG_M5272
79#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
80#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
81#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
82#else
83#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
84#endif
85#define MCFUART_UIPR 0x34 /* Input Port (r) */
86#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
87#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
88
89
90/*
91 * Define bit flags in Mode Register 1 (MR1).
92 */
93#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
94#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
95#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
96#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
97#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
98
99#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
100#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
101#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
102#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
103#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
104
105#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
106#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
107#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
108#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
109
110/*
111 * Define bit flags in Mode Register 2 (MR2).
112 */
113#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
114#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
115#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
116#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
117#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
118
119#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
120#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
121#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
122
123/*
124 * Define bit flags in Status Register (USR).
125 */
126#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
127#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
128#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
129#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
130#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
131#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
132#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
133#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
134
135#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
136 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
137
138/*
139 * Define bit flags in Clock Select Register (UCSR).
140 */
141#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
142#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
143#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
144
145#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
146#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
147#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
148
149/*
150 * Define bit flags in Command Register (UCR).
151 */
152#define MCFUART_UCR_CMDNULL 0x00 /* No command */
153#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
154#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
155#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
156#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
157#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
158#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
159#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
160
161#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
162#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
163#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
164#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
165#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
166#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
167
168/*
169 * Define bit flags in Input Port Change Register (UIPCR).
170 */
171#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
172#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
173
174/*
175 * Define bit flags in Input Port Register (UIP).
176 */
177#define MCFUART_UIPR_CTS 0x01 /* CTS value */
178
179/*
180 * Define bit flags in Output Port Registers (UOP).
181 * Clear bit by writing to UOP0, set by writing to UOP1.
182 */
183#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
184
185/*
186 * Define bit flags in the Auxiliary Control Register (UACR).
187 */
188#define MCFUART_UACR_IEC 0x01 /* Input enable control */
189
190/*
191 * Define bit flags in Interrupt Status Register (UISR).
192 * These same bits are used for the Interrupt Mask Register (UIMR).
193 */
194#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
195#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
196#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
197#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
198
199#ifdef CONFIG_M5272
200/*
201 * Define bit flags in the Transmitter FIFO Register (UTF).
202 */
203#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */
204#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */
205#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */
206
207/*
208 * Define bit flags in the Receiver FIFO Register (URF).
209 */
210#define MCFUART_URF_RXB 0x1f /* Receiver data level */
211#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */
212#define MCFUART_URF_RXS 0xc0 /* Receiver status */
213#endif
214
215/****************************************************************************/
216#endif /* mcfuart_h */
diff --git a/arch/m68knommu/include/asm/mcfwdebug.h b/arch/m68knommu/include/asm/mcfwdebug.h
new file mode 100644
index 000000000000..27f70e45d700
--- /dev/null
+++ b/arch/m68knommu/include/asm/mcfwdebug.h
@@ -0,0 +1,118 @@
1/****************************************************************************/
2
3/*
4 * mcfdebug.h -- ColdFire Debug Module support.
5 *
6 * (C) Copyright 2001, Lineo Inc. (www.lineo.com)
7 */
8
9/****************************************************************************/
10#ifndef mcfdebug_h
11#define mcfdebug_h
12/****************************************************************************/
13
14/* Define the debug module registers */
15#define MCFDEBUG_CSR 0x0 /* Configuration status */
16#define MCFDEBUG_BAAR 0x5 /* BDM address attribute */
17#define MCFDEBUG_AATR 0x6 /* Address attribute trigger */
18#define MCFDEBUG_TDR 0x7 /* Trigger definition */
19#define MCFDEBUG_PBR 0x8 /* PC breakpoint */
20#define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */
21#define MCFDEBUG_ABHR 0xc /* High address breakpoint */
22#define MCFDEBUG_ABLR 0xd /* Low address breakpoint */
23#define MCFDEBUG_DBR 0xe /* Data breakpoint */
24#define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */
25
26/* Define some handy constants for the trigger definition register */
27#define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */
28#define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */
29#define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */
30#define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */
31#define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */
32#define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */
33#define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */
34#define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */
35#define MCFDEBUG_TDR_EDLW2 0x10000000
36#define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */
37#define MCFDEBUG_TDR_EDWL2 0x08000000
38#define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */
39#define MCFDEBUG_TDR_EDWU2 0x04000000
40#define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */
41#define MCFDEBUG_TDR_EDLL2 0x02000000
42#define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */
43#define MCFDEBUG_TDR_EDLM2 0x01000000
44#define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */
45#define MCFDEBUG_TDR_EDUM2 0x00800000
46#define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */
47#define MCFDEBUG_TDR_EDUU2 0x00400000
48#define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */
49#define MCFDEBUG_TDR_DI2 0x00200000
50#define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */
51#define MCFDEBUG_TDR_EAI2 0x00100000
52#define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */
53#define MCFDEBUG_TDR_EAR2 0x00080000
54#define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */
55#define MCFDEBUG_TDR_EAL2 0x00040000
56#define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */
57#define MCFDEBUG_TDR_EPC2 0x00020000
58#define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */
59#define MCFDEBUG_TDR_PCI2 0x00010000
60
61/* Constants for the address attribute trigger register */
62#define MCFDEBUG_AAR_RESET 0x00000005
63/* Fields not yet implemented */
64
65/* And some definitions for the writable sections of the CSR */
66#define MCFDEBUG_CSR_RESET 0x00100000
67#define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */
68#define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */
69#define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */
70#define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */
71#define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */
72#define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */
73#define MCFDEBUG_CSR_DDC_WRITE 0x00001000
74#define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */
75#define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */
76#define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */
77#define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */
78#define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */
79#define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */
80#define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */
81
82/* Constants for the BDM address attribute register */
83#define MCFDEBUG_BAAR_RESET 0x00000005
84/* Fields not yet implemented */
85
86
87/* This routine wrappers up the wdebug asm instruction so that the register
88 * and value can be relatively easily specified. The biggest hassle here is
89 * that the debug module instructions (2 longs) must be long word aligned and
90 * some pointer fiddling is performed to ensure this.
91 */
92static inline void wdebug(int reg, unsigned long data) {
93 unsigned short dbg_spc[6];
94 unsigned short *dbg;
95
96 // Force alignment to long word boundary
97 dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc);
98
99 // Build up the debug instruction
100 dbg[0] = 0x2c80 | (reg & 0xf);
101 dbg[1] = (data >> 16) & 0xffff;
102 dbg[2] = data & 0xffff;
103 dbg[3] = 0;
104
105 // Perform the wdebug instruction
106#if 0
107 // This strain is for gas which doesn't have the wdebug instructions defined
108 asm( "move.l %0, %%a0\n\t"
109 ".word 0xfbd0\n\t"
110 ".word 0x0003\n\t"
111 :: "g" (dbg) : "a0");
112#else
113 // And this is for when it does
114 asm( "wdebug (%0)" :: "a" (dbg));
115#endif
116}
117
118#endif
diff --git a/arch/m68knommu/include/asm/md.h b/arch/m68knommu/include/asm/md.h
new file mode 100644
index 000000000000..d810c78de5ff
--- /dev/null
+++ b/arch/m68knommu/include/asm/md.h
@@ -0,0 +1 @@
#include <asm-m68k/md.h>
diff --git a/arch/m68knommu/include/asm/mman.h b/arch/m68knommu/include/asm/mman.h
new file mode 100644
index 000000000000..4846c682efed
--- /dev/null
+++ b/arch/m68knommu/include/asm/mman.h
@@ -0,0 +1 @@
#include <asm-m68k/mman.h>
diff --git a/arch/m68knommu/include/asm/mmu.h b/arch/m68knommu/include/asm/mmu.h
new file mode 100644
index 000000000000..5fa6b68353ba
--- /dev/null
+++ b/arch/m68knommu/include/asm/mmu.h
@@ -0,0 +1,11 @@
1#ifndef __M68KNOMMU_MMU_H
2#define __M68KNOMMU_MMU_H
3
4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
5
6typedef struct {
7 struct vm_list_struct *vmlist;
8 unsigned long end_brk;
9} mm_context_t;
10
11#endif /* __M68KNOMMU_MMU_H */
diff --git a/arch/m68knommu/include/asm/mmu_context.h b/arch/m68knommu/include/asm/mmu_context.h
new file mode 100644
index 000000000000..9ccee4278c97
--- /dev/null
+++ b/arch/m68knommu/include/asm/mmu_context.h
@@ -0,0 +1,33 @@
1#ifndef __M68KNOMMU_MMU_CONTEXT_H
2#define __M68KNOMMU_MMU_CONTEXT_H
3
4#include <asm/setup.h>
5#include <asm/page.h>
6#include <asm/pgalloc.h>
7#include <asm-generic/mm_hooks.h>
8
9static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
10{
11}
12
13static inline int
14init_new_context(struct task_struct *tsk, struct mm_struct *mm)
15{
16 // mm->context = virt_to_phys(mm->pgd);
17 return(0);
18}
19
20#define destroy_context(mm) do { } while(0)
21
22static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
23{
24}
25
26#define deactivate_mm(tsk,mm) do { } while (0)
27
28static inline void activate_mm(struct mm_struct *prev_mm,
29 struct mm_struct *next_mm)
30{
31}
32
33#endif
diff --git a/arch/m68knommu/include/asm/module.h b/arch/m68knommu/include/asm/module.h
new file mode 100644
index 000000000000..2e45ab50b232
--- /dev/null
+++ b/arch/m68knommu/include/asm/module.h
@@ -0,0 +1,11 @@
1#ifndef ASM_M68KNOMMU_MODULE_H
2#define ASM_M68KNOMMU_MODULE_H
3
4struct mod_arch_specific {
5};
6
7#define Elf_Shdr Elf32_Shdr
8#define Elf_Sym Elf32_Sym
9#define Elf_Ehdr Elf32_Ehdr
10
11#endif /* ASM_M68KNOMMU_MODULE_H */
diff --git a/arch/m68knommu/include/asm/movs.h b/arch/m68knommu/include/asm/movs.h
new file mode 100644
index 000000000000..81a16779e833
--- /dev/null
+++ b/arch/m68knommu/include/asm/movs.h
@@ -0,0 +1 @@
#include <asm-m68k/movs.h>
diff --git a/arch/m68knommu/include/asm/msgbuf.h b/arch/m68knommu/include/asm/msgbuf.h
new file mode 100644
index 000000000000..bdfadec4d52d
--- /dev/null
+++ b/arch/m68knommu/include/asm/msgbuf.h
@@ -0,0 +1 @@
#include <asm-m68k/msgbuf.h>
diff --git a/arch/m68knommu/include/asm/mutex.h b/arch/m68knommu/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/m68knommu/include/asm/mutex.h
@@ -0,0 +1,9 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/arch/m68knommu/include/asm/nettel.h b/arch/m68knommu/include/asm/nettel.h
new file mode 100644
index 000000000000..0299f6a2deeb
--- /dev/null
+++ b/arch/m68knommu/include/asm/nettel.h
@@ -0,0 +1,108 @@
1/****************************************************************************/
2
3/*
4 * nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
5 *
6 * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
7 * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com)
8 * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com)
9 */
10
11/****************************************************************************/
12#ifndef nettel_h
13#define nettel_h
14/****************************************************************************/
15
16
17/****************************************************************************/
18#ifdef CONFIG_NETtel
19/****************************************************************************/
20
21#ifdef CONFIG_COLDFIRE
22#include <asm/coldfire.h>
23#include <asm/mcfsim.h>
24#endif
25
26/*---------------------------------------------------------------------------*/
27#if defined(CONFIG_M5307)
28/*
29 * NETtel/5307 based hardware first. DTR/DCD lines are wired to
30 * GPIO lines. Most of the LED's are driver through a latch
31 * connected to CS2.
32 */
33#define MCFPP_DCD1 0x0001
34#define MCFPP_DCD0 0x0002
35#define MCFPP_DTR1 0x0004
36#define MCFPP_DTR0 0x0008
37
38#define NETtel_LEDADDR 0x30400000
39
40#ifndef __ASSEMBLY__
41
42extern volatile unsigned short ppdata;
43
44/*
45 * These functions defined to give quasi generic access to the
46 * PPIO bits used for DTR/DCD.
47 */
48static __inline__ unsigned int mcf_getppdata(void)
49{
50 volatile unsigned short *pp;
51 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT);
52 return((unsigned int) *pp);
53}
54
55static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
56{
57 volatile unsigned short *pp;
58 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT);
59 ppdata = (ppdata & ~mask) | bits;
60 *pp = ppdata;
61}
62#endif
63
64/*---------------------------------------------------------------------------*/
65#elif defined(CONFIG_M5206e)
66/*
67 * NETtel/5206e based hardware has leds on latch on CS3.
68 * No support modem for lines??
69 */
70#define NETtel_LEDADDR 0x50000000
71
72/*---------------------------------------------------------------------------*/
73#elif defined(CONFIG_M5272)
74/*
75 * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines.
76 */
77#define MCFPP_DCD0 0x0080
78#define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */
79#define MCFPP_DTR0 0x0040
80#define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */
81
82#ifndef __ASSEMBLY__
83/*
84 * These functions defined to give quasi generic access to the
85 * PPIO bits used for DTR/DCD.
86 */
87static __inline__ unsigned int mcf_getppdata(void)
88{
89 volatile unsigned short *pp;
90 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
91 return((unsigned int) *pp);
92}
93
94static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
95{
96 volatile unsigned short *pp;
97 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
98 *pp = (*pp & ~mask) | bits;
99}
100#endif
101
102#endif
103/*---------------------------------------------------------------------------*/
104
105/****************************************************************************/
106#endif /* CONFIG_NETtel */
107/****************************************************************************/
108#endif /* nettel_h */
diff --git a/arch/m68knommu/include/asm/openprom.h b/arch/m68knommu/include/asm/openprom.h
new file mode 100644
index 000000000000..fdba7953ff9f
--- /dev/null
+++ b/arch/m68knommu/include/asm/openprom.h
@@ -0,0 +1 @@
#include <asm-m68k/openprom.h>
diff --git a/arch/m68knommu/include/asm/oplib.h b/arch/m68knommu/include/asm/oplib.h
new file mode 100644
index 000000000000..ce079dc332d9
--- /dev/null
+++ b/arch/m68knommu/include/asm/oplib.h
@@ -0,0 +1 @@
#include <asm-m68k/oplib.h>
diff --git a/arch/m68knommu/include/asm/page.h b/arch/m68knommu/include/asm/page.h
new file mode 100644
index 000000000000..3a1ede4544cb
--- /dev/null
+++ b/arch/m68knommu/include/asm/page.h
@@ -0,0 +1,77 @@
1#ifndef _M68KNOMMU_PAGE_H
2#define _M68KNOMMU_PAGE_H
3
4/* PAGE_SHIFT determines the page size */
5
6#define PAGE_SHIFT (12)
7#define PAGE_SIZE (1UL << PAGE_SHIFT)
8#define PAGE_MASK (~(PAGE_SIZE-1))
9
10#include <asm/setup.h>
11
12#ifndef __ASSEMBLY__
13
14#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
15#define free_user_page(page, addr) free_page(addr)
16
17#define clear_page(page) memset((page), 0, PAGE_SIZE)
18#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
19
20#define clear_user_page(page, vaddr, pg) clear_page(page)
21#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
22
23#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
24 alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
25#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
26
27/*
28 * These are used to make use of C type-checking..
29 */
30typedef struct { unsigned long pte; } pte_t;
31typedef struct { unsigned long pmd[16]; } pmd_t;
32typedef struct { unsigned long pgd; } pgd_t;
33typedef struct { unsigned long pgprot; } pgprot_t;
34typedef struct page *pgtable_t;
35
36#define pte_val(x) ((x).pte)
37#define pmd_val(x) ((&x)->pmd[0])
38#define pgd_val(x) ((x).pgd)
39#define pgprot_val(x) ((x).pgprot)
40
41#define __pte(x) ((pte_t) { (x) } )
42#define __pmd(x) ((pmd_t) { (x) } )
43#define __pgd(x) ((pgd_t) { (x) } )
44#define __pgprot(x) ((pgprot_t) { (x) } )
45
46extern unsigned long memory_start;
47extern unsigned long memory_end;
48
49#endif /* !__ASSEMBLY__ */
50
51#include <asm/page_offset.h>
52
53#define PAGE_OFFSET (PAGE_OFFSET_RAW)
54
55#ifndef __ASSEMBLY__
56
57#define __pa(vaddr) virt_to_phys((void *)(vaddr))
58#define __va(paddr) phys_to_virt((unsigned long)(paddr))
59
60#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
61#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
62
63#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
64#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
65
66#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
67#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
68#define pfn_valid(pfn) ((pfn) < max_mapnr)
69
70#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
71 ((void *)(kaddr) < (void *)memory_end))
72
73#endif /* __ASSEMBLY__ */
74
75#include <asm-generic/page.h>
76
77#endif /* _M68KNOMMU_PAGE_H */
diff --git a/arch/m68knommu/include/asm/page_offset.h b/arch/m68knommu/include/asm/page_offset.h
new file mode 100644
index 000000000000..d4e73e0ba646
--- /dev/null
+++ b/arch/m68knommu/include/asm/page_offset.h
@@ -0,0 +1,5 @@
1
2
3/* This handles the memory map.. */
4#define PAGE_OFFSET_RAW CONFIG_RAMBASE
5
diff --git a/arch/m68knommu/include/asm/param.h b/arch/m68knommu/include/asm/param.h
new file mode 100644
index 000000000000..6044397adb64
--- /dev/null
+++ b/arch/m68knommu/include/asm/param.h
@@ -0,0 +1,22 @@
1#ifndef _M68KNOMMU_PARAM_H
2#define _M68KNOMMU_PARAM_H
3
4#ifdef __KERNEL__
5#define HZ CONFIG_HZ
6#define USER_HZ HZ
7#define CLOCKS_PER_SEC (USER_HZ)
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* _M68KNOMMU_PARAM_H */
diff --git a/arch/m68knommu/include/asm/pci.h b/arch/m68knommu/include/asm/pci.h
new file mode 100644
index 000000000000..a13f3cc87451
--- /dev/null
+++ b/arch/m68knommu/include/asm/pci.h
@@ -0,0 +1,29 @@
1#ifndef M68KNOMMU_PCI_H
2#define M68KNOMMU_PCI_H
3
4#include <asm-m68k/pci.h>
5
6#ifdef CONFIG_COMEMPCI
7/*
8 * These are pretty much arbitary with the CoMEM implementation.
9 * We have the whole address space to ourselves.
10 */
11#define PCIBIOS_MIN_IO 0x100
12#define PCIBIOS_MIN_MEM 0x00010000
13
14#define pcibios_scan_all_fns(a, b) 0
15
16/*
17 * Return whether the given PCI device DMA address mask can
18 * be supported properly. For example, if your device can
19 * only drive the low 24-bits during PCI bus mastering, then
20 * you would pass 0x00ffffff as the mask to this function.
21 */
22static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
23{
24 return 1;
25}
26
27#endif /* CONFIG_COMEMPCI */
28
29#endif /* M68KNOMMU_PCI_H */
diff --git a/arch/m68knommu/include/asm/percpu.h b/arch/m68knommu/include/asm/percpu.h
new file mode 100644
index 000000000000..5de72c327efd
--- /dev/null
+++ b/arch/m68knommu/include/asm/percpu.h
@@ -0,0 +1,6 @@
1#ifndef __ARCH_M68KNOMMU_PERCPU__
2#define __ARCH_M68KNOMMU_PERCPU__
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ARCH_M68KNOMMU_PERCPU__ */
diff --git a/arch/m68knommu/include/asm/pgalloc.h b/arch/m68knommu/include/asm/pgalloc.h
new file mode 100644
index 000000000000..d6352f671ec0
--- /dev/null
+++ b/arch/m68knommu/include/asm/pgalloc.h
@@ -0,0 +1,8 @@
1#ifndef _M68KNOMMU_PGALLOC_H
2#define _M68KNOMMU_PGALLOC_H
3
4#include <asm/setup.h>
5
6#define check_pgt_cache() do { } while (0)
7
8#endif /* _M68KNOMMU_PGALLOC_H */
diff --git a/arch/m68knommu/include/asm/pgtable.h b/arch/m68knommu/include/asm/pgtable.h
new file mode 100644
index 000000000000..46251016e821
--- /dev/null
+++ b/arch/m68knommu/include/asm/pgtable.h
@@ -0,0 +1,70 @@
1#ifndef _M68KNOMMU_PGTABLE_H
2#define _M68KNOMMU_PGTABLE_H
3
4#include <asm-generic/4level-fixup.h>
5
6/*
7 * (C) Copyright 2000-2002, Greg Ungerer <gerg@snapgear.com>
8 */
9
10#include <linux/slab.h>
11#include <asm/processor.h>
12#include <asm/page.h>
13#include <asm/io.h>
14
15/*
16 * Trivial page table functions.
17 */
18#define pgd_present(pgd) (1)
19#define pgd_none(pgd) (0)
20#define pgd_bad(pgd) (0)
21#define pgd_clear(pgdp)
22#define kern_addr_valid(addr) (1)
23#define pmd_offset(a, b) ((void *)0)
24
25#define PAGE_NONE __pgprot(0)
26#define PAGE_SHARED __pgprot(0)
27#define PAGE_COPY __pgprot(0)
28#define PAGE_READONLY __pgprot(0)
29#define PAGE_KERNEL __pgprot(0)
30
31extern void paging_init(void);
32#define swapper_pg_dir ((pgd_t *) 0)
33
34#define __swp_type(x) (0)
35#define __swp_offset(x) (0)
36#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
37#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
38#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
39
40static inline int pte_file(pte_t pte) { return 0; }
41
42/*
43 * ZERO_PAGE is a global shared page that is always zero: used
44 * for zero-mapped memory areas etc..
45 */
46#define ZERO_PAGE(vaddr) (virt_to_page(0))
47
48/*
49 * These would be in other places but having them here reduces the diffs.
50 */
51extern unsigned int kobjsize(const void *objp);
52
53/*
54 * No page table caches to initialise.
55 */
56#define pgtable_cache_init() do { } while (0)
57
58#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
59 remap_pfn_range(vma, vaddr, pfn, size, prot)
60
61/*
62 * All 32bit addresses are effectively valid for vmalloc...
63 * Sort of meaningless for non-VM targets.
64 */
65#define VMALLOC_START 0
66#define VMALLOC_END 0xffffffff
67
68#include <asm-generic/pgtable.h>
69
70#endif /* _M68KNOMMU_PGTABLE_H */
diff --git a/arch/m68knommu/include/asm/poll.h b/arch/m68knommu/include/asm/poll.h
new file mode 100644
index 000000000000..ee1b6cb549ca
--- /dev/null
+++ b/arch/m68knommu/include/asm/poll.h
@@ -0,0 +1 @@
#include <asm-m68k/poll.h>
diff --git a/arch/m68knommu/include/asm/posix_types.h b/arch/m68knommu/include/asm/posix_types.h
new file mode 100644
index 000000000000..6205fb9392a3
--- /dev/null
+++ b/arch/m68knommu/include/asm/posix_types.h
@@ -0,0 +1 @@
#include <asm-m68k/posix_types.h>
diff --git a/arch/m68knommu/include/asm/processor.h b/arch/m68knommu/include/asm/processor.h
new file mode 100644
index 000000000000..91cba18acdd3
--- /dev/null
+++ b/arch/m68knommu/include/asm/processor.h
@@ -0,0 +1,143 @@
1/*
2 * include/asm-m68knommu/processor.h
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 */
6
7#ifndef __ASM_M68K_PROCESSOR_H
8#define __ASM_M68K_PROCESSOR_H
9
10/*
11 * Default implementation of macro that returns current
12 * instruction pointer ("program counter").
13 */
14#define current_text_addr() ({ __label__ _l; _l: &&_l;})
15
16#include <linux/compiler.h>
17#include <linux/threads.h>
18#include <asm/types.h>
19#include <asm/segment.h>
20#include <asm/fpu.h>
21#include <asm/ptrace.h>
22#include <asm/current.h>
23
24static inline unsigned long rdusp(void)
25{
26#ifdef CONFIG_COLDFIRE
27 extern unsigned int sw_usp;
28 return(sw_usp);
29#else
30 unsigned long usp;
31 __asm__ __volatile__("move %/usp,%0" : "=a" (usp));
32 return usp;
33#endif
34}
35
36static inline void wrusp(unsigned long usp)
37{
38#ifdef CONFIG_COLDFIRE
39 extern unsigned int sw_usp;
40 sw_usp = usp;
41#else
42 __asm__ __volatile__("move %0,%/usp" : : "a" (usp));
43#endif
44}
45
46/*
47 * User space process size: 3.75GB. This is hardcoded into a few places,
48 * so don't change it unless you know what you are doing.
49 */
50#define TASK_SIZE (0xF0000000UL)
51
52/*
53 * This decides where the kernel will search for a free chunk of vm
54 * space during mmap's. We won't be using it
55 */
56#define TASK_UNMAPPED_BASE 0
57
58/*
59 * if you change this structure, you must change the code and offsets
60 * in m68k/machasm.S
61 */
62
63struct thread_struct {
64 unsigned long ksp; /* kernel stack pointer */
65 unsigned long usp; /* user stack pointer */
66 unsigned short sr; /* saved status register */
67 unsigned short fs; /* saved fs (sfc, dfc) */
68 unsigned long crp[2]; /* cpu root pointer */
69 unsigned long esp0; /* points to SR of stack frame */
70 unsigned long fp[8*3];
71 unsigned long fpcntl[3]; /* fp control regs */
72 unsigned char fpstate[FPSTATESIZE]; /* floating point state */
73};
74
75#define INIT_THREAD { \
76 sizeof(init_stack) + (unsigned long) init_stack, 0, \
77 PS_S, __KERNEL_DS, \
78 {0, 0}, 0, {0,}, {0, 0, 0}, {0,}, \
79}
80
81/*
82 * Coldfire stacks need to be re-aligned on trap exit, conventional
83 * 68k can handle this case cleanly.
84 */
85#if defined(CONFIG_COLDFIRE)
86#define reformat(_regs) do { (_regs)->format = 0x4; } while(0)
87#else
88#define reformat(_regs) do { } while (0)
89#endif
90
91/*
92 * Do necessary setup to start up a newly executed thread.
93 *
94 * pass the data segment into user programs if it exists,
95 * it can't hurt anything as far as I can tell
96 */
97#define start_thread(_regs, _pc, _usp) \
98do { \
99 set_fs(USER_DS); /* reads from user space */ \
100 (_regs)->pc = (_pc); \
101 ((struct switch_stack *)(_regs))[-1].a6 = 0; \
102 reformat(_regs); \
103 if (current->mm) \
104 (_regs)->d5 = current->mm->start_data; \
105 (_regs)->sr &= ~0x2000; \
106 wrusp(_usp); \
107} while(0)
108
109/* Forward declaration, a strange C thing */
110struct task_struct;
111
112/* Free all resources held by a thread. */
113static inline void release_thread(struct task_struct *dead_task)
114{
115}
116
117/* Prepare to copy thread state - unlazy all lazy status */
118#define prepare_to_copy(tsk) do { } while (0)
119
120extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
121
122/*
123 * Free current thread data structures etc..
124 */
125static inline void exit_thread(void)
126{
127}
128
129unsigned long thread_saved_pc(struct task_struct *tsk);
130unsigned long get_wchan(struct task_struct *p);
131
132#define KSTK_EIP(tsk) \
133 ({ \
134 unsigned long eip = 0; \
135 if ((tsk)->thread.esp0 > PAGE_SIZE && \
136 (virt_addr_valid((tsk)->thread.esp0))) \
137 eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
138 eip; })
139#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
140
141#define cpu_relax() barrier()
142
143#endif
diff --git a/arch/m68knommu/include/asm/ptrace.h b/arch/m68knommu/include/asm/ptrace.h
new file mode 100644
index 000000000000..8c9194b98548
--- /dev/null
+++ b/arch/m68knommu/include/asm/ptrace.h
@@ -0,0 +1,87 @@
1#ifndef _M68K_PTRACE_H
2#define _M68K_PTRACE_H
3
4#define PT_D1 0
5#define PT_D2 1
6#define PT_D3 2
7#define PT_D4 3
8#define PT_D5 4
9#define PT_D6 5
10#define PT_D7 6
11#define PT_A0 7
12#define PT_A1 8
13#define PT_A2 9
14#define PT_A3 10
15#define PT_A4 11
16#define PT_A5 12
17#define PT_A6 13
18#define PT_D0 14
19#define PT_USP 15
20#define PT_ORIG_D0 16
21#define PT_SR 17
22#define PT_PC 18
23
24#ifndef __ASSEMBLY__
25
26/* this struct defines the way the registers are stored on the
27 stack during a system call. */
28
29struct pt_regs {
30 long d1;
31 long d2;
32 long d3;
33 long d4;
34 long d5;
35 long a0;
36 long a1;
37 long a2;
38 long d0;
39 long orig_d0;
40 long stkadj;
41#ifdef CONFIG_COLDFIRE
42 unsigned format : 4; /* frame format specifier */
43 unsigned vector : 12; /* vector offset */
44 unsigned short sr;
45 unsigned long pc;
46#else
47 unsigned short sr;
48 unsigned long pc;
49 unsigned format : 4; /* frame format specifier */
50 unsigned vector : 12; /* vector offset */
51#endif
52};
53
54/*
55 * This is the extended stack used by signal handlers and the context
56 * switcher: it's pushed after the normal "struct pt_regs".
57 */
58struct switch_stack {
59 unsigned long d6;
60 unsigned long d7;
61 unsigned long a3;
62 unsigned long a4;
63 unsigned long a5;
64 unsigned long a6;
65 unsigned long retpc;
66};
67
68/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
69#define PTRACE_GETREGS 12
70#define PTRACE_SETREGS 13
71#define PTRACE_GETFPREGS 14
72#define PTRACE_SETFPREGS 15
73
74#ifdef __KERNEL__
75
76#ifndef PS_S
77#define PS_S (0x2000)
78#define PS_M (0x1000)
79#endif
80
81#define user_mode(regs) (!((regs)->sr & PS_S))
82#define instruction_pointer(regs) ((regs)->pc)
83#define profile_pc(regs) instruction_pointer(regs)
84extern void show_regs(struct pt_regs *);
85#endif /* __KERNEL__ */
86#endif /* __ASSEMBLY__ */
87#endif /* _M68K_PTRACE_H */
diff --git a/arch/m68knommu/include/asm/quicc_simple.h b/arch/m68knommu/include/asm/quicc_simple.h
new file mode 100644
index 000000000000..c3636932d4bc
--- /dev/null
+++ b/arch/m68knommu/include/asm/quicc_simple.h
@@ -0,0 +1,52 @@
1/***********************************
2 * $Id: quicc_simple.h,v 1.1 2002/03/02 15:01:10 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Simple drivers common header
7 ***************************************
8 */
9
10#ifndef __SIMPLE_H
11#define __SIMPLE_H
12
13/* #include "quicc.h" */
14
15#define GLB_SCC_0 0
16#define GLB_SCC_1 1
17#define GLB_SCC_2 2
18#define GLB_SCC_3 3
19
20typedef void (int_routine)(unsigned short interrupt_event);
21typedef int_routine *int_routine_ptr;
22typedef void *(alloc_routine)(int length);
23typedef void (free_routine)(int scc_num, int channel_num, void *buf);
24typedef void (store_rx_buffer_routine)(int scc_num, int channel_num, void *buff, int length);
25typedef int (handle_tx_error_routine)(int scc_num, int channel_num, QUICC_BD *tbd);
26typedef void (handle_rx_error_routine)(int scc_num, int channel_num, QUICC_BD *rbd);
27typedef void (handle_lost_error_routine)(int scc_num, int channel_num);
28
29/* user defined functions for global errors */
30typedef void (handle_glob_overrun_routine)(int scc_number);
31typedef void (handle_glob_underrun_routine)(int scc_number);
32typedef void (glob_intr_q_overflow_routine)(int scc_number);
33
34/*
35 * General initialization and command routines
36 */
37void quicc_issue_cmd (unsigned short cmd, int scc_num);
38void quicc_init(void);
39void quicc_scc_init(int scc_number, int number_of_rx_buf, int number_of_tx_buf);
40void quicc_smc_init(int smc_number, int number_of_rx_buf, int number_of_tx_buf);
41void quicc_scc_start(int scc_num);
42void quicc_scc_loopback(int scc_num);
43
44/* Interrupt enable/disable routines for critical pieces of code*/
45unsigned short IntrDis(void);
46void IntrEna(unsigned short old_sr);
47
48/* For debugging */
49void print_rbd(int scc_num);
50void print_tbd(int scc_num);
51
52#endif
diff --git a/arch/m68knommu/include/asm/resource.h b/arch/m68knommu/include/asm/resource.h
new file mode 100644
index 000000000000..7fa63d5ea576
--- /dev/null
+++ b/arch/m68knommu/include/asm/resource.h
@@ -0,0 +1 @@
#include <asm-m68k/resource.h>
diff --git a/arch/m68knommu/include/asm/rtc.h b/arch/m68knommu/include/asm/rtc.h
new file mode 100644
index 000000000000..eaf18ec83c8e
--- /dev/null
+++ b/arch/m68knommu/include/asm/rtc.h
@@ -0,0 +1 @@
#include <asm-m68k/rtc.h>
diff --git a/arch/m68knommu/include/asm/scatterlist.h b/arch/m68knommu/include/asm/scatterlist.h
new file mode 100644
index 000000000000..afc4788b0d2c
--- /dev/null
+++ b/arch/m68knommu/include/asm/scatterlist.h
@@ -0,0 +1,22 @@
1#ifndef _M68KNOMMU_SCATTERLIST_H
2#define _M68KNOMMU_SCATTERLIST_H
3
4#include <linux/mm.h>
5#include <asm/types.h>
6
7struct scatterlist {
8#ifdef CONFIG_DEBUG_SG
9 unsigned long sg_magic;
10#endif
11 unsigned long page_link;
12 unsigned int offset;
13 dma_addr_t dma_address;
14 unsigned int length;
15};
16
17#define sg_dma_address(sg) ((sg)->dma_address)
18#define sg_dma_len(sg) ((sg)->length)
19
20#define ISA_DMA_THRESHOLD (0xffffffff)
21
22#endif /* !(_M68KNOMMU_SCATTERLIST_H) */
diff --git a/arch/m68knommu/include/asm/sections.h b/arch/m68knommu/include/asm/sections.h
new file mode 100644
index 000000000000..dd0ecb98ec08
--- /dev/null
+++ b/arch/m68knommu/include/asm/sections.h
@@ -0,0 +1,7 @@
1#ifndef _M68KNOMMU_SECTIONS_H
2#define _M68KNOMMU_SECTIONS_H
3
4/* nothing to see, move along */
5#include <asm-generic/sections.h>
6
7#endif
diff --git a/arch/m68knommu/include/asm/segment.h b/arch/m68knommu/include/asm/segment.h
new file mode 100644
index 000000000000..42318ebec7ec
--- /dev/null
+++ b/arch/m68knommu/include/asm/segment.h
@@ -0,0 +1,51 @@
1#ifndef _M68K_SEGMENT_H
2#define _M68K_SEGMENT_H
3
4/* define constants */
5/* Address spaces (FC0-FC2) */
6#define USER_DATA (1)
7#ifndef __USER_DS
8#define __USER_DS (USER_DATA)
9#endif
10#define USER_PROGRAM (2)
11#define SUPER_DATA (5)
12#ifndef __KERNEL_DS
13#define __KERNEL_DS (SUPER_DATA)
14#endif
15#define SUPER_PROGRAM (6)
16#define CPU_SPACE (7)
17
18#ifndef __ASSEMBLY__
19
20typedef struct {
21 unsigned long seg;
22} mm_segment_t;
23
24#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
25#define USER_DS MAKE_MM_SEG(__USER_DS)
26#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS)
27
28/*
29 * Get/set the SFC/DFC registers for MOVES instructions
30 */
31
32static inline mm_segment_t get_fs(void)
33{
34 return USER_DS;
35}
36
37static inline mm_segment_t get_ds(void)
38{
39 /* return the supervisor data space code */
40 return KERNEL_DS;
41}
42
43static inline void set_fs(mm_segment_t val)
44{
45}
46
47#define segment_eq(a,b) ((a).seg == (b).seg)
48
49#endif /* __ASSEMBLY__ */
50
51#endif /* _M68K_SEGMENT_H */
diff --git a/arch/m68knommu/include/asm/sembuf.h b/arch/m68knommu/include/asm/sembuf.h
new file mode 100644
index 000000000000..3a634f9ecf50
--- /dev/null
+++ b/arch/m68knommu/include/asm/sembuf.h
@@ -0,0 +1 @@
#include <asm-m68k/sembuf.h>
diff --git a/arch/m68knommu/include/asm/setup.h b/arch/m68knommu/include/asm/setup.h
new file mode 100644
index 000000000000..fb86bb2a6078
--- /dev/null
+++ b/arch/m68knommu/include/asm/setup.h
@@ -0,0 +1,10 @@
1#ifdef __KERNEL__
2
3#include <asm-m68k/setup.h>
4
5/* We have a bigger command line buffer. */
6#undef COMMAND_LINE_SIZE
7
8#endif /* __KERNEL__ */
9
10#define COMMAND_LINE_SIZE 512
diff --git a/arch/m68knommu/include/asm/shm.h b/arch/m68knommu/include/asm/shm.h
new file mode 100644
index 000000000000..cc8e522d9050
--- /dev/null
+++ b/arch/m68knommu/include/asm/shm.h
@@ -0,0 +1 @@
#include <asm-m68k/shm.h>
diff --git a/arch/m68knommu/include/asm/shmbuf.h b/arch/m68knommu/include/asm/shmbuf.h
new file mode 100644
index 000000000000..bc34cf8eefce
--- /dev/null
+++ b/arch/m68knommu/include/asm/shmbuf.h
@@ -0,0 +1 @@
#include <asm-m68k/shmbuf.h>
diff --git a/arch/m68knommu/include/asm/shmparam.h b/arch/m68knommu/include/asm/shmparam.h
new file mode 100644
index 000000000000..d7ee69648ebf
--- /dev/null
+++ b/arch/m68knommu/include/asm/shmparam.h
@@ -0,0 +1 @@
#include <asm-m68k/shmparam.h>
diff --git a/arch/m68knommu/include/asm/sigcontext.h b/arch/m68knommu/include/asm/sigcontext.h
new file mode 100644
index 000000000000..36c293fc133d
--- /dev/null
+++ b/arch/m68knommu/include/asm/sigcontext.h
@@ -0,0 +1,17 @@
1#ifndef _ASM_M68KNOMMU_SIGCONTEXT_H
2#define _ASM_M68KNOMMU_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long sc_mask; /* old sigmask */
6 unsigned long sc_usp; /* old user stack pointer */
7 unsigned long sc_d0;
8 unsigned long sc_d1;
9 unsigned long sc_a0;
10 unsigned long sc_a1;
11 unsigned long sc_a5;
12 unsigned short sc_sr;
13 unsigned long sc_pc;
14 unsigned short sc_formatvec;
15};
16
17#endif
diff --git a/arch/m68knommu/include/asm/siginfo.h b/arch/m68knommu/include/asm/siginfo.h
new file mode 100644
index 000000000000..b18e5f4064ae
--- /dev/null
+++ b/arch/m68knommu/include/asm/siginfo.h
@@ -0,0 +1,6 @@
1#ifndef _M68KNOMMU_SIGINFO_H
2#define _M68KNOMMU_SIGINFO_H
3
4#include <asm-generic/siginfo.h>
5
6#endif
diff --git a/arch/m68knommu/include/asm/signal.h b/arch/m68knommu/include/asm/signal.h
new file mode 100644
index 000000000000..216c08be54a0
--- /dev/null
+++ b/arch/m68knommu/include/asm/signal.h
@@ -0,0 +1,159 @@
1#ifndef _M68KNOMMU_SIGNAL_H
2#define _M68KNOMMU_SIGNAL_H
3
4#include <linux/types.h>
5
6/* Avoid too many header ordering problems. */
7struct siginfo;
8
9#ifdef __KERNEL__
10/* Most things should be clean enough to redefine this at will, if care
11 is taken to make libc match. */
12
13#define _NSIG 64
14#define _NSIG_BPW 32
15#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
16
17typedef unsigned long old_sigset_t; /* at least 32 bits */
18
19typedef struct {
20 unsigned long sig[_NSIG_WORDS];
21} sigset_t;
22
23#else
24/* Here we must cater to libcs that poke about in kernel headers. */
25
26#define NSIG 32
27typedef unsigned long sigset_t;
28
29#endif /* __KERNEL__ */
30
31#define SIGHUP 1
32#define SIGINT 2
33#define SIGQUIT 3
34#define SIGILL 4
35#define SIGTRAP 5
36#define SIGABRT 6
37#define SIGIOT 6
38#define SIGBUS 7
39#define SIGFPE 8
40#define SIGKILL 9
41#define SIGUSR1 10
42#define SIGSEGV 11
43#define SIGUSR2 12
44#define SIGPIPE 13
45#define SIGALRM 14
46#define SIGTERM 15
47#define SIGSTKFLT 16
48#define SIGCHLD 17
49#define SIGCONT 18
50#define SIGSTOP 19
51#define SIGTSTP 20
52#define SIGTTIN 21
53#define SIGTTOU 22
54#define SIGURG 23
55#define SIGXCPU 24
56#define SIGXFSZ 25
57#define SIGVTALRM 26
58#define SIGPROF 27
59#define SIGWINCH 28
60#define SIGIO 29
61#define SIGPOLL SIGIO
62/*
63#define SIGLOST 29
64*/
65#define SIGPWR 30
66#define SIGSYS 31
67#define SIGUNUSED 31
68
69/* These should not be considered constants from userland. */
70#define SIGRTMIN 32
71#define SIGRTMAX _NSIG
72
73/*
74 * SA_FLAGS values:
75 *
76 * SA_ONSTACK indicates that a registered stack_t will be used.
77 * SA_RESTART flag to get restarting signals (which were the default long ago)
78 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
79 * SA_RESETHAND clears the handler when the signal is delivered.
80 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
81 * SA_NODEFER prevents the current signal from being masked in the handler.
82 *
83 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
84 * Unix names RESETHAND and NODEFER respectively.
85 */
86#define SA_NOCLDSTOP 0x00000001
87#define SA_NOCLDWAIT 0x00000002
88#define SA_SIGINFO 0x00000004
89#define SA_ONSTACK 0x08000000
90#define SA_RESTART 0x10000000
91#define SA_NODEFER 0x40000000
92#define SA_RESETHAND 0x80000000
93
94#define SA_NOMASK SA_NODEFER
95#define SA_ONESHOT SA_RESETHAND
96
97/*
98 * sigaltstack controls
99 */
100#define SS_ONSTACK 1
101#define SS_DISABLE 2
102
103#define MINSIGSTKSZ 2048
104#define SIGSTKSZ 8192
105
106#include <asm-generic/signal.h>
107
108#ifdef __KERNEL__
109struct old_sigaction {
110 __sighandler_t sa_handler;
111 old_sigset_t sa_mask;
112 unsigned long sa_flags;
113 void (*sa_restorer)(void);
114};
115
116struct sigaction {
117 __sighandler_t sa_handler;
118 unsigned long sa_flags;
119 void (*sa_restorer)(void);
120 sigset_t sa_mask; /* mask last for extensibility */
121};
122
123struct k_sigaction {
124 struct sigaction sa;
125};
126#else
127/* Here we must cater to libcs that poke about in kernel headers. */
128
129struct sigaction {
130 union {
131 __sighandler_t _sa_handler;
132 void (*_sa_sigaction)(int, struct siginfo *, void *);
133 } _u;
134 sigset_t sa_mask;
135 unsigned long sa_flags;
136 void (*sa_restorer)(void);
137};
138
139#define sa_handler _u._sa_handler
140#define sa_sigaction _u._sa_sigaction
141
142#endif /* __KERNEL__ */
143
144typedef struct sigaltstack {
145 void *ss_sp;
146 int ss_flags;
147 size_t ss_size;
148} stack_t;
149
150#ifdef __KERNEL__
151
152#include <asm/sigcontext.h>
153#undef __HAVE_ARCH_SIG_BITOPS
154
155#define ptrace_signal_deliver(regs, cookie) do { } while (0)
156
157#endif /* __KERNEL__ */
158
159#endif /* _M68KNOMMU_SIGNAL_H */
diff --git a/arch/m68knommu/include/asm/smp.h b/arch/m68knommu/include/asm/smp.h
new file mode 100644
index 000000000000..9e9bd7e58922
--- /dev/null
+++ b/arch/m68knommu/include/asm/smp.h
@@ -0,0 +1 @@
/* nothing required here yet */
diff --git a/arch/m68knommu/include/asm/socket.h b/arch/m68knommu/include/asm/socket.h
new file mode 100644
index 000000000000..ac5478bf6371
--- /dev/null
+++ b/arch/m68knommu/include/asm/socket.h
@@ -0,0 +1 @@
#include <asm-m68k/socket.h>
diff --git a/arch/m68knommu/include/asm/sockios.h b/arch/m68knommu/include/asm/sockios.h
new file mode 100644
index 000000000000..dcc6a8900ce2
--- /dev/null
+++ b/arch/m68knommu/include/asm/sockios.h
@@ -0,0 +1 @@
#include <asm-m68k/sockios.h>
diff --git a/arch/m68knommu/include/asm/spinlock.h b/arch/m68knommu/include/asm/spinlock.h
new file mode 100644
index 000000000000..6bb1f06c4781
--- /dev/null
+++ b/arch/m68knommu/include/asm/spinlock.h
@@ -0,0 +1 @@
#include <asm-m68k/spinlock.h>
diff --git a/arch/m68knommu/include/asm/stat.h b/arch/m68knommu/include/asm/stat.h
new file mode 100644
index 000000000000..3d4b260e7c03
--- /dev/null
+++ b/arch/m68knommu/include/asm/stat.h
@@ -0,0 +1 @@
#include <asm-m68k/stat.h>
diff --git a/arch/m68knommu/include/asm/statfs.h b/arch/m68knommu/include/asm/statfs.h
new file mode 100644
index 000000000000..2ce99eaf0970
--- /dev/null
+++ b/arch/m68knommu/include/asm/statfs.h
@@ -0,0 +1 @@
#include <asm-m68k/statfs.h>
diff --git a/arch/m68knommu/include/asm/string.h b/arch/m68knommu/include/asm/string.h
new file mode 100644
index 000000000000..af09e17000fc
--- /dev/null
+++ b/arch/m68knommu/include/asm/string.h
@@ -0,0 +1,126 @@
1#ifndef _M68KNOMMU_STRING_H_
2#define _M68KNOMMU_STRING_H_
3
4#ifdef __KERNEL__ /* only set these up for kernel code */
5
6#include <asm/setup.h>
7#include <asm/page.h>
8
9#define __HAVE_ARCH_STRCPY
10static inline char * strcpy(char * dest,const char *src)
11{
12 char *xdest = dest;
13
14 __asm__ __volatile__
15 ("1:\tmoveb %1@+,%0@+\n\t"
16 "jne 1b"
17 : "=a" (dest), "=a" (src)
18 : "0" (dest), "1" (src) : "memory");
19 return xdest;
20}
21
22#define __HAVE_ARCH_STRNCPY
23static inline char * strncpy(char *dest, const char *src, size_t n)
24{
25 char *xdest = dest;
26
27 if (n == 0)
28 return xdest;
29
30 __asm__ __volatile__
31 ("1:\tmoveb %1@+,%0@+\n\t"
32 "jeq 2f\n\t"
33 "subql #1,%2\n\t"
34 "jne 1b\n\t"
35 "2:"
36 : "=a" (dest), "=a" (src), "=d" (n)
37 : "0" (dest), "1" (src), "2" (n)
38 : "memory");
39 return xdest;
40}
41
42
43#ifndef CONFIG_COLDFIRE
44
45#define __HAVE_ARCH_STRCMP
46static inline int strcmp(const char * cs,const char * ct)
47{
48 char __res;
49
50 __asm__
51 ("1:\tmoveb %0@+,%2\n\t" /* get *cs */
52 "cmpb %1@+,%2\n\t" /* compare a byte */
53 "jne 2f\n\t" /* not equal, break out */
54 "tstb %2\n\t" /* at end of cs? */
55 "jne 1b\n\t" /* no, keep going */
56 "jra 3f\n\t" /* strings are equal */
57 "2:\tsubb %1@-,%2\n\t" /* *cs - *ct */
58 "3:"
59 : "=a" (cs), "=a" (ct), "=d" (__res)
60 : "0" (cs), "1" (ct));
61
62 return __res;
63}
64
65#define __HAVE_ARCH_STRNCMP
66static inline int strncmp(const char * cs,const char * ct,size_t count)
67{
68 char __res;
69
70 if (!count)
71 return 0;
72 __asm__
73 ("1:\tmovb %0@+,%3\n\t" /* get *cs */
74 "cmpb %1@+,%3\n\t" /* compare a byte */
75 "jne 3f\n\t" /* not equal, break out */
76 "tstb %3\n\t" /* at end of cs? */
77 "jeq 4f\n\t" /* yes, all done */
78 "subql #1,%2\n\t" /* no, adjust count */
79 "jne 1b\n\t" /* more to do, keep going */
80 "2:\tmoveq #0,%3\n\t" /* strings are equal */
81 "jra 4f\n\t"
82 "3:\tsubb %1@-,%3\n\t" /* *cs - *ct */
83 "4:"
84 : "=a" (cs), "=a" (ct), "=d" (count), "=d" (__res)
85 : "0" (cs), "1" (ct), "2" (count));
86 return __res;
87}
88
89#endif /* CONFIG_COLDFIRE */
90
91#define __HAVE_ARCH_MEMSET
92extern void * memset(void * s, int c, size_t count);
93
94#define __HAVE_ARCH_MEMCPY
95extern void * memcpy(void *d, const void *s, size_t count);
96
97#else /* KERNEL */
98
99/*
100 * let user libraries deal with these,
101 * IMHO the kernel has no place defining these functions for user apps
102 */
103
104#define __HAVE_ARCH_STRCPY 1
105#define __HAVE_ARCH_STRNCPY 1
106#define __HAVE_ARCH_STRCAT 1
107#define __HAVE_ARCH_STRNCAT 1
108#define __HAVE_ARCH_STRCMP 1
109#define __HAVE_ARCH_STRNCMP 1
110#define __HAVE_ARCH_STRNICMP 1
111#define __HAVE_ARCH_STRCHR 1
112#define __HAVE_ARCH_STRRCHR 1
113#define __HAVE_ARCH_STRSTR 1
114#define __HAVE_ARCH_STRLEN 1
115#define __HAVE_ARCH_STRNLEN 1
116#define __HAVE_ARCH_MEMSET 1
117#define __HAVE_ARCH_MEMCPY 1
118#define __HAVE_ARCH_MEMMOVE 1
119#define __HAVE_ARCH_MEMSCAN 1
120#define __HAVE_ARCH_MEMCMP 1
121#define __HAVE_ARCH_MEMCHR 1
122#define __HAVE_ARCH_STRTOK 1
123
124#endif /* KERNEL */
125
126#endif /* _M68K_STRING_H_ */
diff --git a/arch/m68knommu/include/asm/system.h b/arch/m68knommu/include/asm/system.h
new file mode 100644
index 000000000000..40f49de69821
--- /dev/null
+++ b/arch/m68knommu/include/asm/system.h
@@ -0,0 +1,324 @@
1#ifndef _M68KNOMMU_SYSTEM_H
2#define _M68KNOMMU_SYSTEM_H
3
4#include <linux/linkage.h>
5#include <asm/segment.h>
6#include <asm/entry.h>
7
8/*
9 * switch_to(n) should switch tasks to task ptr, first checking that
10 * ptr isn't the current task, in which case it does nothing. This
11 * also clears the TS-flag if the task we switched to has used the
12 * math co-processor latest.
13 */
14/*
15 * switch_to() saves the extra registers, that are not saved
16 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
17 * a0-a1. Some of these are used by schedule() and its predecessors
18 * and so we might get see unexpected behaviors when a task returns
19 * with unexpected register values.
20 *
21 * syscall stores these registers itself and none of them are used
22 * by syscall after the function in the syscall has been called.
23 *
24 * Beware that resume now expects *next to be in d1 and the offset of
25 * tss to be in a1. This saves a few instructions as we no longer have
26 * to push them onto the stack and read them back right after.
27 *
28 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
29 *
30 * Changed 96/09/19 by Andreas Schwab
31 * pass prev in a0, next in a1, offset of tss in d1, and whether
32 * the mm structures are shared in d2 (to avoid atc flushing).
33 */
34asmlinkage void resume(void);
35#define switch_to(prev,next,last) \
36{ \
37 void *_last; \
38 __asm__ __volatile__( \
39 "movel %1, %%a0\n\t" \
40 "movel %2, %%a1\n\t" \
41 "jbsr resume\n\t" \
42 "movel %%d1, %0\n\t" \
43 : "=d" (_last) \
44 : "d" (prev), "d" (next) \
45 : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
46 (last) = _last; \
47}
48
49#ifdef CONFIG_COLDFIRE
50#define local_irq_enable() __asm__ __volatile__ ( \
51 "move %/sr,%%d0\n\t" \
52 "andi.l #0xf8ff,%%d0\n\t" \
53 "move %%d0,%/sr\n" \
54 : /* no outputs */ \
55 : \
56 : "cc", "%d0", "memory")
57#define local_irq_disable() __asm__ __volatile__ ( \
58 "move %/sr,%%d0\n\t" \
59 "ori.l #0x0700,%%d0\n\t" \
60 "move %%d0,%/sr\n" \
61 : /* no outputs */ \
62 : \
63 : "cc", "%d0", "memory")
64/* For spinlocks etc */
65#define local_irq_save(x) __asm__ __volatile__ ( \
66 "movew %%sr,%0\n\t" \
67 "movew #0x0700,%%d0\n\t" \
68 "or.l %0,%%d0\n\t" \
69 "movew %%d0,%/sr" \
70 : "=d" (x) \
71 : \
72 : "cc", "%d0", "memory")
73#else
74
75/* portable version */ /* FIXME - see entry.h*/
76#define ALLOWINT 0xf8ff
77
78#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
79#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
80#endif
81
82#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
83#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
84
85/* For spinlocks etc */
86#ifndef local_irq_save
87#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
88#endif
89
90#define irqs_disabled() \
91({ \
92 unsigned long flags; \
93 local_save_flags(flags); \
94 ((flags & 0x0700) == 0x0700); \
95})
96
97#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
98
99/*
100 * Force strict CPU ordering.
101 * Not really required on m68k...
102 */
103#define nop() asm volatile ("nop"::)
104#define mb() asm volatile ("" : : :"memory")
105#define rmb() asm volatile ("" : : :"memory")
106#define wmb() asm volatile ("" : : :"memory")
107#define set_mb(var, value) ({ (var) = (value); wmb(); })
108
109#ifdef CONFIG_SMP
110#define smp_mb() mb()
111#define smp_rmb() rmb()
112#define smp_wmb() wmb()
113#define smp_read_barrier_depends() read_barrier_depends()
114#else
115#define smp_mb() barrier()
116#define smp_rmb() barrier()
117#define smp_wmb() barrier()
118#define smp_read_barrier_depends() do { } while(0)
119#endif
120
121#define read_barrier_depends() ((void)0)
122
123#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
124
125struct __xchg_dummy { unsigned long a[100]; };
126#define __xg(x) ((volatile struct __xchg_dummy *)(x))
127
128#ifndef CONFIG_RMW_INSNS
129static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
130{
131 unsigned long tmp, flags;
132
133 local_irq_save(flags);
134
135 switch (size) {
136 case 1:
137 __asm__ __volatile__
138 ("moveb %2,%0\n\t"
139 "moveb %1,%2"
140 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
141 break;
142 case 2:
143 __asm__ __volatile__
144 ("movew %2,%0\n\t"
145 "movew %1,%2"
146 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
147 break;
148 case 4:
149 __asm__ __volatile__
150 ("movel %2,%0\n\t"
151 "movel %1,%2"
152 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
153 break;
154 }
155 local_irq_restore(flags);
156 return tmp;
157}
158#else
159static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
160{
161 switch (size) {
162 case 1:
163 __asm__ __volatile__
164 ("moveb %2,%0\n\t"
165 "1:\n\t"
166 "casb %0,%1,%2\n\t"
167 "jne 1b"
168 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
169 break;
170 case 2:
171 __asm__ __volatile__
172 ("movew %2,%0\n\t"
173 "1:\n\t"
174 "casw %0,%1,%2\n\t"
175 "jne 1b"
176 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
177 break;
178 case 4:
179 __asm__ __volatile__
180 ("movel %2,%0\n\t"
181 "1:\n\t"
182 "casl %0,%1,%2\n\t"
183 "jne 1b"
184 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
185 break;
186 }
187 return x;
188}
189#endif
190
191#include <asm-generic/cmpxchg-local.h>
192
193/*
194 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
195 * them available.
196 */
197#define cmpxchg_local(ptr, o, n) \
198 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
199 (unsigned long)(n), sizeof(*(ptr))))
200#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
201
202#ifndef CONFIG_SMP
203#include <asm-generic/cmpxchg.h>
204#endif
205
206#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \
207 defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 )
208#define HARD_RESET_NOW() ({ \
209 local_irq_disable(); \
210 asm(" \
211 moveal #0x10c00000, %a0; \
212 moveb #0, 0xFFFFF300; \
213 moveal 0(%a0), %sp; \
214 moveal 4(%a0), %a0; \
215 jmp (%a0); \
216 "); \
217})
218#endif
219
220#ifdef CONFIG_COLDFIRE
221#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
222/*
223 * Need to account for broken early mask of 5272 silicon. So don't
224 * jump through the original start address. Jump strait into the
225 * known start of the FLASH code.
226 */
227#define HARD_RESET_NOW() ({ \
228 asm(" \
229 movew #0x2700, %sr; \
230 jmp 0xf0000400; \
231 "); \
232})
233#elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
234 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
235#define HARD_RESET_NOW() ({ \
236 asm(" \
237 movew #0x2700, %sr; \
238 moveal #0x10000044, %a0; \
239 movel #0xffffffff, (%a0); \
240 moveal #0x10000001, %a0; \
241 moveb #0x00, (%a0); \
242 moveal #0xf0000004, %a0; \
243 moveal (%a0), %a0; \
244 jmp (%a0); \
245 "); \
246})
247#elif defined(CONFIG_M5272)
248/*
249 * Retrieve the boot address in flash using CSBR0 and CSOR0
250 * find the reset vector at flash_address + 4 (e.g. 0x400)
251 * remap it in the flash's current location (e.g. 0xf0000400)
252 * and jump there.
253 */
254#define HARD_RESET_NOW() ({ \
255 asm(" \
256 movew #0x2700, %%sr; \
257 move.l %0+0x40,%%d0; \
258 and.l %0+0x44,%%d0; \
259 andi.l #0xfffff000,%%d0; \
260 mov.l %%d0,%%a0; \
261 or.l 4(%%a0),%%d0; \
262 mov.l %%d0,%%a0; \
263 jmp (%%a0);" \
264 : /* No output */ \
265 : "o" (*(char *)MCF_MBAR) ); \
266})
267#elif defined(CONFIG_M528x)
268/*
269 * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
270 * that when set, resets the MCF528x.
271 */
272#define HARD_RESET_NOW() \
273({ \
274 unsigned char volatile *reset; \
275 asm("move.w #0x2700, %sr"); \
276 reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \
277 while(1) \
278 *reset |= (0x01 << 7);\
279})
280#elif defined(CONFIG_M523x)
281#define HARD_RESET_NOW() ({ \
282 asm(" \
283 movew #0x2700, %sr; \
284 movel #0x01000000, %sp; \
285 moveal #0x40110000, %a0; \
286 moveb #0x80, (%a0); \
287 "); \
288})
289#elif defined(CONFIG_M520x)
290 /*
291 * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register
292 * RCR), that when set, resets the MCF5208.
293 */
294#define HARD_RESET_NOW() \
295({ \
296 unsigned char volatile *reset; \
297 asm("move.w #0x2700, %sr"); \
298 reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \
299 while(1) \
300 *reset |= 0x80; \
301})
302#else
303#define HARD_RESET_NOW() ({ \
304 asm(" \
305 movew #0x2700, %sr; \
306 moveal #0x4, %a0; \
307 moveal (%a0), %a0; \
308 jmp (%a0); \
309 "); \
310})
311#endif
312#endif
313#define arch_align_stack(x) (x)
314
315
316static inline int irqs_disabled_flags(unsigned long flags)
317{
318 if (flags & 0x0700)
319 return 0;
320 else
321 return 1;
322}
323
324#endif /* _M68KNOMMU_SYSTEM_H */
diff --git a/arch/m68knommu/include/asm/termbits.h b/arch/m68knommu/include/asm/termbits.h
new file mode 100644
index 000000000000..05dd6bc27285
--- /dev/null
+++ b/arch/m68knommu/include/asm/termbits.h
@@ -0,0 +1 @@
#include <asm-m68k/termbits.h>
diff --git a/arch/m68knommu/include/asm/termios.h b/arch/m68knommu/include/asm/termios.h
new file mode 100644
index 000000000000..e7337881a985
--- /dev/null
+++ b/arch/m68knommu/include/asm/termios.h
@@ -0,0 +1 @@
#include <asm-m68k/termios.h>
diff --git a/arch/m68knommu/include/asm/thread_info.h b/arch/m68knommu/include/asm/thread_info.h
new file mode 100644
index 000000000000..0c9bc095f3f0
--- /dev/null
+++ b/arch/m68knommu/include/asm/thread_info.h
@@ -0,0 +1,98 @@
1/* thread_info.h: m68knommu low-level thread information
2 * adapted from the i386 and PPC versions by Greg Ungerer (gerg@snapgear.com)
3 *
4 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
5 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
6 */
7
8#ifndef _ASM_THREAD_INFO_H
9#define _ASM_THREAD_INFO_H
10
11#include <asm/page.h>
12
13#ifdef __KERNEL__
14
15#ifndef __ASSEMBLY__
16
17/*
18 * Size of kernel stack for each process. This must be a power of 2...
19 */
20#ifdef CONFIG_4KSTACKS
21#define THREAD_SIZE_ORDER (0)
22#else
23#define THREAD_SIZE_ORDER (1)
24#endif
25
26/*
27 * for asm files, THREAD_SIZE is now generated by asm-offsets.c
28 */
29#define THREAD_SIZE (PAGE_SIZE<<THREAD_SIZE_ORDER)
30
31/*
32 * low level task data.
33 */
34struct thread_info {
35 struct task_struct *task; /* main task structure */
36 struct exec_domain *exec_domain; /* execution domain */
37 unsigned long flags; /* low level flags */
38 int cpu; /* cpu we're on */
39 int preempt_count; /* 0 => preemptable, <0 => BUG */
40 struct restart_block restart_block;
41};
42
43/*
44 * macros/functions for gaining access to the thread information structure
45 */
46#define INIT_THREAD_INFO(tsk) \
47{ \
48 .task = &tsk, \
49 .exec_domain = &default_exec_domain, \
50 .flags = 0, \
51 .cpu = 0, \
52 .restart_block = { \
53 .fn = do_no_restart_syscall, \
54 }, \
55}
56
57#define init_thread_info (init_thread_union.thread_info)
58#define init_stack (init_thread_union.stack)
59
60
61/* how to get the thread information struct from C */
62static inline struct thread_info *current_thread_info(void)
63{
64 struct thread_info *ti;
65 __asm__(
66 "move.l %%sp, %0 \n\t"
67 "and.l %1, %0"
68 : "=&d"(ti)
69 : "di" (~(THREAD_SIZE-1))
70 );
71 return ti;
72}
73
74#endif /* __ASSEMBLY__ */
75
76#define PREEMPT_ACTIVE 0x4000000
77
78/*
79 * thread information flag bit numbers
80 */
81#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
82#define TIF_SIGPENDING 1 /* signal pending */
83#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
84#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
85 TIF_NEED_RESCHED */
86#define TIF_MEMDIE 4
87
88/* as above, but as bit values */
89#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
90#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
91#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
92#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
93
94#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
95
96#endif /* __KERNEL__ */
97
98#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/m68knommu/include/asm/timex.h b/arch/m68knommu/include/asm/timex.h
new file mode 100644
index 000000000000..109050f3fe91
--- /dev/null
+++ b/arch/m68knommu/include/asm/timex.h
@@ -0,0 +1,23 @@
1/*
2 * linux/include/asm-m68knommu/timex.h
3 *
4 * m68knommu architecture timex specifications
5 */
6#ifndef _ASM_M68KNOMMU_TIMEX_H
7#define _ASM_M68KNOMMU_TIMEX_H
8
9#ifdef CONFIG_COLDFIRE
10#include <asm/coldfire.h>
11#define CLOCK_TICK_RATE MCF_CLK
12#else
13#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
14#endif
15
16typedef unsigned long cycles_t;
17
18static inline cycles_t get_cycles(void)
19{
20 return 0;
21}
22
23#endif
diff --git a/arch/m68knommu/include/asm/tlb.h b/arch/m68knommu/include/asm/tlb.h
new file mode 100644
index 000000000000..77a7c51ca299
--- /dev/null
+++ b/arch/m68knommu/include/asm/tlb.h
@@ -0,0 +1 @@
#include <asm-m68k/tlb.h>
diff --git a/arch/m68knommu/include/asm/tlbflush.h b/arch/m68knommu/include/asm/tlbflush.h
new file mode 100644
index 000000000000..a470cfb803eb
--- /dev/null
+++ b/arch/m68knommu/include/asm/tlbflush.h
@@ -0,0 +1,55 @@
1#ifndef _M68KNOMMU_TLBFLUSH_H
2#define _M68KNOMMU_TLBFLUSH_H
3
4/*
5 * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
6 * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
7 */
8
9#include <asm/setup.h>
10
11/*
12 * flush all user-space atc entries.
13 */
14static inline void __flush_tlb(void)
15{
16 BUG();
17}
18
19static inline void __flush_tlb_one(unsigned long addr)
20{
21 BUG();
22}
23
24#define flush_tlb() __flush_tlb()
25
26/*
27 * flush all atc entries (both kernel and user-space entries).
28 */
29static inline void flush_tlb_all(void)
30{
31 BUG();
32}
33
34static inline void flush_tlb_mm(struct mm_struct *mm)
35{
36 BUG();
37}
38
39static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
40{
41 BUG();
42}
43
44static inline void flush_tlb_range(struct mm_struct *mm,
45 unsigned long start, unsigned long end)
46{
47 BUG();
48}
49
50static inline void flush_tlb_kernel_page(unsigned long addr)
51{
52 BUG();
53}
54
55#endif /* _M68KNOMMU_TLBFLUSH_H */
diff --git a/arch/m68knommu/include/asm/topology.h b/arch/m68knommu/include/asm/topology.h
new file mode 100644
index 000000000000..ca173e9f26ff
--- /dev/null
+++ b/arch/m68knommu/include/asm/topology.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_M68K_TOPOLOGY_H
2#define _ASM_M68K_TOPOLOGY_H
3
4#include <asm-generic/topology.h>
5
6#endif /* _ASM_M68K_TOPOLOGY_H */
diff --git a/arch/m68knommu/include/asm/traps.h b/arch/m68knommu/include/asm/traps.h
new file mode 100644
index 000000000000..d0671e5f8e29
--- /dev/null
+++ b/arch/m68knommu/include/asm/traps.h
@@ -0,0 +1,154 @@
1/*
2 * linux/include/asm/traps.h
3 *
4 * Copyright (C) 1993 Hamish Macdonald
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef _M68KNOMMU_TRAPS_H
12#define _M68KNOMMU_TRAPS_H
13
14#ifndef __ASSEMBLY__
15
16typedef void (*e_vector)(void);
17
18extern e_vector vectors[];
19extern void init_vectors(void);
20extern void enable_vector(unsigned int irq);
21extern void disable_vector(unsigned int irq);
22extern void ack_vector(unsigned int irq);
23
24#endif
25
26#define VEC_BUSERR (2)
27#define VEC_ADDRERR (3)
28#define VEC_ILLEGAL (4)
29#define VEC_ZERODIV (5)
30#define VEC_CHK (6)
31#define VEC_TRAP (7)
32#define VEC_PRIV (8)
33#define VEC_TRACE (9)
34#define VEC_LINE10 (10)
35#define VEC_LINE11 (11)
36#define VEC_RESV1 (12)
37#define VEC_COPROC (13)
38#define VEC_FORMAT (14)
39#define VEC_UNINT (15)
40#define VEC_SPUR (24)
41#define VEC_INT1 (25)
42#define VEC_INT2 (26)
43#define VEC_INT3 (27)
44#define VEC_INT4 (28)
45#define VEC_INT5 (29)
46#define VEC_INT6 (30)
47#define VEC_INT7 (31)
48#define VEC_SYS (32)
49#define VEC_TRAP1 (33)
50#define VEC_TRAP2 (34)
51#define VEC_TRAP3 (35)
52#define VEC_TRAP4 (36)
53#define VEC_TRAP5 (37)
54#define VEC_TRAP6 (38)
55#define VEC_TRAP7 (39)
56#define VEC_TRAP8 (40)
57#define VEC_TRAP9 (41)
58#define VEC_TRAP10 (42)
59#define VEC_TRAP11 (43)
60#define VEC_TRAP12 (44)
61#define VEC_TRAP13 (45)
62#define VEC_TRAP14 (46)
63#define VEC_TRAP15 (47)
64#define VEC_FPBRUC (48)
65#define VEC_FPIR (49)
66#define VEC_FPDIVZ (50)
67#define VEC_FPUNDER (51)
68#define VEC_FPOE (52)
69#define VEC_FPOVER (53)
70#define VEC_FPNAN (54)
71#define VEC_FPUNSUP (55)
72#define VEC_UNIMPEA (60)
73#define VEC_UNIMPII (61)
74#define VEC_USER (64)
75
76#define VECOFF(vec) ((vec)<<2)
77
78#ifndef __ASSEMBLY__
79
80/* Status register bits */
81#define PS_T (0x8000)
82#define PS_S (0x2000)
83#define PS_M (0x1000)
84#define PS_C (0x0001)
85
86/* structure for stack frames */
87
88struct frame {
89 struct pt_regs ptregs;
90 union {
91 struct {
92 unsigned long iaddr; /* instruction address */
93 } fmt2;
94 struct {
95 unsigned long effaddr; /* effective address */
96 } fmt3;
97 struct {
98 unsigned long effaddr; /* effective address */
99 unsigned long pc; /* pc of faulted instr */
100 } fmt4;
101 struct {
102 unsigned long effaddr; /* effective address */
103 unsigned short ssw; /* special status word */
104 unsigned short wb3s; /* write back 3 status */
105 unsigned short wb2s; /* write back 2 status */
106 unsigned short wb1s; /* write back 1 status */
107 unsigned long faddr; /* fault address */
108 unsigned long wb3a; /* write back 3 address */
109 unsigned long wb3d; /* write back 3 data */
110 unsigned long wb2a; /* write back 2 address */
111 unsigned long wb2d; /* write back 2 data */
112 unsigned long wb1a; /* write back 1 address */
113 unsigned long wb1dpd0; /* write back 1 data/push data 0*/
114 unsigned long pd1; /* push data 1*/
115 unsigned long pd2; /* push data 2*/
116 unsigned long pd3; /* push data 3*/
117 } fmt7;
118 struct {
119 unsigned long iaddr; /* instruction address */
120 unsigned short int1[4]; /* internal registers */
121 } fmt9;
122 struct {
123 unsigned short int1;
124 unsigned short ssw; /* special status word */
125 unsigned short isc; /* instruction stage c */
126 unsigned short isb; /* instruction stage b */
127 unsigned long daddr; /* data cycle fault address */
128 unsigned short int2[2];
129 unsigned long dobuf; /* data cycle output buffer */
130 unsigned short int3[2];
131 } fmta;
132 struct {
133 unsigned short int1;
134 unsigned short ssw; /* special status word */
135 unsigned short isc; /* instruction stage c */
136 unsigned short isb; /* instruction stage b */
137 unsigned long daddr; /* data cycle fault address */
138 unsigned short int2[2];
139 unsigned long dobuf; /* data cycle output buffer */
140 unsigned short int3[4];
141 unsigned long baddr; /* stage B address */
142 unsigned short int4[2];
143 unsigned long dibuf; /* data cycle input buffer */
144 unsigned short int5[3];
145 unsigned ver : 4; /* stack frame version # */
146 unsigned int6:12;
147 unsigned short int7[18];
148 } fmtb;
149 } un;
150};
151
152#endif /* __ASSEMBLY__ */
153
154#endif /* _M68KNOMMU_TRAPS_H */
diff --git a/arch/m68knommu/include/asm/types.h b/arch/m68knommu/include/asm/types.h
new file mode 100644
index 000000000000..031238c2d180
--- /dev/null
+++ b/arch/m68knommu/include/asm/types.h
@@ -0,0 +1 @@
#include <asm-m68k/types.h>
diff --git a/arch/m68knommu/include/asm/uaccess.h b/arch/m68knommu/include/asm/uaccess.h
new file mode 100644
index 000000000000..68bbe9b312f1
--- /dev/null
+++ b/arch/m68knommu/include/asm/uaccess.h
@@ -0,0 +1,181 @@
1#ifndef __M68KNOMMU_UACCESS_H
2#define __M68KNOMMU_UACCESS_H
3
4/*
5 * User space memory access functions
6 */
7#include <linux/sched.h>
8#include <linux/mm.h>
9#include <linux/string.h>
10
11#include <asm/segment.h>
12
13#define VERIFY_READ 0
14#define VERIFY_WRITE 1
15
16#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size))
17
18/*
19 * It is not enough to just have access_ok check for a real RAM address.
20 * This would disallow the case of code/ro-data running XIP in flash/rom.
21 * Ideally we would check the possible flash ranges too, but that is
22 * currently not so easy.
23 */
24static inline int _access_ok(unsigned long addr, unsigned long size)
25{
26 return 1;
27}
28
29/*
30 * The exception table consists of pairs of addresses: the first is the
31 * address of an instruction that is allowed to fault, and the second is
32 * the address at which the program should continue. No registers are
33 * modified, so it is entirely up to the continuation code to figure out
34 * what to do.
35 *
36 * All the routines below use bits of fixup code that are out of line
37 * with the main instruction path. This means when everything is well,
38 * we don't even have to jump over them. Further, they do not intrude
39 * on our cache or tlb entries.
40 */
41
42struct exception_table_entry
43{
44 unsigned long insn, fixup;
45};
46
47/* Returns 0 if exception not found and fixup otherwise. */
48extern unsigned long search_exception_table(unsigned long);
49
50
51/*
52 * These are the main single-value transfer routines. They automatically
53 * use the right size if we just have the right pointer type.
54 */
55
56#define put_user(x, ptr) \
57({ \
58 int __pu_err = 0; \
59 typeof(*(ptr)) __pu_val = (x); \
60 switch (sizeof (*(ptr))) { \
61 case 1: \
62 __put_user_asm(__pu_err, __pu_val, ptr, b); \
63 break; \
64 case 2: \
65 __put_user_asm(__pu_err, __pu_val, ptr, w); \
66 break; \
67 case 4: \
68 __put_user_asm(__pu_err, __pu_val, ptr, l); \
69 break; \
70 case 8: \
71 memcpy(ptr, &__pu_val, sizeof (*(ptr))); \
72 break; \
73 default: \
74 __pu_err = __put_user_bad(); \
75 break; \
76 } \
77 __pu_err; \
78})
79#define __put_user(x, ptr) put_user(x, ptr)
80
81extern int __put_user_bad(void);
82
83/*
84 * Tell gcc we read from memory instead of writing: this is because
85 * we do not write to any memory gcc knows about, so there are no
86 * aliasing issues.
87 */
88
89#define __ptr(x) ((unsigned long *)(x))
90
91#define __put_user_asm(err,x,ptr,bwl) \
92 __asm__ ("move" #bwl " %0,%1" \
93 : /* no outputs */ \
94 :"d" (x),"m" (*__ptr(ptr)) : "memory")
95
96#define get_user(x, ptr) \
97({ \
98 int __gu_err = 0; \
99 typeof(x) __gu_val = 0; \
100 switch (sizeof(*(ptr))) { \
101 case 1: \
102 __get_user_asm(__gu_err, __gu_val, ptr, b, "=d"); \
103 break; \
104 case 2: \
105 __get_user_asm(__gu_err, __gu_val, ptr, w, "=r"); \
106 break; \
107 case 4: \
108 __get_user_asm(__gu_err, __gu_val, ptr, l, "=r"); \
109 break; \
110 case 8: \
111 memcpy((void *) &__gu_val, ptr, sizeof (*(ptr))); \
112 break; \
113 default: \
114 __gu_val = 0; \
115 __gu_err = __get_user_bad(); \
116 break; \
117 } \
118 (x) = (typeof(*(ptr))) __gu_val; \
119 __gu_err; \
120})
121#define __get_user(x, ptr) get_user(x, ptr)
122
123extern int __get_user_bad(void);
124
125#define __get_user_asm(err,x,ptr,bwl,reg) \
126 __asm__ ("move" #bwl " %1,%0" \
127 : "=d" (x) \
128 : "m" (*__ptr(ptr)))
129
130#define copy_from_user(to, from, n) (memcpy(to, from, n), 0)
131#define copy_to_user(to, from, n) (memcpy(to, from, n), 0)
132
133#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
134#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
135#define __copy_to_user_inatomic __copy_to_user
136#define __copy_from_user_inatomic __copy_from_user
137
138#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; })
139
140#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; })
141
142/*
143 * Copy a null terminated string from userspace.
144 */
145
146static inline long
147strncpy_from_user(char *dst, const char *src, long count)
148{
149 char *tmp;
150 strncpy(dst, src, count);
151 for (tmp = dst; *tmp && count > 0; tmp++, count--)
152 ;
153 return(tmp - dst); /* DAVIDM should we count a NUL ? check getname */
154}
155
156/*
157 * Return the size of a string (including the ending 0)
158 *
159 * Return 0 on exception, a value greater than N if too long
160 */
161static inline long strnlen_user(const char *src, long n)
162{
163 return(strlen(src) + 1); /* DAVIDM make safer */
164}
165
166#define strlen_user(str) strnlen_user(str, 32767)
167
168/*
169 * Zero Userspace
170 */
171
172static inline unsigned long
173__clear_user(void *to, unsigned long n)
174{
175 memset(to, 0, n);
176 return 0;
177}
178
179#define clear_user(to,n) __clear_user(to,n)
180
181#endif /* _M68KNOMMU_UACCESS_H */
diff --git a/arch/m68knommu/include/asm/ucontext.h b/arch/m68knommu/include/asm/ucontext.h
new file mode 100644
index 000000000000..713a27f901cd
--- /dev/null
+++ b/arch/m68knommu/include/asm/ucontext.h
@@ -0,0 +1,32 @@
1#ifndef _M68KNOMMU_UCONTEXT_H
2#define _M68KNOMMU_UCONTEXT_H
3
4typedef int greg_t;
5#define NGREG 18
6typedef greg_t gregset_t[NGREG];
7
8typedef struct fpregset {
9 int f_pcr;
10 int f_psr;
11 int f_fpiaddr;
12 int f_fpregs[8][3];
13} fpregset_t;
14
15struct mcontext {
16 int version;
17 gregset_t gregs;
18 fpregset_t fpregs;
19};
20
21#define MCONTEXT_VERSION 2
22
23struct ucontext {
24 unsigned long uc_flags;
25 struct ucontext *uc_link;
26 stack_t uc_stack;
27 struct mcontext uc_mcontext;
28 unsigned long uc_filler[80];
29 sigset_t uc_sigmask; /* mask last for extensibility */
30};
31
32#endif
diff --git a/arch/m68knommu/include/asm/unaligned.h b/arch/m68knommu/include/asm/unaligned.h
new file mode 100644
index 000000000000..eb1ea4cb9a59
--- /dev/null
+++ b/arch/m68knommu/include/asm/unaligned.h
@@ -0,0 +1,25 @@
1#ifndef _ASM_M68KNOMMU_UNALIGNED_H
2#define _ASM_M68KNOMMU_UNALIGNED_H
3
4
5#ifdef CONFIG_COLDFIRE
6#include <linux/unaligned/be_struct.h>
7#include <linux/unaligned/le_byteshift.h>
8#include <linux/unaligned/generic.h>
9
10#define get_unaligned __get_unaligned_be
11#define put_unaligned __put_unaligned_be
12
13#else
14/*
15 * The m68k can do unaligned accesses itself.
16 */
17#include <linux/unaligned/access_ok.h>
18#include <linux/unaligned/generic.h>
19
20#define get_unaligned __get_unaligned_be
21#define put_unaligned __put_unaligned_be
22
23#endif
24
25#endif /* _ASM_M68KNOMMU_UNALIGNED_H */
diff --git a/arch/m68knommu/include/asm/unistd.h b/arch/m68knommu/include/asm/unistd.h
new file mode 100644
index 000000000000..4ba98b9c5d79
--- /dev/null
+++ b/arch/m68knommu/include/asm/unistd.h
@@ -0,0 +1,366 @@
1#ifndef _ASM_M68K_UNISTD_H_
2#define _ASM_M68K_UNISTD_H_
3
4/*
5 * This file contains the system call numbers.
6 */
7
8#define __NR_restart_syscall 0
9#define __NR_exit 1
10#define __NR_fork 2
11#define __NR_read 3
12#define __NR_write 4
13#define __NR_open 5
14#define __NR_close 6
15#define __NR_waitpid 7
16#define __NR_creat 8
17#define __NR_link 9
18#define __NR_unlink 10
19#define __NR_execve 11
20#define __NR_chdir 12
21#define __NR_time 13
22#define __NR_mknod 14
23#define __NR_chmod 15
24#define __NR_chown 16
25#define __NR_break 17
26#define __NR_oldstat 18
27#define __NR_lseek 19
28#define __NR_getpid 20
29#define __NR_mount 21
30#define __NR_umount 22
31#define __NR_setuid 23
32#define __NR_getuid 24
33#define __NR_stime 25
34#define __NR_ptrace 26
35#define __NR_alarm 27
36#define __NR_oldfstat 28
37#define __NR_pause 29
38#define __NR_utime 30
39#define __NR_stty 31
40#define __NR_gtty 32
41#define __NR_access 33
42#define __NR_nice 34
43#define __NR_ftime 35
44#define __NR_sync 36
45#define __NR_kill 37
46#define __NR_rename 38
47#define __NR_mkdir 39
48#define __NR_rmdir 40
49#define __NR_dup 41
50#define __NR_pipe 42
51#define __NR_times 43
52#define __NR_prof 44
53#define __NR_brk 45
54#define __NR_setgid 46
55#define __NR_getgid 47
56#define __NR_signal 48
57#define __NR_geteuid 49
58#define __NR_getegid 50
59#define __NR_acct 51
60#define __NR_umount2 52
61#define __NR_lock 53
62#define __NR_ioctl 54
63#define __NR_fcntl 55
64#define __NR_mpx 56
65#define __NR_setpgid 57
66#define __NR_ulimit 58
67#define __NR_oldolduname 59
68#define __NR_umask 60
69#define __NR_chroot 61
70#define __NR_ustat 62
71#define __NR_dup2 63
72#define __NR_getppid 64
73#define __NR_getpgrp 65
74#define __NR_setsid 66
75#define __NR_sigaction 67
76#define __NR_sgetmask 68
77#define __NR_ssetmask 69
78#define __NR_setreuid 70
79#define __NR_setregid 71
80#define __NR_sigsuspend 72
81#define __NR_sigpending 73
82#define __NR_sethostname 74
83#define __NR_setrlimit 75
84#define __NR_getrlimit 76
85#define __NR_getrusage 77
86#define __NR_gettimeofday 78
87#define __NR_settimeofday 79
88#define __NR_getgroups 80
89#define __NR_setgroups 81
90#define __NR_select 82
91#define __NR_symlink 83
92#define __NR_oldlstat 84
93#define __NR_readlink 85
94#define __NR_uselib 86
95#define __NR_swapon 87
96#define __NR_reboot 88
97#define __NR_readdir 89
98#define __NR_mmap 90
99#define __NR_munmap 91
100#define __NR_truncate 92
101#define __NR_ftruncate 93
102#define __NR_fchmod 94
103#define __NR_fchown 95
104#define __NR_getpriority 96
105#define __NR_setpriority 97
106#define __NR_profil 98
107#define __NR_statfs 99
108#define __NR_fstatfs 100
109#define __NR_ioperm 101
110#define __NR_socketcall 102
111#define __NR_syslog 103
112#define __NR_setitimer 104
113#define __NR_getitimer 105
114#define __NR_stat 106
115#define __NR_lstat 107
116#define __NR_fstat 108
117#define __NR_olduname 109
118#define __NR_iopl /* 110 */ not supported
119#define __NR_vhangup 111
120#define __NR_idle /* 112 */ Obsolete
121#define __NR_vm86 /* 113 */ not supported
122#define __NR_wait4 114
123#define __NR_swapoff 115
124#define __NR_sysinfo 116
125#define __NR_ipc 117
126#define __NR_fsync 118
127#define __NR_sigreturn 119
128#define __NR_clone 120
129#define __NR_setdomainname 121
130#define __NR_uname 122
131#define __NR_cacheflush 123
132#define __NR_adjtimex 124
133#define __NR_mprotect 125
134#define __NR_sigprocmask 126
135#define __NR_create_module 127
136#define __NR_init_module 128
137#define __NR_delete_module 129
138#define __NR_get_kernel_syms 130
139#define __NR_quotactl 131
140#define __NR_getpgid 132
141#define __NR_fchdir 133
142#define __NR_bdflush 134
143#define __NR_sysfs 135
144#define __NR_personality 136
145#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
146#define __NR_setfsuid 138
147#define __NR_setfsgid 139
148#define __NR__llseek 140
149#define __NR_getdents 141
150#define __NR__newselect 142
151#define __NR_flock 143
152#define __NR_msync 144
153#define __NR_readv 145
154#define __NR_writev 146
155#define __NR_getsid 147
156#define __NR_fdatasync 148
157#define __NR__sysctl 149
158#define __NR_mlock 150
159#define __NR_munlock 151
160#define __NR_mlockall 152
161#define __NR_munlockall 153
162#define __NR_sched_setparam 154
163#define __NR_sched_getparam 155
164#define __NR_sched_setscheduler 156
165#define __NR_sched_getscheduler 157
166#define __NR_sched_yield 158
167#define __NR_sched_get_priority_max 159
168#define __NR_sched_get_priority_min 160
169#define __NR_sched_rr_get_interval 161
170#define __NR_nanosleep 162
171#define __NR_mremap 163
172#define __NR_setresuid 164
173#define __NR_getresuid 165
174#define __NR_getpagesize 166
175#define __NR_query_module 167
176#define __NR_poll 168
177#define __NR_nfsservctl 169
178#define __NR_setresgid 170
179#define __NR_getresgid 171
180#define __NR_prctl 172
181#define __NR_rt_sigreturn 173
182#define __NR_rt_sigaction 174
183#define __NR_rt_sigprocmask 175
184#define __NR_rt_sigpending 176
185#define __NR_rt_sigtimedwait 177
186#define __NR_rt_sigqueueinfo 178
187#define __NR_rt_sigsuspend 179
188#define __NR_pread64 180
189#define __NR_pwrite64 181
190#define __NR_lchown 182
191#define __NR_getcwd 183
192#define __NR_capget 184
193#define __NR_capset 185
194#define __NR_sigaltstack 186
195#define __NR_sendfile 187
196#define __NR_getpmsg 188 /* some people actually want streams */
197#define __NR_putpmsg 189 /* some people actually want streams */
198#define __NR_vfork 190
199#define __NR_ugetrlimit 191
200#define __NR_mmap2 192
201#define __NR_truncate64 193
202#define __NR_ftruncate64 194
203#define __NR_stat64 195
204#define __NR_lstat64 196
205#define __NR_fstat64 197
206#define __NR_chown32 198
207#define __NR_getuid32 199
208#define __NR_getgid32 200
209#define __NR_geteuid32 201
210#define __NR_getegid32 202
211#define __NR_setreuid32 203
212#define __NR_setregid32 204
213#define __NR_getgroups32 205
214#define __NR_setgroups32 206
215#define __NR_fchown32 207
216#define __NR_setresuid32 208
217#define __NR_getresuid32 209
218#define __NR_setresgid32 210
219#define __NR_getresgid32 211
220#define __NR_lchown32 212
221#define __NR_setuid32 213
222#define __NR_setgid32 214
223#define __NR_setfsuid32 215
224#define __NR_setfsgid32 216
225#define __NR_pivot_root 217
226#define __NR_getdents64 220
227#define __NR_gettid 221
228#define __NR_tkill 222
229#define __NR_setxattr 223
230#define __NR_lsetxattr 224
231#define __NR_fsetxattr 225
232#define __NR_getxattr 226
233#define __NR_lgetxattr 227
234#define __NR_fgetxattr 228
235#define __NR_listxattr 229
236#define __NR_llistxattr 230
237#define __NR_flistxattr 231
238#define __NR_removexattr 232
239#define __NR_lremovexattr 233
240#define __NR_fremovexattr 234
241#define __NR_futex 235
242#define __NR_sendfile64 236
243#define __NR_mincore 237
244#define __NR_madvise 238
245#define __NR_fcntl64 239
246#define __NR_readahead 240
247#define __NR_io_setup 241
248#define __NR_io_destroy 242
249#define __NR_io_getevents 243
250#define __NR_io_submit 244
251#define __NR_io_cancel 245
252#define __NR_fadvise64 246
253#define __NR_exit_group 247
254#define __NR_lookup_dcookie 248
255#define __NR_epoll_create 249
256#define __NR_epoll_ctl 250
257#define __NR_epoll_wait 251
258#define __NR_remap_file_pages 252
259#define __NR_set_tid_address 253
260#define __NR_timer_create 254
261#define __NR_timer_settime 255
262#define __NR_timer_gettime 256
263#define __NR_timer_getoverrun 257
264#define __NR_timer_delete 258
265#define __NR_clock_settime 259
266#define __NR_clock_gettime 260
267#define __NR_clock_getres 261
268#define __NR_clock_nanosleep 262
269#define __NR_statfs64 263
270#define __NR_fstatfs64 264
271#define __NR_tgkill 265
272#define __NR_utimes 266
273#define __NR_fadvise64_64 267
274#define __NR_mbind 268
275#define __NR_get_mempolicy 269
276#define __NR_set_mempolicy 270
277#define __NR_mq_open 271
278#define __NR_mq_unlink 272
279#define __NR_mq_timedsend 273
280#define __NR_mq_timedreceive 274
281#define __NR_mq_notify 275
282#define __NR_mq_getsetattr 276
283#define __NR_waitid 277
284#define __NR_vserver 278
285#define __NR_add_key 279
286#define __NR_request_key 280
287#define __NR_keyctl 281
288#define __NR_ioprio_set 282
289#define __NR_ioprio_get 283
290#define __NR_inotify_init 284
291#define __NR_inotify_add_watch 285
292#define __NR_inotify_rm_watch 286
293#define __NR_migrate_pages 287
294#define __NR_openat 288
295#define __NR_mkdirat 289
296#define __NR_mknodat 290
297#define __NR_fchownat 291
298#define __NR_futimesat 292
299#define __NR_fstatat64 293
300#define __NR_unlinkat 294
301#define __NR_renameat 295
302#define __NR_linkat 296
303#define __NR_symlinkat 297
304#define __NR_readlinkat 298
305#define __NR_fchmodat 299
306#define __NR_faccessat 300
307#define __NR_pselect6 301
308#define __NR_ppoll 302
309#define __NR_unshare 303
310#define __NR_set_robust_list 304
311#define __NR_get_robust_list 305
312#define __NR_splice 306
313#define __NR_sync_file_range 307
314#define __NR_tee 308
315#define __NR_vmsplice 309
316#define __NR_move_pages 310
317#define __NR_sched_setaffinity 311
318#define __NR_sched_getaffinity 312
319#define __NR_kexec_load 313
320#define __NR_getcpu 314
321#define __NR_epoll_pwait 315
322#define __NR_utimensat 316
323#define __NR_signalfd 317
324#define __NR_timerfd_create 318
325#define __NR_eventfd 319
326#define __NR_fallocate 320
327#define __NR_timerfd_settime 321
328#define __NR_timerfd_gettime 322
329
330#ifdef __KERNEL__
331
332#define NR_syscalls 323
333
334#define __ARCH_WANT_IPC_PARSE_VERSION
335#define __ARCH_WANT_OLD_READDIR
336#define __ARCH_WANT_OLD_STAT
337#define __ARCH_WANT_STAT64
338#define __ARCH_WANT_SYS_ALARM
339#define __ARCH_WANT_SYS_GETHOSTNAME
340#define __ARCH_WANT_SYS_PAUSE
341#define __ARCH_WANT_SYS_SGETMASK
342#define __ARCH_WANT_SYS_SIGNAL
343#define __ARCH_WANT_SYS_TIME
344#define __ARCH_WANT_SYS_UTIME
345#define __ARCH_WANT_SYS_WAITPID
346#define __ARCH_WANT_SYS_SOCKETCALL
347#define __ARCH_WANT_SYS_FADVISE64
348#define __ARCH_WANT_SYS_GETPGRP
349#define __ARCH_WANT_SYS_LLSEEK
350#define __ARCH_WANT_SYS_NICE
351#define __ARCH_WANT_SYS_OLD_GETRLIMIT
352#define __ARCH_WANT_SYS_OLDUMOUNT
353#define __ARCH_WANT_SYS_SIGPENDING
354#define __ARCH_WANT_SYS_SIGPROCMASK
355#define __ARCH_WANT_SYS_RT_SIGACTION
356
357/*
358 * "Conditional" syscalls
359 *
360 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
361 * but it doesn't work on all toolchains, so we just do it by hand
362 */
363#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
364
365#endif /* __KERNEL__ */
366#endif /* _ASM_M68K_UNISTD_H_ */
diff --git a/arch/m68knommu/include/asm/user.h b/arch/m68knommu/include/asm/user.h
new file mode 100644
index 000000000000..a5a555b761c4
--- /dev/null
+++ b/arch/m68knommu/include/asm/user.h
@@ -0,0 +1 @@
#include <asm-m68k/user.h>