m68knommu: support ColdFire caches that do copyback and write-through

The version 3 and version 4 ColdFire cache controllers support both
write-through and copy-back modes on the data cache. Allow for Kconfig
time configuration of this, and set the cache mode appropriately.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

2 files changed, 11 insertions, 1 deletions

diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index 74c81c9b177e..d8b8dd68368f 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -53,6 +53,12 @@
  * CACR is cache inhibited, we use the ACR register to set cacheing
  * enabled on the regions we want (eg RAM).
  */
+#if defined(CONFIG_CACHE_COPYBACK)
+#define CACHE_TYPE      ACR_CM_CB
+#else
+#define CACHE_TYPE      ACR_CM_WT
+#endif
+
 #ifdef CONFIG_COLDFIRE_SW_A7
 #define CACHE_MODE      (CACR_EC + CACR_ESB + CACR_DCM_PRE)
 #else
@@ -63,7 +69,7 @@
 
 #define ACR0_MODE       ((CONFIG_RAMBASE & 0xff000000) + \
                          (0x000f0000) + \
-                         (ACR_ENABLE + ACR_ANY + ACR_CM_CB))
+                         (ACR_ENABLE + ACR_ANY + CACHE_TYPE))
 #define ACR1_MODE       0
 
 /****************************************************************************/
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 6bce82fdb9c3..29d4713f796b 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -73,7 +73,11 @@
 #else
 #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
 #endif
+#if defined(CONFIG_CACHE_COPYBACK)
+#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
+#else
 #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
+#endif
 #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
 
 #define CACHE_INIT      (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)