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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 22:02:36 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 22:02:36 -0400
commite34551339a195aa548eaf698523714a8fe7f1984 (patch)
tree8319ac8492bc1bf6dd6182cbcb9002b2aeb82d63 /arch/m68k
parent242e5d06be2ad2633c85313a37862e03f4450a46 (diff)
parent47e0c7e128afb85cf4fb7792e6e7fcb91e2a5cc4 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (41 commits) m68knommu: external interrupt support to ColdFire intc-simr controller m68knommu: external interrupt support to ColdFire intc-2 controller m68knommu: remove ColdFire CLOCK_DIV config option m68knommu: fix gpio warnings for ColdFire 5407 targets m68knommu: fix gpio warnings for ColdFire 532x targets m68knommu: fix gpio warnings for ColdFire 5307 targets m68knommu: fix gpio warnings for ColdFire 527x targets m68knommu: fix gpio warnings for ColdFire 5272 targets m68knommu: fix gpio warnings for ColdFire 5249 targets m68knommu: fix gpio warnings for ColdFire 523x targets m68knommu: fix gpio warnings for ColdFire 520x targets m68knommu: fix gpio warnings for ColdFire 5206e targets m68knommu: fix gpio warnings for ColdFire 5206 targets m68knommu: fixing compiler warnings m68knommu: limit interrupts supported by ColdFire intc-simr driver m68knommu: move some init code out of unmask routine for ColdFire intc-2 m68knommu: limit interrupts supported by ColdFire intc-2 driver m68knommu: add basic support for the ColdFire based FireBee board m68knommu: make ColdFire internal peripheral region configurable m68knommu: clean up definitions of ColdFire peripheral base registers ...
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/coldfire.h42
-rw-r--r--arch/m68k/include/asm/m5206sim.h23
-rw-r--r--arch/m68k/include/asm/m520xsim.h50
-rw-r--r--arch/m68k/include/asm/m523xsim.h52
-rw-r--r--arch/m68k/include/asm/m5249sim.h30
-rw-r--r--arch/m68k/include/asm/m5272sim.h8
-rw-r--r--arch/m68k/include/asm/m527xsim.h68
-rw-r--r--arch/m68k/include/asm/m528xsim.h44
-rw-r--r--arch/m68k/include/asm/m5307sim.h25
-rw-r--r--arch/m68k/include/asm/m532xsim.h9
-rw-r--r--arch/m68k/include/asm/m5407sim.h25
-rw-r--r--arch/m68k/include/asm/m54xxsim.h14
-rw-r--r--arch/m68k/include/asm/mcfdma.h23
-rw-r--r--arch/m68k/include/asm/mcfpit.h16
-rw-r--r--arch/m68k/include/asm/mcftimer.h23
15 files changed, 285 insertions, 167 deletions
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 213028cbe110..c94557b91448 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -14,39 +14,35 @@
14 14
15 15
16/* 16/*
17 * Define master clock frequency. This is essentially done at config 17 * Define master clock frequency. This is done at config time now.
18 * time now. No point enumerating dozens of possible clock options 18 * No point enumerating dozens of possible clock options here. And
19 * here. Also the peripheral clock (bus clock) divide ratio is set 19 * in any case new boards come along from time to time that have yet
20 * at config time too. 20 * another different clocking frequency.
21 */ 21 */
22#ifdef CONFIG_CLOCK_SET 22#ifdef CONFIG_CLOCK_SET
23#define MCF_CLK CONFIG_CLOCK_FREQ 23#define MCF_CLK CONFIG_CLOCK_FREQ
24#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
25#else 24#else
26#error "Don't know what your ColdFire CPU clock frequency is??" 25#error "Don't know what your ColdFire CPU clock frequency is??"
27#endif 26#endif
28 27
29/* 28/*
30 * Define the processor support peripherals base address. 29 * Define the processor internal peripherals base address.
31 * This is generally setup by the boards start up code. 30 *
31 * The majority of ColdFire parts use an MBAR register to set
32 * the base address. Some have an IPSBAR register instead, and it
33 * has slightly different rules on its size and alignment. Some
34 * parts have fixed addresses and the internal peripherals cannot
35 * be relocated in the CPU address space.
36 *
37 * The value of MBAR or IPSBAR is config time selectable, we no
38 * longer hard define it here. No MBAR or IPSBAR will be defined if
39 * this part has a fixed peripheral address map.
32 */ 40 */
33#define MCF_MBAR 0x10000000 41#ifdef CONFIG_MBAR
34#define MCF_MBAR2 0x80000000 42#define MCF_MBAR CONFIG_MBAR
35#if defined(CONFIG_M54xx)
36#define MCF_IPSBAR MCF_MBAR
37#elif defined(CONFIG_M520x)
38#define MCF_IPSBAR 0xFC000000
39#else
40#define MCF_IPSBAR 0x40000000
41#endif 43#endif
42 44#ifdef CONFIG_IPSBAR
43#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 45#define MCF_IPSBAR CONFIG_IPSBAR
44 defined(CONFIG_M520x)
45#undef MCF_MBAR
46#define MCF_MBAR MCF_IPSBAR
47#elif defined(CONFIG_M532x)
48#undef MCF_MBAR
49#define MCF_MBAR 0x00000000
50#endif 46#endif
51 47
52/****************************************************************************/ 48/****************************************************************************/
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 561b03b5ddf8..9015eadd5c00 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -14,6 +14,7 @@
14 14
15#define CPU_NAME "COLDFIRE(m5206)" 15#define CPU_NAME "COLDFIRE(m5206)"
16#define CPU_INSTR_PER_JIFFY 3 16#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK MCF_CLK
17 18
18#include <asm/m52xxacr.h> 19#include <asm/m52xxacr.h>
19 20
@@ -48,14 +49,14 @@
48#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ 49#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
49#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ 50#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
50 51
51#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ 52#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
52#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ 53#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
53#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */ 54#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
54#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ 55#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
55#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */ 56#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
56#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */ 57#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
57#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 58#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
58#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */ 59#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
59 60
60#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ 61#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
61#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ 62#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
@@ -89,9 +90,15 @@
89#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ 90#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
90#endif 91#endif
91 92
93#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
94#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
95
92#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ 96#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
93#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ 97#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
94 98
99#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
101
95#if defined(CONFIG_NETtel) 102#if defined(CONFIG_NETtel)
96#define MCFUART_BASE1 0x180 /* Base address of UART1 */ 103#define MCFUART_BASE1 0x180 /* Base address of UART1 */
97#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 104#define MCFUART_BASE2 0x140 /* Base address of UART2 */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 88ed8239fe4e..55d5a4c5fe0b 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -13,13 +13,14 @@
13 13
14#define CPU_NAME "COLDFIRE(m520x)" 14#define CPU_NAME "COLDFIRE(m520x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 520x SIM register set addresses. 21 * Define the 520x SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
23#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
24#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
25#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -35,9 +36,9 @@
35 * address to the SIMR and CIMR registers (not offsets into IPSBAR). 36 * address to the SIMR and CIMR registers (not offsets into IPSBAR).
36 * The 520x family only has a single INTC unit. 37 * The 520x family only has a single INTC unit.
37 */ 38 */
38#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR) 39#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
39#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR) 40#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
40#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0) 41#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
41#define MCFINTC1_SIMR (0) 42#define MCFINTC1_SIMR (0)
42#define MCFINTC1_CIMR (0) 43#define MCFINTC1_CIMR (0)
43#define MCFINTC1_ICR0 (0) 44#define MCFINTC1_ICR0 (0)
@@ -52,19 +53,22 @@
52/* 53/*
53 * SDRAM configuration registers. 54 * SDRAM configuration registers.
54 */ 55 */
55#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ 56#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
56#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ 57#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
57#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ 58#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
58#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ 59#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
59#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 60#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
60#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 61#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
61 62
62/* 63/*
63 * EPORT and GPIO registers. 64 * EPORT and GPIO registers.
64 */ 65 */
66#define MCFEPORT_EPPAR 0xFC088000
65#define MCFEPORT_EPDDR 0xFC088002 67#define MCFEPORT_EPDDR 0xFC088002
68#define MCFEPORT_EPIER 0xFC088003
66#define MCFEPORT_EPDR 0xFC088004 69#define MCFEPORT_EPDR 0xFC088004
67#define MCFEPORT_EPPDR 0xFC088005 70#define MCFEPORT_EPPDR 0xFC088005
71#define MCFEPORT_EPFR 0xFC088006
68 72
69#define MCFGPIO_PODR_BUSCTL 0xFC0A4000 73#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
70#define MCFGPIO_PODR_BE 0xFC0A4001 74#define MCFGPIO_PODR_BE 0xFC0A4001
@@ -119,10 +123,10 @@
119#define MCFGPIO_IRQ_MAX 8 123#define MCFGPIO_IRQ_MAX 8
120#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 124#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
121 125
122#define MCF_GPIO_PAR_UART (0xA4036) 126#define MCF_GPIO_PAR_UART 0xFC0A4036
123#define MCF_GPIO_PAR_FECI2C (0xA4033) 127#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
124#define MCF_GPIO_PAR_QSPI (0xA4034) 128#define MCF_GPIO_PAR_QSPI 0xFC0A4034
125#define MCF_GPIO_PAR_FEC (0xA4038) 129#define MCF_GPIO_PAR_FEC 0xFC0A4038
126 130
127#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 131#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
128#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 132#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
@@ -134,11 +138,23 @@
134#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 138#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
135 139
136/* 140/*
141 * PIT timer module.
142 */
143#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
144#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
145
146/*
137 * UART module. 147 * UART module.
138 */ 148 */
139#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ 149#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
140#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ 150#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
141#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ 151#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
152
153/*
154 * FEC module.
155 */
156#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
157#define MCFFEC_SIZE 0x800 /* Register set size */
142 158
143/* 159/*
144 * Reset Controll Unit. 160 * Reset Controll Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 4ad7a00257a8..8996df62ede4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -13,14 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m523x)" 14#define CPU_NAME "COLDFIRE(m523x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 523x SIM register set addresses. 21 * Define the 523x SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ 24#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
25
24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -39,11 +41,11 @@
39/* 41/*
40 * SDRAM configuration registers. 42 * SDRAM configuration registers.
41 */ 43 */
42#define MCFSIM_DCR 0x44 /* SDRAM control */ 44#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
43#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 45#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
44#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 46#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
45#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 47#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
46#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
47 49
48/* 50/*
49 * Reset Controll Unit (relative to IPSBAR). 51 * Reset Controll Unit (relative to IPSBAR).
@@ -57,10 +59,19 @@
57/* 59/*
58 * UART module. 60 * UART module.
59 */ 61 */
60#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 62#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
61#define MCFUART_BASE2 0x240 /* Base address of UART2 */ 63#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
62#define MCFUART_BASE3 0x280 /* Base address of UART3 */ 64#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
65
66/*
67 * FEC ethernet module.
68 */
69#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
70#define MCFFEC_SIZE 0x800
63 71
72/*
73 * GPIO module.
74 */
64#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 75#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
65#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 76#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
66#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 77#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
@@ -118,12 +129,22 @@
118#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) 129#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
119 130
120/* 131/*
121 * EPort 132 * PIT timer base addresses.
122 */ 133 */
134#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
135#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
136#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
137#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
123 138
139/*
140 * EPort
141 */
142#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
124#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 143#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
144#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
125#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 145#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
126#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 146#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
147#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
127 148
128/* 149/*
129 * Generic GPIO support 150 * Generic GPIO support
@@ -143,5 +164,14 @@
143*/ 164*/
144#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 165#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
145#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 166#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
167
168/*
169 * DMA unit base addresses.
170 */
171#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
172#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
173#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
174#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
175
146/****************************************************************************/ 176/****************************************************************************/
147#endif /* m523xsim_h */ 177#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 4908b118f2fd..805714ca8d7d 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -13,10 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m5249)" 14#define CPU_NAME "COLDFIRE(m5249)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
21 * The 5249 has a second MBAR region, define its address.
22 */
23#define MCF_MBAR2 0x80000000
24
25/*
20 * Define the 5249 SIM register set addresses. 26 * Define the 5249 SIM register set addresses.
21 */ 27 */
22#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 28#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
@@ -55,11 +61,17 @@
55#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 61#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
56#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 62#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
57 63
58#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ 64#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
59#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ 65#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
60#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ 66#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
61#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 67#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
62#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 68#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
69
70/*
71 * Timer module.
72 */
73#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
74#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
63 75
64/* 76/*
65 * UART module. 77 * UART module.
@@ -68,6 +80,14 @@
68#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 80#define MCFUART_BASE2 0x200 /* Base address of UART2 */
69 81
70/* 82/*
83 * DMA unit base addresses.
84 */
85#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
86#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
87#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
88#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
89
90/*
71 * Some symbol defines for the above... 91 * Some symbol defines for the above...
72 */ 92 */
73#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 93#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index b7cc50abc831..759c2b07a994 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -14,6 +14,7 @@
14 14
15#define CPU_NAME "COLDFIRE(m5272)" 15#define CPU_NAME "COLDFIRE(m5272)"
16#define CPU_INSTR_PER_JIFFY 3 16#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK MCF_CLK
17 18
18#include <asm/m52xxacr.h> 19#include <asm/m52xxacr.h>
19 20
@@ -80,6 +81,13 @@
80#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ 81#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
81#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ 82#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
82 83
84#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
85
86#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
87#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
90
83/* 91/*
84 * Define system peripheral IRQ usage. 92 * Define system peripheral IRQ usage.
85 */ 93 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index e8042e8bc003..74855a66c050 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -13,14 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m527x)" 14#define CPU_NAME "COLDFIRE(m527x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 5270/5271 SIM register set addresses. 21 * Define the 5270/5271 SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ 24#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
25
24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -42,29 +44,45 @@
42 * SDRAM configuration registers. 44 * SDRAM configuration registers.
43 */ 45 */
44#ifdef CONFIG_M5271 46#ifdef CONFIG_M5271
45#define MCFSIM_DCR 0x40 /* SDRAM control */ 47#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
46#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 48#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
47#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 49#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
48#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 50#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
49#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 51#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
50#endif 52#endif
51#ifdef CONFIG_M5275 53#ifdef CONFIG_M5275
52#define MCFSIM_DMR 0x40 /* SDRAM mode */ 54#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
53#define MCFSIM_DCR 0x44 /* SDRAM control */ 55#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
54#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ 56#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
55#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ 57#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
56#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ 58#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
57#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ 59#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
58#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ 60#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
59#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ 61#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
60#endif 62#endif
61 63
62/* 64/*
65 * DMA unit base addresses.
66 */
67#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
68#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
69#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
70#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
71
72/*
63 * UART module. 73 * UART module.
64 */ 74 */
65#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 75#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
66#define MCFUART_BASE2 0x240 /* Base address of UART2 */ 76#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
67#define MCFUART_BASE3 0x280 /* Base address of UART3 */ 77#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
78
79/*
80 * FEC ethernet module.
81 */
82#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
83#define MCFFEC_SIZE0 0x800
84#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
85#define MCFFEC_SIZE1 0x800
68 86
69#ifdef CONFIG_M5271 87#ifdef CONFIG_M5271
70#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 88#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
@@ -231,14 +249,22 @@
231#endif 249#endif
232 250
233/* 251/*
234 * EPort 252 * PIT timer base addresses.
235 */ 253 */
254#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
255#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
256#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
257#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
236 258
259/*
260 * EPort
261 */
262#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
237#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 263#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
264#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
238#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 265#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
239#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 266#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
240 267#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
241
242 268
243/* 269/*
244 * GPIO pins setups to enable the UARTs. 270 * GPIO pins setups to enable the UARTs.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a6d2f4d9aaa0..d798bd5df56c 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -13,14 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m528x)" 14#define CPU_NAME "COLDFIRE(m528x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK MCF_CLK
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 5280/5282 SIM register set addresses. 21 * Define the 5280/5282 SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ 24#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
25
24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -39,18 +41,32 @@
39/* 41/*
40 * SDRAM configuration registers. 42 * SDRAM configuration registers.
41 */ 43 */
42#define MCFSIM_DCR 0x44 /* SDRAM control */ 44#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
43#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 45#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
44#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 46#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
45#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 47#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
46#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
49
50/*
51 * DMA unit base addresses.
52 */
53#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
54#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
55#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
56#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
47 57
48/* 58/*
49 * UART module. 59 * UART module.
50 */ 60 */
51#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 61#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
52#define MCFUART_BASE2 0x240 /* Base address of UART2 */ 62#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
53#define MCFUART_BASE3 0x280 /* Base address of UART3 */ 63#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
64
65/*
66 * FEC ethernet module.
67 */
68#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
69#define MCFFEC_SIZE 0x800
54 70
55/* 71/*
56 * GPIO registers 72 * GPIO registers
@@ -163,6 +179,14 @@
163#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) 179#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
164 180
165/* 181/*
182 * PIT timer base addresses.
183 */
184#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
185#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
186#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
187#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
188
189/*
166 * Edge Port registers 190 * Edge Port registers
167 */ 191 */
168#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) 192#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 0bf57397e7a9..4c94c01f36c4 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -16,6 +16,7 @@
16 16
17#define CPU_NAME "COLDFIRE(m5307)" 17#define CPU_NAME "COLDFIRE(m5307)"
18#define CPU_INSTR_PER_JIFFY 3 18#define CPU_INSTR_PER_JIFFY 3
19#define MCF_BUSCLK (MCF_CLK / 2)
19 20
20#include <asm/m53xxacr.h> 21#include <asm/m53xxacr.h>
21 22
@@ -89,16 +90,30 @@
89#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 90#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
90#endif /* CONFIG_OLDMASK */ 91#endif /* CONFIG_OLDMASK */
91 92
92#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ 93#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
93#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ 94#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
94#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ 95#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
95#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 96#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
96#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 97#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
98
99/*
100 * Timer module.
101 */
102#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
103#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
97 104
98#define MCFSIM_PADDR (MCF_MBAR + 0x244) 105#define MCFSIM_PADDR (MCF_MBAR + 0x244)
99#define MCFSIM_PADAT (MCF_MBAR + 0x248) 106#define MCFSIM_PADAT (MCF_MBAR + 0x248)
100 107
101/* 108/*
109 * DMA unit base addresses.
110 */
111#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
112#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
113#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
114#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
115
116/*
102 * UART module. 117 * UART module.
103 */ 118 */
104#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index e6470f8ca324..ba4cc784f574 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -11,6 +11,7 @@
11 11
12#define CPU_NAME "COLDFIRE(m532x)" 12#define CPU_NAME "COLDFIRE(m532x)"
13#define CPU_INSTR_PER_JIFFY 3 13#define CPU_INSTR_PER_JIFFY 3
14#define MCF_BUSCLK (MCF_CLK / 3)
14 15
15#include <asm/m53xxacr.h> 16#include <asm/m53xxacr.h>
16 17
@@ -85,6 +86,14 @@
85#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 86#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
86#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ 87#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
87 88
89/*
90 * Timer module.
91 */
92#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
93#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
94#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
95#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
96
88/********************************************************************* 97/*********************************************************************
89 * 98 *
90 * Reset Controller Module 99 * Reset Controller Module
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 75f5c28a551d..762c58c89050 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -16,6 +16,7 @@
16 16
17#define CPU_NAME "COLDFIRE(m5407)" 17#define CPU_NAME "COLDFIRE(m5407)"
18#define CPU_INSTR_PER_JIFFY 3 18#define CPU_INSTR_PER_JIFFY 3
19#define MCF_BUSCLK (MCF_CLK / 2)
19 20
20#include <asm/m54xxacr.h> 21#include <asm/m54xxacr.h>
21 22
@@ -72,11 +73,17 @@
72#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ 73#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
73#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 74#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
74 75
75#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ 76#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
76#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ 77#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
77#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ 78#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
78#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 79#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
79#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 80#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
81
82/*
83 * Timer module.
84 */
85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
80 87
81#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 88#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
82#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 89#define MCFUART_BASE2 0x200 /* Base address of UART2 */
@@ -85,6 +92,14 @@
85#define MCFSIM_PADAT (MCF_MBAR + 0x248) 92#define MCFSIM_PADAT (MCF_MBAR + 0x248)
86 93
87/* 94/*
95 * DMA unit base addresses.
96 */
97#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
98#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
99#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
100#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
101
102/*
88 * Generic GPIO support 103 * Generic GPIO support
89 */ 104 */
90#define MCFGPIO_PIN_MAX 16 105#define MCFGPIO_PIN_MAX 16
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 462ae5328441..1ed8bfb02772 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -7,6 +7,7 @@
7 7
8#define CPU_NAME "COLDFIRE(m54xx)" 8#define CPU_NAME "COLDFIRE(m54xx)"
9#define CPU_INSTR_PER_JIFFY 2 9#define CPU_INSTR_PER_JIFFY 2
10#define MCF_BUSCLK (MCF_CLK / 2)
10 11
11#include <asm/m54xxacr.h> 12#include <asm/m54xxacr.h>
12 13
@@ -15,7 +16,8 @@
15/* 16/*
16 * Interrupt Controller Registers 17 * Interrupt Controller Registers
17 */ 18 */
18#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ 19#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
20
19#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 21#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
20#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 22#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
21#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 23#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -48,6 +50,16 @@
48#define MCFGPIO_IRQ_VECBASE -1 50#define MCFGPIO_IRQ_VECBASE -1
49 51
50/* 52/*
53 * EDGE Port support.
54 */
55#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
56#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
57#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
58#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
59#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
60#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
61
62/*
51 * Some PSC related definitions 63 * Some PSC related definitions
52 */ 64 */
53#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) 65#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h
index 705c52c79cd8..10bc7e391c14 100644
--- a/arch/m68k/include/asm/mcfdma.h
+++ b/arch/m68k/include/asm/mcfdma.h
@@ -11,29 +11,6 @@
11#define mcfdma_h 11#define mcfdma_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14
15/*
16 * Get address specific defines for this Coldfire member.
17 */
18#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
19#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
20#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
21#elif defined(CONFIG_M5272)
22#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */
23#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
24/* These are relative to the IPSBAR, not MBAR */
25#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */
26#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */
27#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */
28#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */
29#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
30#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
31#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
32#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
33#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
34#endif
35
36
37#if !defined(CONFIG_M5272) 14#if !defined(CONFIG_M5272)
38 15
39/* 16/*
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h
index f570cf64fd29..9fd321ca0725 100644
--- a/arch/m68k/include/asm/mcfpit.h
+++ b/arch/m68k/include/asm/mcfpit.h
@@ -11,22 +11,8 @@
11#define mcfpit_h 11#define mcfpit_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14
15/*
16 * Get address specific defines for the 5270/5271, 5280/5282, and 5208.
17 */
18#if defined(CONFIG_M520x)
19#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
20#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
21#else
22#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
23#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
24#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
25#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
26#endif
27
28/* 14/*
29 * Define the PIT timer register set addresses. 15 * Define the PIT timer register address offsets.
30 */ 16 */
31#define MCFPIT_PCSR 0x0 /* PIT control register */ 17#define MCFPIT_PCSR 0x0 /* PIT control register */
32#define MCFPIT_PMR 0x2 /* PIT modulus register */ 18#define MCFPIT_PMR 0x2 /* PIT modulus register */
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 0f90f6d2227a..92b276fe8240 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -12,29 +12,6 @@
12#define mcftimer_h 12#define mcftimer_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15
16/*
17 * Get address specific defines for this ColdFire member.
18 */
19#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
20#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
21#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
22#elif defined(CONFIG_M5272)
23#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
24#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
25#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
26#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
27#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
28#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
29#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
30#elif defined(CONFIG_M532x)
31#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */
32#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */
33#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */
34#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */
35#endif
36
37
38/* 15/*
39 * Define the TIMER register set addresses. 16 * Define the TIMER register set addresses.
40 */ 17 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 09:24:21 -0500