m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx

The ColdFire 54xx family shares the same interrupt controller used
on the 523x, 527x and 528x ColdFire parts, but it isn't offset
relative to the IPSBAR register. The 54xx doesn't have an IPSBAR
register.

By including the base address of the peripheral registers in the register
definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid
having to define a fake IPSBAR for the 54xx. And this makes the register
address definitions of these more consistent, the majority of the other
register address defines include the peripheral base address already.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

5 files changed, 12 insertions, 10 deletions

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index d70cf0f1c40a..91676454731b 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -31,9 +31,7 @@
  *      This is generally setup by the boards start up code.
  */
 #define MCF_MBAR        0x10000000
-#if defined(CONFIG_M54xx)
-#define MCF_IPSBAR      MCF_MBAR
-#elif defined(CONFIG_M520x)
+#if defined(CONFIG_M520x)
 #define MCF_IPSBAR      0xFC000000
 #else
 #define MCF_IPSBAR      0x40000000
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 4ad7a00257a8..9701ed34d234 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -19,8 +19,9 @@
 /*
  *      Define the 523x SIM register set addresses.
  */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0            (MCF_IPSBAR + 0x0c00)   /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1            (MCF_IPSBAR + 0x0d00)   /* Base for Interrupt Ctrl 0 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index e8042e8bc003..3712f611bd5e 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -19,8 +19,9 @@
 /*
  *      Define the 5270/5271 SIM register set addresses.
  */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 1 */
+#define MCFICM_INTC0            (MCF_IPSBAR + 0x0c00)   /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1            (MCF_IPSBAR + 0x0d00)   /* Base for Interrupt Ctrl 1 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a6d2f4d9aaa0..a918545f6a5a 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -19,8 +19,9 @@
 /*
  *      Define the 5280/5282 SIM register set addresses.
  */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0            (MCF_IPSBAR + 0x0c00)   /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1            (MCF_IPSBAR + 0x0d00)   /* Base for Interrupt Ctrl 0 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 462ae5328441..cc5d94d215b4 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -15,7 +15,8 @@
 /*
  *      Interrupt Controller Registers
  */
-#define MCFICM_INTC0            0x0700          /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0            (MCF_MBAR + 0x700)      /* Base for Interrupt Ctrl 0 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */