diff options
author | Greg Ungerer <gerg@uclinux.org> | 2009-05-21 23:33:35 -0400 |
---|---|---|
committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-15 19:43:52 -0400 |
commit | 39f0fb6a3448cfc316e0d5295ed1b121db50037e (patch) | |
tree | 657db8073835e8d499708a898a36f1d3a1e39a32 /arch/m68k | |
parent | f6a66276f5fdc018d2a9378c71de3bae13c588d7 (diff) |
m68knommu: map ColdFire interrupts to correct masking bits
The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r-- | arch/m68k/include/asm/mcfintc.h | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/m68k/include/asm/mcfintc.h b/arch/m68k/include/asm/mcfintc.h index 213aa6c68abb..4183320a3813 100644 --- a/arch/m68k/include/asm/mcfintc.h +++ b/arch/m68k/include/asm/mcfintc.h | |||
@@ -25,11 +25,6 @@ | |||
25 | */ | 25 | */ |
26 | 26 | ||
27 | /* | 27 | /* |
28 | * Define the base address of the SIM within the MBAR address space. | ||
29 | */ | ||
30 | #define MCFSIM_BASE 0x0 /* Base address within SIM */ | ||
31 | |||
32 | /* | ||
33 | * Bit definitions for the ICR family of registers. | 28 | * Bit definitions for the ICR family of registers. |
34 | */ | 29 | */ |
35 | #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ | 30 | #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ |
@@ -48,7 +43,9 @@ | |||
48 | #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ | 43 | #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ |
49 | 44 | ||
50 | /* | 45 | /* |
51 | * IMR bit position definitions. | 46 | * IMR bit position definitions. Not all ColdFire parts with this interrupt |
47 | * controller actually support all of these interrupt sources. But the bit | ||
48 | * numbers are the same in all cores. | ||
52 | */ | 49 | */ |
53 | #define MCFINTC_EINT1 1 /* External int #1 */ | 50 | #define MCFINTC_EINT1 1 /* External int #1 */ |
54 | #define MCFINTC_EINT2 2 /* External int #2 */ | 51 | #define MCFINTC_EINT2 2 /* External int #2 */ |
@@ -70,6 +67,19 @@ | |||
70 | #define MCFINTC_QSPI 18 | 67 | #define MCFINTC_QSPI 18 |
71 | 68 | ||
72 | #ifndef __ASSEMBLER__ | 69 | #ifndef __ASSEMBLER__ |
70 | |||
71 | /* | ||
72 | * There is no one-is-one correspondance between the interrupt number (irq) | ||
73 | * and the bit fields on the mask register. So we create a per-cpu type | ||
74 | * mapping of irq to mask bit. The CPU platform code needs to register | ||
75 | * its supported irq's at init time, using this function. | ||
76 | */ | ||
77 | extern unsigned char mcf_irq2imr[]; | ||
78 | static inline void mcf_mapirq2imr(int irq, int imr) | ||
79 | { | ||
80 | mcf_irq2imr[irq] = imr; | ||
81 | } | ||
82 | |||
73 | void mcf_autovector(int irq); | 83 | void mcf_autovector(int irq); |
74 | void mcf_setimr(int index); | 84 | void mcf_setimr(int index); |
75 | void mcf_clrimr(int index); | 85 | void mcf_clrimr(int index); |