m68knommu: general interrupt controller for ColdFire 532x parts

The ColdFire 532x family of parts uses 2 of the same INTC interrupt
controlers used in the ColdFire 520x family. So modify the code to
support both parts. The extra code for the second INTC controler in
the case of the 520x is easily optimized away to nothing.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

2 files changed, 23 insertions, 10 deletions

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index e79b9bc76a12..91de39c8d865 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -11,9 +11,8 @@
 #define m520xsim_h
 /****************************************************************************/
 
-
 /*
- *  Define the 5282 SIM register set addresses.
+ *  Define the 520x SIM register set addresses.
  */
 #define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
 #define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
@@ -26,6 +25,18 @@
 #define MCFINTC_CIMR        0x1d        /* Clear interrupt mask 0-63 */
 #define MCFINTC_ICR0        0x40        /* Base ICR register */
 
+/*
+ *  The common interrupt controller code just wants to know the absolute
+ *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
+ *  The 520x family only has a single INTC unit.
+ */
+#define MCFINTC0_SIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
+#define MCFINTC0_CIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
+#define MCFINTC0_ICR0       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
+#define MCFINTC1_SIMR       (0)
+#define MCFINTC1_CIMR       (0)
+#define MCFINTC1_ICR0       (0)
+
 #define MCFINT_VECBASE      64
 #define MCFINT_UART0        26          /* Interrupt number for UART0 */
 #define MCFINT_UART1        27          /* Interrupt number for UART1 */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 3e80810b3784..41c57e0f445a 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -58,10 +58,12 @@
 
 #define MCFSIM_IMR_MASKALL      0xFFFFFFFF      /* All SIM intr sources */
 
-#define MCFSIM_IMR_SIMR0        0xFC04801C
-#define MCFSIM_IMR_SIMR1        0xFC04C01C
-#define MCFSIM_IMR_CIMR0        0xFC04801D
-#define MCFSIM_IMR_CIMR1        0xFC04C01D
+#define MCFINTC0_SIMR           0xFC04801C
+#define MCFINTC0_CIMR           0xFC04801D
+#define MCFINTC0_ICR0           0xFC048040
+#define MCFINTC1_SIMR           0xFC04C01C
+#define MCFINTC1_CIMR           0xFC04C01D
+#define MCFINTC1_ICR0           0xFC04C040
 
 #define MCFSIM_ICR_TIMER1       (0xFC048040+32)
 #define MCFSIM_ICR_TIMER2       (0xFC048040+33)
@@ -87,16 +89,16 @@
 
 
 #define mcf_enable_irq0(irq)            \
-        *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq);
+        *((volatile unsigned char *) (MCFINTC0_CIMR)) = (irq);
 
 #define mcf_enable_irq1(irq)            \
-        *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq);
+        *((volatile unsigned char *) (MCFINTC1_CIMR)) = (irq);
 
 #define mcf_disable_irq0(irq)           \
-        *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq);
+        *((volatile unsigned char *) (MCFINTC0_SIMR)) = (irq);
 
 #define mcf_disable_irq1(irq)           \
-        *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq);
+        *((volatile unsigned char *) (MCFINTC1_SIMR)) = (irq);
 
 /*
  *      Define the Cache register flags.