diff options
author | sfking@fdwdc.com <sfking@fdwdc.com> | 2009-06-19 21:11:04 -0400 |
---|---|---|
committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-09 22:01:22 -0400 |
commit | a03ce7d9ef05e145ef706f99e68d5ffacf0ad325 (patch) | |
tree | f654f0374276f65f9d61f80204b81949d1845168 /arch/m68k | |
parent | afde8560b4217338c17b7dbc9e9d7676c1b3a5ff (diff) |
generic GPIO support for the Freescale Coldfire 523x.
Add support for the 523x.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r-- | arch/m68k/include/asm/m523xsim.h | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 55183b5df1b8..a34894cf8e6f 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h | |||
@@ -50,5 +50,82 @@ | |||
50 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | 50 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
51 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | 51 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
52 | 52 | ||
53 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) | ||
54 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) | ||
55 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) | ||
56 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) | ||
57 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) | ||
58 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) | ||
59 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) | ||
60 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) | ||
61 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) | ||
62 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) | ||
63 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) | ||
64 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) | ||
65 | #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) | ||
66 | |||
67 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) | ||
68 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) | ||
69 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) | ||
70 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) | ||
71 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) | ||
72 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) | ||
73 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) | ||
74 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) | ||
75 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) | ||
76 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) | ||
77 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) | ||
78 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) | ||
79 | #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) | ||
80 | |||
81 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) | ||
82 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) | ||
83 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) | ||
84 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) | ||
85 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) | ||
86 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) | ||
87 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) | ||
88 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) | ||
89 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) | ||
90 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) | ||
91 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) | ||
92 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) | ||
93 | #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) | ||
94 | |||
95 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) | ||
96 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) | ||
97 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) | ||
98 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) | ||
99 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) | ||
100 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) | ||
101 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) | ||
102 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) | ||
103 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) | ||
104 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) | ||
105 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) | ||
106 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) | ||
107 | #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) | ||
108 | |||
109 | /* | ||
110 | * EPort | ||
111 | */ | ||
112 | |||
113 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) | ||
114 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) | ||
115 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) | ||
116 | |||
117 | /* | ||
118 | * Generic GPIO support | ||
119 | */ | ||
120 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR | ||
121 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR | ||
122 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR | ||
123 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR | ||
124 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR | ||
125 | |||
126 | #define MCFGPIO_PIN_MAX 107 | ||
127 | #define MCFGPIO_IRQ_MAX 8 | ||
128 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | ||
129 | |||
53 | /****************************************************************************/ | 130 | /****************************************************************************/ |
54 | #endif /* m523xsim_h */ | 131 | #endif /* m523xsim_h */ |