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authorGreg Ungerer <gerg@uclinux.org>2009-05-18 23:56:44 -0400
committerGreg Ungerer <gerg@uclinux.org>2009-09-15 19:43:49 -0400
commit5938084bd8843490a4493d19fb108df70d87df2d (patch)
tree9f63d02cf26ae38723a3eb7282ccb84565b3556d /arch/m68k
parente47cc3d6acacffdc673779a44c21a4a12b20db23 (diff)
m68knommu: move ColdFire INTC definitions to new include file
Create an mcfintc.h include file with the definitions for the old style ColdFire interrupt controller. They are only needed on CPU's that use this old controller - so isolate them on their own. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/mcfintc.h106
-rw-r--r--arch/m68k/include/asm/mcfsim.h81
2 files changed, 114 insertions, 73 deletions
diff --git a/arch/m68k/include/asm/mcfintc.h b/arch/m68k/include/asm/mcfintc.h
new file mode 100644
index 000000000000..a75a001e773a
--- /dev/null
+++ b/arch/m68k/include/asm/mcfintc.h
@@ -0,0 +1,106 @@
1/****************************************************************************/
2
3/*
4 * mcfintc.h -- support definitions for the simple ColdFire
5 * Interrupt Controller
6 *
7 * (C) Copyright 2009, Greg Ungerer <gerg@uclinux.org>
8 */
9
10/****************************************************************************/
11#ifndef mcfintc_h
12#define mcfintc_h
13/****************************************************************************/
14
15/*
16 * Most of the older ColdFire parts use the same simple interrupt
17 * controller. This is currently used on the 5206, 5206e, 5249, 5307
18 * and 5407 parts.
19 *
20 * The builtin peripherals are masked through dedicated bits in the
21 * Interrupt Mask register (IMR) - and this is not indexed (or in any way
22 * related to) the actual interrupt number they use. So knowing the IRQ
23 * number doesn't explicitly map to a certain internal device for
24 * interrupt control purposes.
25 */
26
27/*
28 * Define the base address of the SIM within the MBAR address space.
29 */
30#define MCFSIM_BASE 0x0 /* Base address within SIM */
31
32/*
33 * Bit definitions for the ICR family of registers.
34 */
35#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
36#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
37#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
38#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
39#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
40#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
41#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
42#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
43#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
44
45#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
46#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
47#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
48#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
49
50/*
51 * Bit definitions for the ICR family of registers.
52 */
53#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
54#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
55#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
56#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
57#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
58#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
59#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
60#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
61#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
62
63#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
64#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
65#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
66#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
67
68/*
69 * Bit definitions for the Interrupt Mask register (IMR).
70 */
71#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
72#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
73#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
74#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
75#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
76#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
77#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
78
79#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
80#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
81#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
82#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
83#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
84#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
85
86#if defined(CONFIG_M5206e)
87#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
88#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
89#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
90#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
91#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
92#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
93#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
94#endif
95
96/*
97 * Mask for all of the SIM devices. Some parts have more or less
98 * SIM devices. This is a catchall for the sandard set.
99 */
100#ifndef MCFSIM_IMR_MASKALL
101#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
102#endif
103
104
105/****************************************************************************/
106#endif /* mcfintc_h */
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index b90425fb50fe..9c70a67bf85f 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -4,7 +4,7 @@
4 * mcfsim.h -- ColdFire System Integration Module support. 4 * mcfsim.h -- ColdFire System Integration Module support.
5 * 5 *
6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) 6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */ 8 */
9 9
10/****************************************************************************/ 10/****************************************************************************/
@@ -12,19 +12,21 @@
12#define mcfsim_h 12#define mcfsim_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15
16/* 15/*
17 * Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282, 16 * Include the appropriate ColdFire CPU specific System Integration Module
18 * 5307 or 5407 specific addresses. 17 * (SIM) definitions.
19 */ 18 */
20#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) 19#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
21#include <asm/m5206sim.h> 20#include <asm/m5206sim.h>
21#include <asm/mcfintc.h>
22#elif defined(CONFIG_M520x) 22#elif defined(CONFIG_M520x)
23#include <asm/m520xsim.h> 23#include <asm/m520xsim.h>
24#elif defined(CONFIG_M523x) 24#elif defined(CONFIG_M523x)
25#include <asm/m523xsim.h> 25#include <asm/m523xsim.h>
26#include <asm/mcfintc.h>
26#elif defined(CONFIG_M5249) 27#elif defined(CONFIG_M5249)
27#include <asm/m5249sim.h> 28#include <asm/m5249sim.h>
29#include <asm/mcfintc.h>
28#elif defined(CONFIG_M527x) 30#elif defined(CONFIG_M527x)
29#include <asm/m527xsim.h> 31#include <asm/m527xsim.h>
30#elif defined(CONFIG_M5272) 32#elif defined(CONFIG_M5272)
@@ -33,80 +35,13 @@
33#include <asm/m528xsim.h> 35#include <asm/m528xsim.h>
34#elif defined(CONFIG_M5307) 36#elif defined(CONFIG_M5307)
35#include <asm/m5307sim.h> 37#include <asm/m5307sim.h>
38#include <asm/mcfintc.h>
36#elif defined(CONFIG_M532x) 39#elif defined(CONFIG_M532x)
37#include <asm/m532xsim.h> 40#include <asm/m532xsim.h>
38#elif defined(CONFIG_M5407) 41#elif defined(CONFIG_M5407)
39#include <asm/m5407sim.h> 42#include <asm/m5407sim.h>
43#include <asm/mcfintc.h>
40#endif 44#endif
41 45
42
43/*
44 * Define the base address of the SIM within the MBAR address space.
45 */
46#define MCFSIM_BASE 0x0 /* Base address of SIM */
47
48
49/*
50 * Bit definitions for the ICR family of registers.
51 */
52#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
53#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
54#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
55#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
56#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
57#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
58#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
59#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
60#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
61
62#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
63#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
64#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
65#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
66
67/*
68 * Bit definitions for the Interrupt Mask register (IMR).
69 */
70#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
71#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
72#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
73#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
74#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
75#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
76#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
77
78#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
79#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
80#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
81#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
82#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
83#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
84
85#if defined(CONFIG_M5206e)
86#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
87#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
88#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
89#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
90#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
91#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
92#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
93#endif
94
95/*
96 * Mask for all of the SIM devices. Some parts have more or less
97 * SIM devices. This is a catchall for the sandard set.
98 */
99#ifndef MCFSIM_IMR_MASKALL
100#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
101#endif
102
103
104#ifndef __ASSEMBLY__
105/*
106 * Definition for the interrupt auto-vectoring support.
107 */
108extern void mcf_autovector(unsigned int vec);
109#endif /* __ASSEMBLY__ */
110
111/****************************************************************************/ 46/****************************************************************************/
112#endif /* mcfsim_h */ 47#endif /* mcfsim_h */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 17:42:15 -0500