diff options
| author | Luis Alves <ljalvs@gmail.com> | 2013-02-27 16:05:42 -0500 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2013-03-03 20:08:50 -0500 |
| commit | e97e9c98168b5357822ce4d8ed81fdb68aad3c30 (patch) | |
| tree | 7dc0830d83ea7a8302dbcca61b6ecd819d9e3e92 /arch/m68k | |
| parent | be3f695cbe3ddd7f334a660b82ae866818ae4b10 (diff) | |
m68knommu: fix MC68328.h defines
This patch fixes some broken #define's in the MC68328.h file.
Most of them are whitespaces and one is an incorrect define of TCN.
Signed-off-by: Luis Alves <ljalvs@gmail.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
| -rw-r--r-- | arch/m68k/include/asm/MC68328.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h index a337e56d09bf..4ebf098b8a1f 100644 --- a/arch/m68k/include/asm/MC68328.h +++ b/arch/m68k/include/asm/MC68328.h | |||
| @@ -293,7 +293,7 @@ | |||
| 293 | /* | 293 | /* |
| 294 | * Here go the bitmasks themselves | 294 | * Here go the bitmasks themselves |
| 295 | */ | 295 | */ |
| 296 | #define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */ | 296 | #define IMR_MSPIM (1 << SPIM_IRQ_NUM) /* Mask SPI Master interrupt */ |
| 297 | #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ | 297 | #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ |
| 298 | #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ | 298 | #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ |
| 299 | #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ | 299 | #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ |
| @@ -327,7 +327,7 @@ | |||
| 327 | #define IWR_ADDR 0xfffff308 | 327 | #define IWR_ADDR 0xfffff308 |
| 328 | #define IWR LONG_REF(IWR_ADDR) | 328 | #define IWR LONG_REF(IWR_ADDR) |
| 329 | 329 | ||
| 330 | #define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ | 330 | #define IWR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */ |
| 331 | #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ | 331 | #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ |
| 332 | #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | 332 | #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ |
| 333 | #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | 333 | #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ |
| @@ -357,7 +357,7 @@ | |||
| 357 | #define ISR_ADDR 0xfffff30c | 357 | #define ISR_ADDR 0xfffff30c |
| 358 | #define ISR LONG_REF(ISR_ADDR) | 358 | #define ISR LONG_REF(ISR_ADDR) |
| 359 | 359 | ||
| 360 | #define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ | 360 | #define ISR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */ |
| 361 | #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ | 361 | #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ |
| 362 | #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | 362 | #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ |
| 363 | #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | 363 | #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ |
| @@ -391,7 +391,7 @@ | |||
| 391 | #define IPR_ADDR 0xfffff310 | 391 | #define IPR_ADDR 0xfffff310 |
| 392 | #define IPR LONG_REF(IPR_ADDR) | 392 | #define IPR LONG_REF(IPR_ADDR) |
| 393 | 393 | ||
| 394 | #define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ | 394 | #define IPR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */ |
| 395 | #define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ | 395 | #define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ |
| 396 | #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | 396 | #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ |
| 397 | #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | 397 | #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ |
| @@ -757,7 +757,7 @@ | |||
| 757 | 757 | ||
| 758 | /* 'EZ328-compatible definitions */ | 758 | /* 'EZ328-compatible definitions */ |
| 759 | #define TCN_ADDR TCN1_ADDR | 759 | #define TCN_ADDR TCN1_ADDR |
| 760 | #define TCN TCN | 760 | #define TCN TCN1 |
| 761 | 761 | ||
| 762 | /* | 762 | /* |
| 763 | * Timer Unit 1 and 2 Status Registers | 763 | * Timer Unit 1 and 2 Status Registers |