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authorGreg Ungerer <gerg@uclinux.org>2011-12-23 21:32:52 -0500
committerGreg Ungerer <gerg@uclinux.org>2012-03-04 18:43:09 -0500
commita4e2e2ac08f73dedeabecb9e1141a05889591b7b (patch)
tree649af490d48b9cc406e5c5709717add5ee6e2697 /arch/m68k
parentb7ce7f0d0efc1a95154fa6872d5d7c970d281c71 (diff)
m68knommu: make 520x QSPI platform addressing consistent
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 520x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/m520xsim.h12
-rw-r--r--arch/m68k/include/asm/mcfqspi.h2
-rw-r--r--arch/m68k/platform/520x/config.c12
3 files changed, 16 insertions, 10 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index b83cee2dfdac..17f2aab9cf97 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -61,6 +61,8 @@
61#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 61#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
62#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 62#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
63 63
64#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
65
64/* 66/*
65 * SDRAM configuration registers. 67 * SDRAM configuration registers.
66 */ 68 */
@@ -166,6 +168,16 @@
166#define MCFFEC_SIZE0 0x800 /* Register set size */ 168#define MCFFEC_SIZE0 0x800 /* Register set size */
167 169
168/* 170/*
171 * QSPI module.
172 */
173#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
174#define MCFQSPI_SIZE 0x40 /* Register set size */
175
176#define MCFQSPI_CS0 46
177#define MCFQSPI_CS1 47
178#define MCFQSPI_CS2 27
179
180/*
169 * Reset Control Unit. 181 * Reset Control Unit.
170 */ 182 */
171#define MCF_RCR 0xFC0A0000 183#define MCF_RCR 0xFC0A0000
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
index 7fe631972f1f..34a531ed2bd1 100644
--- a/arch/m68k/include/asm/mcfqspi.h
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -25,8 +25,6 @@
25#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) 25#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
26#elif defined(CONFIG_M5249) 26#elif defined(CONFIG_M5249)
27#define MCFQSPI_IOBASE (MCF_MBAR + 0x300) 27#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
28#elif defined(CONFIG_M520x)
29#define MCFQSPI_IOBASE 0xFC05C000
30#elif defined(CONFIG_M532x) 28#elif defined(CONFIG_M532x)
31#define MCFQSPI_IOBASE 0xFC058000 29#define MCFQSPI_IOBASE 0xFC058000
32#endif 30#endif
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
index 5746fa52ed56..c83fd1a3d47c 100644
--- a/arch/m68k/platform/520x/config.c
+++ b/arch/m68k/platform/520x/config.c
@@ -28,21 +28,17 @@
28#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) 28#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
29static struct resource m520x_qspi_resources[] = { 29static struct resource m520x_qspi_resources[] = {
30 { 30 {
31 .start = MCFQSPI_IOBASE, 31 .start = MCFQSPI_BASE,
32 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, 32 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
33 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
34 }, 34 },
35 { 35 {
36 .start = MCFINT_VECBASE + MCFINT_QSPI, 36 .start = MCF_IRQ_QSPI,
37 .end = MCFINT_VECBASE + MCFINT_QSPI, 37 .end = MCF_IRQ_QSPI,
38 .flags = IORESOURCE_IRQ, 38 .flags = IORESOURCE_IRQ,
39 }, 39 },
40}; 40};
41 41
42#define MCFQSPI_CS0 46
43#define MCFQSPI_CS1 47
44#define MCFQSPI_CS2 27
45
46static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control) 42static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
47{ 43{
48 int status; 44 int status;