diff options
author | Paul Bolle <pebolle@tiscali.nl> | 2012-06-07 04:57:07 -0400 |
---|---|---|
committer | Geert Uytterhoeven <geert@linux-m68k.org> | 2012-06-27 03:27:31 -0400 |
commit | dffc5837d80451e7fa3505ddc2e6c2fd4546641f (patch) | |
tree | 175fb11760f5ffac538b4116a5120da17b4171d0 /arch/m68k | |
parent | 7df0d27f3d78282e9ab97da060e85f53a5f556b5 (diff) |
m68k: Remove five unused headers
There are five entirely unused headers in arch/m68k/include/asm. Nothing
includes these headers. And a few tests found no hits for the things
they provide (which makes sense).
MC68332.h, mac_mouse.h, and mcfmbus.h are all unused since at least
v2.6.12-rc2 (I didn't bother looking further back than that).
apollodma.h is unused since v2.6.19: commit
2ed0ce5b57950a620155433c62a5a02a067f1376 ("m68k/Apollo: Remove obsolete
arch/m68k/apollo/dma.c") removed the last file interested in that
header.
And everything interested in <asm/sbus.h> was removed in the v2.6.28
release cycle. The last occurrence of "sbus.h" was deleted with commit
0c0db98b50ed1217c0dbf4051722034ba314d06e ("sparc: Remove
Documentation/sparc/sbus_drivers.txt"). I'm not sure whether anything
relevant for m68k was included in v2.6.27, but it doesn't really matter.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Acked-by: Greg Ungerer<gerg@uclinux.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r-- | arch/m68k/include/asm/MC68332.h | 152 | ||||
-rw-r--r-- | arch/m68k/include/asm/apollodma.h | 248 | ||||
-rw-r--r-- | arch/m68k/include/asm/mac_mouse.h | 23 | ||||
-rw-r--r-- | arch/m68k/include/asm/mcfmbus.h | 77 | ||||
-rw-r--r-- | arch/m68k/include/asm/sbus.h | 45 |
5 files changed, 0 insertions, 545 deletions
diff --git a/arch/m68k/include/asm/MC68332.h b/arch/m68k/include/asm/MC68332.h deleted file mode 100644 index 6bb8f02685a2..000000000000 --- a/arch/m68k/include/asm/MC68332.h +++ /dev/null | |||
@@ -1,152 +0,0 @@ | |||
1 | |||
2 | /* include/asm-m68knommu/MC68332.h: '332 control registers | ||
3 | * | ||
4 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, | ||
5 | * | ||
6 | */ | ||
7 | |||
8 | #ifndef _MC68332_H_ | ||
9 | #define _MC68332_H_ | ||
10 | |||
11 | #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) | ||
12 | #define WORD_REF(addr) (*((volatile unsigned short*)addr)) | ||
13 | |||
14 | #define PORTE_ADDR 0xfffa11 | ||
15 | #define PORTE BYTE_REF(PORTE_ADDR) | ||
16 | #define DDRE_ADDR 0xfffa15 | ||
17 | #define DDRE BYTE_REF(DDRE_ADDR) | ||
18 | #define PEPAR_ADDR 0xfffa17 | ||
19 | #define PEPAR BYTE_REF(PEPAR_ADDR) | ||
20 | |||
21 | #define PORTF_ADDR 0xfffa19 | ||
22 | #define PORTF BYTE_REF(PORTF_ADDR) | ||
23 | #define DDRF_ADDR 0xfffa1d | ||
24 | #define DDRF BYTE_REF(DDRF_ADDR) | ||
25 | #define PFPAR_ADDR 0xfffa1f | ||
26 | #define PFPAR BYTE_REF(PFPAR_ADDR) | ||
27 | |||
28 | #define PORTQS_ADDR 0xfffc15 | ||
29 | #define PORTQS BYTE_REF(PORTQS_ADDR) | ||
30 | #define DDRQS_ADDR 0xfffc17 | ||
31 | #define DDRQS BYTE_REF(DDRQS_ADDR) | ||
32 | #define PQSPAR_ADDR 0xfffc16 | ||
33 | #define PQSPAR BYTE_REF(PQSPAR_ADDR) | ||
34 | |||
35 | #define CSPAR0_ADDR 0xFFFA44 | ||
36 | #define CSPAR0 WORD_REF(CSPAR0_ADDR) | ||
37 | #define CSPAR1_ADDR 0xFFFA46 | ||
38 | #define CSPAR1 WORD_REF(CSPAR1_ADDR) | ||
39 | #define CSARBT_ADDR 0xFFFA48 | ||
40 | #define CSARBT WORD_REF(CSARBT_ADDR) | ||
41 | #define CSOPBT_ADDR 0xFFFA4A | ||
42 | #define CSOPBT WORD_REF(CSOPBT_ADDR) | ||
43 | #define CSBAR0_ADDR 0xFFFA4C | ||
44 | #define CSBAR0 WORD_REF(CSBAR0_ADDR) | ||
45 | #define CSOR0_ADDR 0xFFFA4E | ||
46 | #define CSOR0 WORD_REF(CSOR0_ADDR) | ||
47 | #define CSBAR1_ADDR 0xFFFA50 | ||
48 | #define CSBAR1 WORD_REF(CSBAR1_ADDR) | ||
49 | #define CSOR1_ADDR 0xFFFA52 | ||
50 | #define CSOR1 WORD_REF(CSOR1_ADDR) | ||
51 | #define CSBAR2_ADDR 0xFFFA54 | ||
52 | #define CSBAR2 WORD_REF(CSBAR2_ADDR) | ||
53 | #define CSOR2_ADDR 0xFFFA56 | ||
54 | #define CSOR2 WORD_REF(CSOR2_ADDR) | ||
55 | #define CSBAR3_ADDR 0xFFFA58 | ||
56 | #define CSBAR3 WORD_REF(CSBAR3_ADDR) | ||
57 | #define CSOR3_ADDR 0xFFFA5A | ||
58 | #define CSOR3 WORD_REF(CSOR3_ADDR) | ||
59 | #define CSBAR4_ADDR 0xFFFA5C | ||
60 | #define CSBAR4 WORD_REF(CSBAR4_ADDR) | ||
61 | #define CSOR4_ADDR 0xFFFA5E | ||
62 | #define CSOR4 WORD_REF(CSOR4_ADDR) | ||
63 | #define CSBAR5_ADDR 0xFFFA60 | ||
64 | #define CSBAR5 WORD_REF(CSBAR5_ADDR) | ||
65 | #define CSOR5_ADDR 0xFFFA62 | ||
66 | #define CSOR5 WORD_REF(CSOR5_ADDR) | ||
67 | #define CSBAR6_ADDR 0xFFFA64 | ||
68 | #define CSBAR6 WORD_REF(CSBAR6_ADDR) | ||
69 | #define CSOR6_ADDR 0xFFFA66 | ||
70 | #define CSOR6 WORD_REF(CSOR6_ADDR) | ||
71 | #define CSBAR7_ADDR 0xFFFA68 | ||
72 | #define CSBAR7 WORD_REF(CSBAR7_ADDR) | ||
73 | #define CSOR7_ADDR 0xFFFA6A | ||
74 | #define CSOR7 WORD_REF(CSOR7_ADDR) | ||
75 | #define CSBAR8_ADDR 0xFFFA6C | ||
76 | #define CSBAR8 WORD_REF(CSBAR8_ADDR) | ||
77 | #define CSOR8_ADDR 0xFFFA6E | ||
78 | #define CSOR8 WORD_REF(CSOR8_ADDR) | ||
79 | #define CSBAR9_ADDR 0xFFFA70 | ||
80 | #define CSBAR9 WORD_REF(CSBAR9_ADDR) | ||
81 | #define CSOR9_ADDR 0xFFFA72 | ||
82 | #define CSOR9 WORD_REF(CSOR9_ADDR) | ||
83 | #define CSBAR10_ADDR 0xFFFA74 | ||
84 | #define CSBAR10 WORD_REF(CSBAR10_ADDR) | ||
85 | #define CSOR10_ADDR 0xFFFA76 | ||
86 | #define CSOR10 WORD_REF(CSOR10_ADDR) | ||
87 | |||
88 | #define CSOR_MODE_ASYNC 0x0000 | ||
89 | #define CSOR_MODE_SYNC 0x8000 | ||
90 | #define CSOR_MODE_MASK 0x8000 | ||
91 | #define CSOR_BYTE_DISABLE 0x0000 | ||
92 | #define CSOR_BYTE_UPPER 0x4000 | ||
93 | #define CSOR_BYTE_LOWER 0x2000 | ||
94 | #define CSOR_BYTE_BOTH 0x6000 | ||
95 | #define CSOR_BYTE_MASK 0x6000 | ||
96 | #define CSOR_RW_RSVD 0x0000 | ||
97 | #define CSOR_RW_READ 0x0800 | ||
98 | #define CSOR_RW_WRITE 0x1000 | ||
99 | #define CSOR_RW_BOTH 0x1800 | ||
100 | #define CSOR_RW_MASK 0x1800 | ||
101 | #define CSOR_STROBE_DS 0x0400 | ||
102 | #define CSOR_STROBE_AS 0x0000 | ||
103 | #define CSOR_STROBE_MASK 0x0400 | ||
104 | #define CSOR_DSACK_WAIT(x) (wait << 6) | ||
105 | #define CSOR_DSACK_FTERM (14 << 6) | ||
106 | #define CSOR_DSACK_EXTERNAL (15 << 6) | ||
107 | #define CSOR_DSACK_MASK 0x03c0 | ||
108 | #define CSOR_SPACE_CPU 0x0000 | ||
109 | #define CSOR_SPACE_USER 0x0010 | ||
110 | #define CSOR_SPACE_SU 0x0020 | ||
111 | #define CSOR_SPACE_BOTH 0x0030 | ||
112 | #define CSOR_SPACE_MASK 0x0030 | ||
113 | #define CSOR_IPL_ALL 0x0000 | ||
114 | #define CSOR_IPL_PRIORITY(x) (x << 1) | ||
115 | #define CSOR_IPL_MASK 0x000e | ||
116 | #define CSOR_AVEC_ON 0x0001 | ||
117 | #define CSOR_AVEC_OFF 0x0000 | ||
118 | #define CSOR_AVEC_MASK 0x0001 | ||
119 | |||
120 | #define CSBAR_ADDR(x) ((addr >> 11) << 3) | ||
121 | #define CSBAR_ADDR_MASK 0xfff8 | ||
122 | #define CSBAR_BLKSIZE_2K 0x0000 | ||
123 | #define CSBAR_BLKSIZE_8K 0x0001 | ||
124 | #define CSBAR_BLKSIZE_16K 0x0002 | ||
125 | #define CSBAR_BLKSIZE_64K 0x0003 | ||
126 | #define CSBAR_BLKSIZE_128K 0x0004 | ||
127 | #define CSBAR_BLKSIZE_256K 0x0005 | ||
128 | #define CSBAR_BLKSIZE_512K 0x0006 | ||
129 | #define CSBAR_BLKSIZE_1M 0x0007 | ||
130 | #define CSBAR_BLKSIZE_MASK 0x0007 | ||
131 | |||
132 | #define CSPAR_DISC 0 | ||
133 | #define CSPAR_ALT 1 | ||
134 | #define CSPAR_CS8 2 | ||
135 | #define CSPAR_CS16 3 | ||
136 | #define CSPAR_MASK 3 | ||
137 | |||
138 | #define CSPAR0_CSBOOT(x) (x << 0) | ||
139 | #define CSPAR0_CS0(x) (x << 2) | ||
140 | #define CSPAR0_CS1(x) (x << 4) | ||
141 | #define CSPAR0_CS2(x) (x << 6) | ||
142 | #define CSPAR0_CS3(x) (x << 8) | ||
143 | #define CSPAR0_CS4(x) (x << 10) | ||
144 | #define CSPAR0_CS5(x) (x << 12) | ||
145 | |||
146 | #define CSPAR1_CS6(x) (x << 0) | ||
147 | #define CSPAR1_CS7(x) (x << 2) | ||
148 | #define CSPAR1_CS8(x) (x << 4) | ||
149 | #define CSPAR1_CS9(x) (x << 6) | ||
150 | #define CSPAR1_CS10(x) (x << 8) | ||
151 | |||
152 | #endif | ||
diff --git a/arch/m68k/include/asm/apollodma.h b/arch/m68k/include/asm/apollodma.h deleted file mode 100644 index 954adc851adb..000000000000 --- a/arch/m68k/include/asm/apollodma.h +++ /dev/null | |||
@@ -1,248 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm/dma.h: Defines for using and allocating dma channels. | ||
3 | * Written by Hennus Bergman, 1992. | ||
4 | * High DMA channel support & info by Hannu Savolainen | ||
5 | * and John Boyd, Nov. 1992. | ||
6 | */ | ||
7 | |||
8 | #ifndef _ASM_APOLLO_DMA_H | ||
9 | #define _ASM_APOLLO_DMA_H | ||
10 | |||
11 | #include <asm/apollohw.h> /* need byte IO */ | ||
12 | #include <linux/spinlock.h> /* And spinlocks */ | ||
13 | #include <linux/delay.h> | ||
14 | |||
15 | |||
16 | #define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val)) | ||
17 | #define dma_inb(addr) (*((volatile unsigned char *)(addr+IO_BASE))) | ||
18 | |||
19 | /* | ||
20 | * NOTES about DMA transfers: | ||
21 | * | ||
22 | * controller 1: channels 0-3, byte operations, ports 00-1F | ||
23 | * controller 2: channels 4-7, word operations, ports C0-DF | ||
24 | * | ||
25 | * - ALL registers are 8 bits only, regardless of transfer size | ||
26 | * - channel 4 is not used - cascades 1 into 2. | ||
27 | * - channels 0-3 are byte - addresses/counts are for physical bytes | ||
28 | * - channels 5-7 are word - addresses/counts are for physical words | ||
29 | * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries | ||
30 | * - transfer count loaded to registers is 1 less than actual count | ||
31 | * - controller 2 offsets are all even (2x offsets for controller 1) | ||
32 | * - page registers for 5-7 don't use data bit 0, represent 128K pages | ||
33 | * - page registers for 0-3 use bit 0, represent 64K pages | ||
34 | * | ||
35 | * DMA transfers are limited to the lower 16MB of _physical_ memory. | ||
36 | * Note that addresses loaded into registers must be _physical_ addresses, | ||
37 | * not logical addresses (which may differ if paging is active). | ||
38 | * | ||
39 | * Address mapping for channels 0-3: | ||
40 | * | ||
41 | * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) | ||
42 | * | ... | | ... | | ... | | ||
43 | * | ... | | ... | | ... | | ||
44 | * | ... | | ... | | ... | | ||
45 | * P7 ... P0 A7 ... A0 A7 ... A0 | ||
46 | * | Page | Addr MSB | Addr LSB | (DMA registers) | ||
47 | * | ||
48 | * Address mapping for channels 5-7: | ||
49 | * | ||
50 | * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) | ||
51 | * | ... | \ \ ... \ \ \ ... \ \ | ||
52 | * | ... | \ \ ... \ \ \ ... \ (not used) | ||
53 | * | ... | \ \ ... \ \ \ ... \ | ||
54 | * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 | ||
55 | * | Page | Addr MSB | Addr LSB | (DMA registers) | ||
56 | * | ||
57 | * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses | ||
58 | * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at | ||
59 | * the hardware level, so odd-byte transfers aren't possible). | ||
60 | * | ||
61 | * Transfer count (_not # bytes_) is limited to 64K, represented as actual | ||
62 | * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, | ||
63 | * and up to 128K bytes may be transferred on channels 5-7 in one operation. | ||
64 | * | ||
65 | */ | ||
66 | |||
67 | #define MAX_DMA_CHANNELS 8 | ||
68 | |||
69 | /* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000) | ||
70 | |||
71 | /* 8237 DMA controllers */ | ||
72 | #define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */ | ||
73 | #define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */ | ||
74 | |||
75 | /* DMA controller registers */ | ||
76 | #define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */ | ||
77 | #define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */ | ||
78 | #define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */ | ||
79 | #define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */ | ||
80 | #define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */ | ||
81 | #define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */ | ||
82 | #define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */ | ||
83 | #define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */ | ||
84 | #define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */ | ||
85 | #define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */ | ||
86 | |||
87 | #define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */ | ||
88 | #define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */ | ||
89 | #define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */ | ||
90 | #define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */ | ||
91 | #define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */ | ||
92 | #define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */ | ||
93 | #define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */ | ||
94 | #define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */ | ||
95 | #define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */ | ||
96 | #define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */ | ||
97 | |||
98 | #define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */ | ||
99 | #define DMA_ADDR_1 (IO_DMA1_BASE+0x02) | ||
100 | #define DMA_ADDR_2 (IO_DMA1_BASE+0x04) | ||
101 | #define DMA_ADDR_3 (IO_DMA1_BASE+0x06) | ||
102 | #define DMA_ADDR_4 (IO_DMA2_BASE+0x00) | ||
103 | #define DMA_ADDR_5 (IO_DMA2_BASE+0x04) | ||
104 | #define DMA_ADDR_6 (IO_DMA2_BASE+0x08) | ||
105 | #define DMA_ADDR_7 (IO_DMA2_BASE+0x0C) | ||
106 | |||
107 | #define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */ | ||
108 | #define DMA_CNT_1 (IO_DMA1_BASE+0x03) | ||
109 | #define DMA_CNT_2 (IO_DMA1_BASE+0x05) | ||
110 | #define DMA_CNT_3 (IO_DMA1_BASE+0x07) | ||
111 | #define DMA_CNT_4 (IO_DMA2_BASE+0x02) | ||
112 | #define DMA_CNT_5 (IO_DMA2_BASE+0x06) | ||
113 | #define DMA_CNT_6 (IO_DMA2_BASE+0x0A) | ||
114 | #define DMA_CNT_7 (IO_DMA2_BASE+0x0E) | ||
115 | |||
116 | #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ | ||
117 | #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ | ||
118 | #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ | ||
119 | |||
120 | #define DMA_AUTOINIT 0x10 | ||
121 | |||
122 | #define DMA_8BIT 0 | ||
123 | #define DMA_16BIT 1 | ||
124 | #define DMA_BUSMASTER 2 | ||
125 | |||
126 | extern spinlock_t dma_spin_lock; | ||
127 | |||
128 | static __inline__ unsigned long claim_dma_lock(void) | ||
129 | { | ||
130 | unsigned long flags; | ||
131 | spin_lock_irqsave(&dma_spin_lock, flags); | ||
132 | return flags; | ||
133 | } | ||
134 | |||
135 | static __inline__ void release_dma_lock(unsigned long flags) | ||
136 | { | ||
137 | spin_unlock_irqrestore(&dma_spin_lock, flags); | ||
138 | } | ||
139 | |||
140 | /* enable/disable a specific DMA channel */ | ||
141 | static __inline__ void enable_dma(unsigned int dmanr) | ||
142 | { | ||
143 | if (dmanr<=3) | ||
144 | dma_outb(dmanr, DMA1_MASK_REG); | ||
145 | else | ||
146 | dma_outb(dmanr & 3, DMA2_MASK_REG); | ||
147 | } | ||
148 | |||
149 | static __inline__ void disable_dma(unsigned int dmanr) | ||
150 | { | ||
151 | if (dmanr<=3) | ||
152 | dma_outb(dmanr | 4, DMA1_MASK_REG); | ||
153 | else | ||
154 | dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); | ||
155 | } | ||
156 | |||
157 | /* Clear the 'DMA Pointer Flip Flop'. | ||
158 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | ||
159 | * Use this once to initialize the FF to a known state. | ||
160 | * After that, keep track of it. :-) | ||
161 | * --- In order to do that, the DMA routines below should --- | ||
162 | * --- only be used while holding the DMA lock ! --- | ||
163 | */ | ||
164 | static __inline__ void clear_dma_ff(unsigned int dmanr) | ||
165 | { | ||
166 | if (dmanr<=3) | ||
167 | dma_outb(0, DMA1_CLEAR_FF_REG); | ||
168 | else | ||
169 | dma_outb(0, DMA2_CLEAR_FF_REG); | ||
170 | } | ||
171 | |||
172 | /* set mode (above) for a specific DMA channel */ | ||
173 | static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | ||
174 | { | ||
175 | if (dmanr<=3) | ||
176 | dma_outb(mode | dmanr, DMA1_MODE_REG); | ||
177 | else | ||
178 | dma_outb(mode | (dmanr&3), DMA2_MODE_REG); | ||
179 | } | ||
180 | |||
181 | /* Set transfer address & page bits for specific DMA channel. | ||
182 | * Assumes dma flipflop is clear. | ||
183 | */ | ||
184 | static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) | ||
185 | { | ||
186 | if (dmanr <= 3) { | ||
187 | dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); | ||
188 | dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); | ||
189 | } else { | ||
190 | dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); | ||
191 | dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); | ||
192 | } | ||
193 | } | ||
194 | |||
195 | |||
196 | /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for | ||
197 | * a specific DMA channel. | ||
198 | * You must ensure the parameters are valid. | ||
199 | * NOTE: from a manual: "the number of transfers is one more | ||
200 | * than the initial word count"! This is taken into account. | ||
201 | * Assumes dma flip-flop is clear. | ||
202 | * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. | ||
203 | */ | ||
204 | static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) | ||
205 | { | ||
206 | count--; | ||
207 | if (dmanr <= 3) { | ||
208 | dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); | ||
209 | dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); | ||
210 | } else { | ||
211 | dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); | ||
212 | dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); | ||
213 | } | ||
214 | } | ||
215 | |||
216 | |||
217 | /* Get DMA residue count. After a DMA transfer, this | ||
218 | * should return zero. Reading this while a DMA transfer is | ||
219 | * still in progress will return unpredictable results. | ||
220 | * If called before the channel has been used, it may return 1. | ||
221 | * Otherwise, it returns the number of _bytes_ left to transfer. | ||
222 | * | ||
223 | * Assumes DMA flip-flop is clear. | ||
224 | */ | ||
225 | static __inline__ int get_dma_residue(unsigned int dmanr) | ||
226 | { | ||
227 | unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE | ||
228 | : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; | ||
229 | |||
230 | /* using short to get 16-bit wrap around */ | ||
231 | unsigned short count; | ||
232 | |||
233 | count = 1 + dma_inb(io_port); | ||
234 | count += dma_inb(io_port) << 8; | ||
235 | |||
236 | return (dmanr<=3)? count : (count<<1); | ||
237 | } | ||
238 | |||
239 | |||
240 | /* These are in kernel/dma.c: */ | ||
241 | extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ | ||
242 | extern void free_dma(unsigned int dmanr); /* release it again */ | ||
243 | |||
244 | /* These are in arch/m68k/apollo/dma.c: */ | ||
245 | extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type); | ||
246 | extern void dma_unmap_page(unsigned short dma_addr); | ||
247 | |||
248 | #endif /* _ASM_APOLLO_DMA_H */ | ||
diff --git a/arch/m68k/include/asm/mac_mouse.h b/arch/m68k/include/asm/mac_mouse.h deleted file mode 100644 index 39a5c292eaee..000000000000 --- a/arch/m68k/include/asm/mac_mouse.h +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | #ifndef _ASM_MAC_MOUSE_H | ||
2 | #define _ASM_MAC_MOUSE_H | ||
3 | |||
4 | /* | ||
5 | * linux/include/asm-m68k/mac_mouse.h | ||
6 | * header file for Macintosh ADB mouse driver | ||
7 | * 27-10-97 Michael Schmitz | ||
8 | * copied from: | ||
9 | * header file for Atari Mouse driver | ||
10 | * by Robert de Vries (robert@and.nl) on 19Jul93 | ||
11 | */ | ||
12 | |||
13 | struct mouse_status { | ||
14 | char buttons; | ||
15 | short dx; | ||
16 | short dy; | ||
17 | int ready; | ||
18 | int active; | ||
19 | wait_queue_head_t wait; | ||
20 | struct fasync_struct *fasyncptr; | ||
21 | }; | ||
22 | |||
23 | #endif | ||
diff --git a/arch/m68k/include/asm/mcfmbus.h b/arch/m68k/include/asm/mcfmbus.h deleted file mode 100644 index 319899c47a2c..000000000000 --- a/arch/m68k/include/asm/mcfmbus.h +++ /dev/null | |||
@@ -1,77 +0,0 @@ | |||
1 | /****************************************************************************/ | ||
2 | |||
3 | /* | ||
4 | * mcfmbus.h -- Coldfire MBUS support defines. | ||
5 | * | ||
6 | * (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) | ||
7 | */ | ||
8 | |||
9 | /****************************************************************************/ | ||
10 | |||
11 | |||
12 | #ifndef mcfmbus_h | ||
13 | #define mcfmbus_h | ||
14 | |||
15 | |||
16 | #define MCFMBUS_BASE 0x280 | ||
17 | #define MCFMBUS_IRQ_VECTOR 0x19 | ||
18 | #define MCFMBUS_IRQ 0x1 | ||
19 | #define MCFMBUS_CLK 0x3f | ||
20 | #define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/ | ||
21 | #define MCFMBUS_ADDRESS 0x01 | ||
22 | |||
23 | |||
24 | /* | ||
25 | * Define the 5307 MBUS register set addresses | ||
26 | */ | ||
27 | |||
28 | #define MCFMBUS_MADR 0x00 | ||
29 | #define MCFMBUS_MFDR 0x04 | ||
30 | #define MCFMBUS_MBCR 0x08 | ||
31 | #define MCFMBUS_MBSR 0x0C | ||
32 | #define MCFMBUS_MBDR 0x10 | ||
33 | |||
34 | |||
35 | #define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/ | ||
36 | |||
37 | #define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/ | ||
38 | |||
39 | /* | ||
40 | * Define bit flags in Control Register | ||
41 | */ | ||
42 | |||
43 | #define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */ | ||
44 | #define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ | ||
45 | #define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */ | ||
46 | #define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */ | ||
47 | #define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ | ||
48 | #define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */ | ||
49 | |||
50 | /* | ||
51 | * Define bit flags in Status Register | ||
52 | */ | ||
53 | |||
54 | #define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */ | ||
55 | #define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */ | ||
56 | #define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */ | ||
57 | #define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */ | ||
58 | #define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */ | ||
59 | #define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */ | ||
60 | #define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */ | ||
61 | |||
62 | /* | ||
63 | * Define bit flags in DATA I/O Register | ||
64 | */ | ||
65 | |||
66 | #define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */ | ||
67 | |||
68 | #define MBUSIOCSCLOCK 1 | ||
69 | #define MBUSIOCGCLOCK 2 | ||
70 | #define MBUSIOCSADDR 3 | ||
71 | #define MBUSIOCGADDR 4 | ||
72 | #define MBUSIOCSSLADDR 5 | ||
73 | #define MBUSIOCGSLADDR 6 | ||
74 | #define MBUSIOCSSUBADDR 7 | ||
75 | #define MBUSIOCGSUBADDR 8 | ||
76 | |||
77 | #endif | ||
diff --git a/arch/m68k/include/asm/sbus.h b/arch/m68k/include/asm/sbus.h deleted file mode 100644 index bfe3ba147f2e..000000000000 --- a/arch/m68k/include/asm/sbus.h +++ /dev/null | |||
@@ -1,45 +0,0 @@ | |||
1 | /* | ||
2 | * some sbus structures and macros to make usage of sbus drivers possible | ||
3 | */ | ||
4 | |||
5 | #ifndef __M68K_SBUS_H | ||
6 | #define __M68K_SBUS_H | ||
7 | |||
8 | struct sbus_dev { | ||
9 | struct { | ||
10 | unsigned int which_io; | ||
11 | unsigned int phys_addr; | ||
12 | } reg_addrs[1]; | ||
13 | }; | ||
14 | |||
15 | /* sbus IO functions stolen from include/asm-sparc/io.h for the serial driver */ | ||
16 | /* No SBUS on the Sun3, kludge -- sam */ | ||
17 | |||
18 | static inline void _sbus_writeb(unsigned char val, unsigned long addr) | ||
19 | { | ||
20 | *(volatile unsigned char *)addr = val; | ||
21 | } | ||
22 | |||
23 | static inline unsigned char _sbus_readb(unsigned long addr) | ||
24 | { | ||
25 | return *(volatile unsigned char *)addr; | ||
26 | } | ||
27 | |||
28 | static inline void _sbus_writel(unsigned long val, unsigned long addr) | ||
29 | { | ||
30 | *(volatile unsigned long *)addr = val; | ||
31 | |||
32 | } | ||
33 | |||
34 | extern inline unsigned long _sbus_readl(unsigned long addr) | ||
35 | { | ||
36 | return *(volatile unsigned long *)addr; | ||
37 | } | ||
38 | |||
39 | |||
40 | #define sbus_readb(a) _sbus_readb((unsigned long)a) | ||
41 | #define sbus_writeb(v, a) _sbus_writeb(v, (unsigned long)a) | ||
42 | #define sbus_readl(a) _sbus_readl((unsigned long)a) | ||
43 | #define sbus_writel(v, a) _sbus_writel(v, (unsigned long)a) | ||
44 | |||
45 | #endif | ||