diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 00:31:08 -0500 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 00:19:20 -0500 |
| commit | 0ef6c9b8f7bf62ea05be5b26ee14b18a116b0c2a (patch) | |
| tree | 01ffb12226fef2f4de5f3408e21fe64e19b5a522 /arch/m68k | |
| parent | d475e3e4739ce465df740b51decbbea3b1b51823 (diff) | |
m68knommu: support version 2 ColdFire split cache
The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
| -rw-r--r-- | arch/m68k/include/asm/m52xxacr.h | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 52230b5e1e4d..701f680bced9 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h | |||
| @@ -53,23 +53,25 @@ | |||
| 53 | #define ACR_WPROTECT 0x00000004 /* Write protect region */ | 53 | #define ACR_WPROTECT 0x00000004 /* Write protect region */ |
| 54 | 54 | ||
| 55 | /* | 55 | /* |
| 56 | * Set the cache controller settings we will use. This code is set to | 56 | * Set the cache controller settings we will use. On the cores that support |
| 57 | * only use the instruction cache, even on the controllers that support | 57 | * a split cache configuration we allow all the combinations at Kconfig |
| 58 | * split cache. (This setup is trying to preserve the existing behavior | 58 | * time. For those cores that only have an instruction cache we just set |
| 59 | * for now, in the furture I hope to actually use the split cache mode). | 59 | * that as on. |
| 60 | */ | 60 | */ |
| 61 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ | 61 | #if defined(CONFIG_CACHE_I) |
| 62 | defined(CONFIG_M5249) || defined(CONFIG_M5272) | 62 | #define CACHE_TYPE CACR_DISD |
| 63 | #define CACHE_INIT (CACR_CINV) | 63 | #elif defined(CONFIG_CACHE_D) |
| 64 | #define CACHE_MODE (CACR_CENB + CACR_DCM) | 64 | #define CACHE_TYPE CACR_DISI |
| 65 | #else | 65 | #else |
| 66 | #ifdef CONFIG_COLDFIRE_SW_A7 | 66 | #define CACHE_TYPE |
| 67 | #define CACHE_INIT (CACR_CINV + CACR_DISD) | ||
| 68 | #define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM) | ||
| 69 | #else | ||
| 70 | #define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP) | ||
| 71 | #define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP) | ||
| 72 | #endif | 67 | #endif |
| 68 | |||
| 69 | #if defined(CONFIG_HAVE_CACHE_SPLIT) | ||
| 70 | #define CACHE_INIT (CACR_CINV + CACHE_TYPE + CACR_EUSP) | ||
| 71 | #define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP) | ||
| 72 | #else | ||
| 73 | #define CACHE_INIT (CACR_CINV) | ||
| 74 | #define CACHE_MODE (CACR_CENB + CACR_DCM) | ||
| 73 | #endif | 75 | #endif |
| 74 | 76 | ||
| 75 | #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) | 77 | #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) |