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authorSteven King <sfking@fdwdc.com>2012-06-05 11:23:08 -0400
committerGreg Ungerer <gerg@uclinux.org>2012-07-15 19:59:21 -0400
commit04e037aa4e5f71d11c004e844339d385a89733f6 (patch)
tree34f27c90251f7770e1bcbdcf3244b6b8b9dc7b85 /arch/m68k
parenteac57949947fa24f47a2e993a1dbbfdb573b4301 (diff)
m68knommu: Add support for the Coldfire 5251/5253
Basic support for the Coldfire 5251/5253. Signed-off-by: Steven king <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/Kconfig.cpu8
-rw-r--r--arch/m68k/Makefile1
-rw-r--r--arch/m68k/include/asm/dma.h4
-rw-r--r--arch/m68k/include/asm/m525xsim.h194
-rw-r--r--arch/m68k/include/asm/mcfgpio.h8
-rw-r--r--arch/m68k/include/asm/mcfsim.h3
-rw-r--r--arch/m68k/include/asm/mcfuart.h4
-rw-r--r--arch/m68k/platform/coldfire/Makefile1
-rw-r--r--arch/m68k/platform/coldfire/head.S6
-rw-r--r--arch/m68k/platform/coldfire/intc-525x.c91
-rw-r--r--arch/m68k/platform/coldfire/m525x.c66
11 files changed, 376 insertions, 10 deletions
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index ff2314d5d934..8d9afb09f569 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -167,6 +167,14 @@ config M5249
167 help 167 help
168 Motorola ColdFire 5249 processor support. 168 Motorola ColdFire 5249 processor support.
169 169
170config M525x
171 bool "MCF525x"
172 depends on !MMU
173 select COLDFIRE_SW_A7
174 select HAVE_MBAR
175 help
176 Freescale (Motorola) Coldfire 5251/5253 processor support.
177
170config M527x 178config M527x
171 bool 179 bool
172 180
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index b7f2e2d5cd2e..8daf9697e5e2 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -50,6 +50,7 @@ cpuflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
50cpuflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307) 50cpuflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307)
51cpuflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307) 51cpuflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307)
52cpuflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307) 52cpuflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307)
53cpuflags-$(CONFIG_M525x) := $(call cc-option,-mcpu=5253,-m5200)
53cpuflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200) 54cpuflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200)
54cpuflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200) 55cpuflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200)
55cpuflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200) 56cpuflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200)
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
index 6fbdfe895104..947064184639 100644
--- a/arch/m68k/include/asm/dma.h
+++ b/arch/m68k/include/asm/dma.h
@@ -33,7 +33,9 @@
33 * Set number of channels of DMA on ColdFire for different implementations. 33 * Set number of channels of DMA on ColdFire for different implementations.
34 */ 34 */
35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ 35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) 36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
37 defined(CONFIG_M528x) || defined(CONFIG_M525x)
38
37#define MAX_M68K_DMA_CHANNELS 4 39#define MAX_M68K_DMA_CHANNELS 4
38#elif defined(CONFIG_M5272) 40#elif defined(CONFIG_M5272)
39#define MAX_M68K_DMA_CHANNELS 1 41#define MAX_M68K_DMA_CHANNELS 1
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
new file mode 100644
index 000000000000..6da24f653902
--- /dev/null
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -0,0 +1,194 @@
1/****************************************************************************/
2
3/*
4 * m525xsim.h -- ColdFire 525x System Integration Module support.
5 *
6 * (C) Copyright 2012, Steven king <sfking@fdwdc.com>
7 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
8 */
9
10/****************************************************************************/
11#ifndef m525xsim_h
12#define m525xsim_h
13/****************************************************************************/
14
15#define CPU_NAME "COLDFIRE(m525x)"
16#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK (MCF_CLK / 2)
18
19#include <asm/m52xxacr.h>
20
21/*
22 * The 525x has a second MBAR region, define its address.
23 */
24#define MCF_MBAR2 0x80000000
25
26/*
27 * Define the 525x SIM register set addresses.
28 */
29#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
30#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
31#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
32#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
36#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
37#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
38#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
39#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
40#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
41#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
42#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
43#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
44#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
45#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
46#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
47#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
48
49#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
50#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
51#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
52#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
53#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
54#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
55#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
56#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
57#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
58#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
59#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
60#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
61#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
62#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
63#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
64
65#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
66#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
67#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
68
69/*
70 * Secondary Interrupt Controller (in MBAR2)
71*/
72#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
73#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
74#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
75#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
76#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
77#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
78#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
79#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
80#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
81
82#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
83 ((((i) - MCFINTC2_VECBASE) / 8) * 4))
84#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
85
86/*
87 * Timer module.
88 */
89#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
90#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
91
92/*
93 * UART module.
94 */
95#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
96#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
97
98/*
99 * QSPI module.
100 */
101#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
102#define MCFQSPI_SIZE 0x40 /* Register set size */
103
104
105#define MCFQSPI_CS0 15
106#define MCFQSPI_CS1 16
107#define MCFQSPI_CS2 24
108#define MCFQSPI_CS3 28
109
110/*
111 * I2C module.
112 */
113#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
114#define MCFI2C_SIZE0 0x20 /* Register set size */
115
116#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
117#define MCFI2C_SIZE1 0x20 /* Register set size */
118/*
119 * DMA unit base addresses.
120 */
121#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
122#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
123#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
124#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
125
126/*
127 * Some symbol defines for the above...
128 */
129#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
130#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
131#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
132#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
133#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
134#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
135#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
136#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
137#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
138#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
139#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
140
141/*
142 * Define system peripheral IRQ usage.
143 */
144#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
145#define MCF_IRQ_I2C0 29
146#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
147#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
148
149#define MCF_IRQ_UART0 73 /* UART0 */
150#define MCF_IRQ_UART1 74 /* UART1 */
151
152/*
153 * Define the base interrupt for the second interrupt controller.
154 * We set it to 128, out of the way of the base interrupts, and plenty
155 * of room for its 64 interrupts.
156 */
157#define MCFINTC2_VECBASE 128
158
159#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
160#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
161#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
162#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
163#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
164#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
165#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
166
167#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
168#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
169
170/*
171 * General purpose IO registers (in MBAR2).
172 */
173#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
174#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
175#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
176#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
177#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
178#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
179#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
180#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
181
182#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
183#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
184#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
185
186/*
187 * Generic GPIO support
188 */
189#define MCFGPIO_PIN_MAX 64
190#define MCFGPIO_IRQ_MAX 7
191#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
192
193/****************************************************************************/
194#endif /* m525xsim_h */
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index 67ba20ffedbe..b2471a5f02eb 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -122,7 +122,7 @@ static inline void gpio_free(unsigned gpio)
122#define mcfgpio_read(port) __raw_readw(port) 122#define mcfgpio_read(port) __raw_readw(port)
123#define mcfgpio_write(data, port) __raw_writew(data, port) 123#define mcfgpio_write(data, port) __raw_writew(data, port)
124 124
125#elif defined(CONFIG_M5249) 125#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
126 126
127/* These parts have GPIO organized by 32 bit ports */ 127/* These parts have GPIO organized by 32 bit ports */
128 128
@@ -183,7 +183,7 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
183 return MCFSIM_PBDAT; 183 return MCFSIM_PBDAT;
184 else 184 else
185 return MCFSIM_PCDAT; 185 return MCFSIM_PCDAT;
186#elif defined(CONFIG_M5249) 186#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
187 if (gpio < 32) 187 if (gpio < 32)
188 return MCFSIM2_GPIOREAD; 188 return MCFSIM2_GPIOREAD;
189 else 189 else
@@ -222,7 +222,7 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
222 return MCFSIM_PBDAT; 222 return MCFSIM_PBDAT;
223 else 223 else
224 return MCFSIM_PCDAT; 224 return MCFSIM_PCDAT;
225#elif defined(CONFIG_M5249) 225#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
226 if (gpio < 32) 226 if (gpio < 32)
227 return MCFSIM2_GPIOWRITE; 227 return MCFSIM2_GPIOWRITE;
228 else 228 else
@@ -261,7 +261,7 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
261 return MCFSIM_PBDDR; 261 return MCFSIM_PBDDR;
262 else 262 else
263 return MCFSIM_PCDDR; 263 return MCFSIM_PCDDR;
264#elif defined(CONFIG_M5249) 264#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
265 if (gpio < 32) 265 if (gpio < 32)
266 return MCFSIM2_GPIOENABLE; 266 return MCFSIM2_GPIOENABLE;
267 else 267 else
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index ebd0304054ad..6871f62b11b1 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -27,6 +27,9 @@
27#elif defined(CONFIG_M5249) 27#elif defined(CONFIG_M5249)
28#include <asm/m5249sim.h> 28#include <asm/m5249sim.h>
29#include <asm/mcfintc.h> 29#include <asm/mcfintc.h>
30#elif defined(CONFIG_M525x)
31#include <asm/m525xsim.h>
32#include <asm/mcfintc.h>
30#elif defined(CONFIG_M527x) 33#elif defined(CONFIG_M527x)
31#include <asm/m527xsim.h> 34#include <asm/m527xsim.h>
32#elif defined(CONFIG_M5272) 35#elif defined(CONFIG_M5272)
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2d3bc774b3c5..b40c20f66647 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -43,8 +43,8 @@ struct mcf_platform_uart {
43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
44#endif 44#endif
45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
46 defined(CONFIG_M5249) || defined(CONFIG_M5307) || \ 46 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
47 defined(CONFIG_M5407) 47 defined(CONFIG_M5307) || defined(CONFIG_M5407)
48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
49#endif 49#endif
50#define MCFUART_UIPR 0x34 /* Input Port (r) */ 50#define MCFUART_UIPR 0x34 /* Input Port (r) */
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index 69bc0ae2538d..a7329b4fbef8 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
20obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o 20obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
21obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o 21obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
22obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o 22obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
23obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
23obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o 24obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
24obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o 25obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
25obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o 26obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index c3db70ed33b3..4e0c9eb3bd1f 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -31,9 +31,9 @@
31.endm 31.endm
32 32
33#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 33#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
34 defined(CONFIG_M5249) || defined(CONFIG_M527x) || \ 34 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
35 defined(CONFIG_M528x) || defined(CONFIG_M5307) || \ 35 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
36 defined(CONFIG_M5407) 36 defined(CONFIG_M5307) || defined(CONFIG_M5407)
37/* 37/*
38 * Not all these devices have exactly the same DRAM controller, 38 * Not all these devices have exactly the same DRAM controller,
39 * but the DCMR register is virtually identical - give or take 39 * but the DCMR register is virtually identical - give or take
diff --git a/arch/m68k/platform/coldfire/intc-525x.c b/arch/m68k/platform/coldfire/intc-525x.c
new file mode 100644
index 000000000000..b23204d059ac
--- /dev/null
+++ b/arch/m68k/platform/coldfire/intc-525x.c
@@ -0,0 +1,91 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 525x
3 *
4 * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21static void intc2_irq_gpio_mask(struct irq_data *d)
22{
23 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
24 u32 type = irqd_get_trigger_type(d);
25 int irq = d->irq - MCF_IRQ_GPIO0;
26
27 if (type & IRQ_TYPE_EDGE_RISING)
28 imr &= ~(0x001 << irq);
29 if (type & IRQ_TYPE_EDGE_FALLING)
30 imr &= ~(0x100 << irq);
31 writel(imr, MCFSIM2_GPIOINTENABLE);
32}
33
34static void intc2_irq_gpio_unmask(struct irq_data *d)
35{
36 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
37 u32 type = irqd_get_trigger_type(d);
38 int irq = d->irq - MCF_IRQ_GPIO0;
39
40 if (type & IRQ_TYPE_EDGE_RISING)
41 imr |= (0x001 << irq);
42 if (type & IRQ_TYPE_EDGE_FALLING)
43 imr |= (0x100 << irq);
44 writel(imr, MCFSIM2_GPIOINTENABLE);
45}
46
47static void intc2_irq_gpio_ack(struct irq_data *d)
48{
49 u32 imr = 0;
50 u32 type = irqd_get_trigger_type(d);
51 int irq = d->irq - MCF_IRQ_GPIO0;
52
53 if (type & IRQ_TYPE_EDGE_RISING)
54 imr |= (0x001 << irq);
55 if (type & IRQ_TYPE_EDGE_FALLING)
56 imr |= (0x100 << irq);
57 writel(imr, MCFSIM2_GPIOINTCLEAR);
58}
59
60static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
61{
62 if (f & ~IRQ_TYPE_EDGE_BOTH)
63 return -EINVAL;
64 return 0;
65}
66
67static struct irq_chip intc2_irq_gpio_chip = {
68 .name = "CF-INTC2",
69 .irq_mask = intc2_irq_gpio_mask,
70 .irq_unmask = intc2_irq_gpio_unmask,
71 .irq_ack = intc2_irq_gpio_ack,
72 .irq_set_type = intc2_irq_gpio_set_type,
73};
74
75static int __init mcf_intc2_init(void)
76{
77 int irq;
78
79 /* set the interrupt base for the second interrupt controller */
80 writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
81
82 /* GPIO interrupt sources */
83 for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {
84 irq_set_chip(irq, &intc2_irq_gpio_chip);
85 irq_set_handler(irq, handle_edge_irq);
86 }
87
88 return 0;
89}
90
91arch_initcall(mcf_intc2_init);
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
new file mode 100644
index 000000000000..8ce905f9b84f
--- /dev/null
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -0,0 +1,66 @@
1/***************************************************************************/
2
3/*
4 * 525x.c
5 *
6 * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19
20/***************************************************************************/
21
22static void __init m525x_qspi_init(void)
23{
24#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
25 /* set the GPIO function for the qspi cs gpios */
26 /* FIXME: replace with pinmux/pinctl support */
27 u32 f = readl(MCFSIM2_GPIOFUNC);
28 f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
29 writel(f, MCFSIM2_GPIOFUNC);
30
31 /* QSPI irq setup */
32 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
33 MCF_MBAR + MCFSIM_QSPIICR);
34 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
35#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
36}
37
38static void __init m525x_i2c_init(void)
39{
40#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
41 u32 r;
42
43 /* first I2C controller uses regular irq setup */
44 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
45 MCF_MBAR + MCFSIM_I2CICR);
46 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
47
48 /* second I2C controller is completely different */
49 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
50 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
51 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
52 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
53#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
54}
55
56/***************************************************************************/
57
58void __init config_BSP(char *commandp, int size)
59{
60 mach_sched_init = hw_timer_init;
61
62 m525x_qspi_init();
63 m525x_i2c_init();
64}
65
66/***************************************************************************/
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 05:33:56 -0400