Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

1 files changed, 85 insertions, 0 deletions

diff --git a/arch/m68k/mm/hwtest.c b/arch/m68k/mm/hwtest.c
new file mode 100644
index 000000000000..2c7dde3c6430
--- /dev/null
+++ b/arch/m68k/mm/hwtest.c
@@ -0,0 +1,85 @@
+/* Tests for presence or absence of hardware registers.
+ * This code was originally in atari/config.c, but I noticed
+ * that it was also in drivers/nubus/nubus.c and I wanted to
+ * use it in hp300/config.c, so it seemed sensible to pull it
+ * out into its own file.
+ *
+ * The test is for use when trying to read a hardware register
+ * that isn't present would cause a bus error. We set up a
+ * temporary handler so that this doesn't kill the kernel.
+ *
+ * There is a test-by-reading and a test-by-writing; I present
+ * them here complete with the comments from the original atari
+ * config.c...
+ *                -- PMM <pmaydell@chiark.greenend.org.uk>, 05/1998
+ */
+
+/* This function tests for the presence of an address, specially a
+ * hardware register address. It is called very early in the kernel
+ * initialization process, when the VBR register isn't set up yet. On
+ * an Atari, it still points to address 0, which is unmapped. So a bus
+ * error would cause another bus error while fetching the exception
+ * vector, and the CPU would do nothing at all. So we needed to set up
+ * a temporary VBR and a vector table for the duration of the test.
+ */
+
+#include <linux/module.h>
+
+int hwreg_present( volatile void *regp )
+{
+    int ret = 0;
+    long        save_sp, save_vbr;
+    long        tmp_vectors[3];
+
+    __asm__ __volatile__
+        (       "movec  %/vbr,%2\n\t"
+                "movel  #Lberr1,%4@(8)\n\t"
+                "movec  %4,%/vbr\n\t"
+                "movel  %/sp,%1\n\t"
+                "moveq  #0,%0\n\t"
+                "tstb   %3@\n\t"
+                "nop\n\t"
+                "moveq  #1,%0\n"
+                "Lberr1:\n\t"
+                "movel  %1,%/sp\n\t"
+                "movec  %2,%/vbr"
+                : "=&d" (ret), "=&r" (save_sp), "=&r" (save_vbr)
+                : "a" (regp), "a" (tmp_vectors)
+                );
+
+    return( ret );
+}
+EXPORT_SYMBOL(hwreg_present);
+
+/* Basically the same, but writes a value into a word register, protected
+ * by a bus error handler. Returns 1 if successful, 0 otherwise.
+ */
+
+int hwreg_write( volatile void *regp, unsigned short val )
+{
+        int             ret;
+        long    save_sp, save_vbr;
+        long    tmp_vectors[3];
+
+        __asm__ __volatile__
+        (       "movec  %/vbr,%2\n\t"
+                "movel  #Lberr2,%4@(8)\n\t"
+                "movec  %4,%/vbr\n\t"
+                "movel  %/sp,%1\n\t"
+                "moveq  #0,%0\n\t"
+                "movew  %5,%3@\n\t"
+                "nop    \n\t"   /* If this nop isn't present, 'ret' may already be
+                                 * loaded with 1 at the time the bus error
+                                 * happens! */
+                "moveq  #1,%0\n"
+        "Lberr2:\n\t"
+                "movel  %1,%/sp\n\t"
+                "movec  %2,%/vbr"
+                : "=&d" (ret), "=&r" (save_sp), "=&r" (save_vbr)
+                : "a" (regp), "a" (tmp_vectors), "g" (val)
+        );
+
+        return( ret );
+}
+EXPORT_SYMBOL(hwreg_write);
+