aboutsummaryrefslogtreecommitdiffstats
path: root/arch/m68k/include
diff options
context:
space:
mode:
authorJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:15 -0400
committerJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:59 -0400
commit07f9479a40cc778bc1462ada11f95b01360ae4ff (patch)
tree0676cf38df3844004bb3ebfd99dfa67a4a8998f5 /arch/m68k/include
parent9d5e6bdb3013acfb311ab407eeca0b6a6a3dedbf (diff)
parentcd2e49e90f1cae7726c9a2c54488d881d7f1cd1c (diff)
Merge branch 'master' into for-next
Fast-forwarded to current state of Linus' tree as there are patches to be applied for files that didn't exist on the old branch.
Diffstat (limited to 'arch/m68k/include')
-rw-r--r--arch/m68k/include/asm/atariints.h2
-rw-r--r--arch/m68k/include/asm/bitops_mm.h102
-rw-r--r--arch/m68k/include/asm/bitops_no.h32
-rw-r--r--arch/m68k/include/asm/bootstd.h2
-rw-r--r--arch/m68k/include/asm/commproc.h4
-rw-r--r--arch/m68k/include/asm/delay_no.h2
-rw-r--r--arch/m68k/include/asm/gpio.h2
-rw-r--r--arch/m68k/include/asm/m520xsim.h2
-rw-r--r--arch/m68k/include/asm/m523xsim.h2
-rw-r--r--arch/m68k/include/asm/m527xsim.h2
-rw-r--r--arch/m68k/include/asm/m5307sim.h2
-rw-r--r--arch/m68k/include/asm/m5407sim.h2
-rw-r--r--arch/m68k/include/asm/m68360_quicc.h2
-rw-r--r--arch/m68k/include/asm/mac_oss.h2
-rw-r--r--arch/m68k/include/asm/mac_via.h2
-rw-r--r--arch/m68k/include/asm/macintosh.h2
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
-rw-r--r--arch/m68k/include/asm/types.h9
-rw-r--r--arch/m68k/include/asm/unistd.h6
19 files changed, 92 insertions, 89 deletions
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index f597892e43a0..656bbbf5a6ff 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -146,7 +146,7 @@ static inline void clear_mfp_bit( unsigned irq, int type )
146 146
147/* 147/*
148 * {en,dis}able_irq have the usual semantics of temporary blocking the 148 * {en,dis}able_irq have the usual semantics of temporary blocking the
149 * interrupt, but not loosing requests that happen between disabling and 149 * interrupt, but not losing requests that happen between disabling and
150 * enabling. This is done with the MFP mask registers. 150 * enabling. This is done with the MFP mask registers.
151 */ 151 */
152 152
diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h
index b4ecdaada520..9d69f6e62365 100644
--- a/arch/m68k/include/asm/bitops_mm.h
+++ b/arch/m68k/include/asm/bitops_mm.h
@@ -325,58 +325,45 @@ static inline int __fls(int x)
325#include <asm-generic/bitops/hweight.h> 325#include <asm-generic/bitops/hweight.h>
326#include <asm-generic/bitops/lock.h> 326#include <asm-generic/bitops/lock.h>
327 327
328/* Bitmap functions for the minix filesystem */ 328/* Bitmap functions for the little endian bitmap. */
329 329
330static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size) 330static inline void __set_bit_le(int nr, void *addr)
331{ 331{
332 const unsigned short *p = vaddr, *addr = vaddr; 332 __set_bit(nr ^ 24, addr);
333 int res; 333}
334 unsigned short num;
335
336 if (!size)
337 return 0;
338
339 size = (size >> 4) + ((size & 15) > 0);
340 while (*p++ == 0xffff)
341 {
342 if (--size == 0)
343 return (p - addr) << 4;
344 }
345 334
346 num = ~*--p; 335static inline void __clear_bit_le(int nr, void *addr)
347 __asm__ __volatile__ ("bfffo %1{#16,#16},%0" 336{
348 : "=d" (res) : "d" (num & -num)); 337 __clear_bit(nr ^ 24, addr);
349 return ((p - addr) << 4) + (res ^ 31);
350} 338}
351 339
352#define minix_test_and_set_bit(nr, addr) __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr)) 340static inline int __test_and_set_bit_le(int nr, void *addr)
353#define minix_set_bit(nr,addr) __set_bit((nr) ^ 16, (unsigned long *)(addr)) 341{
354#define minix_test_and_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr)) 342 return __test_and_set_bit(nr ^ 24, addr);
343}
355 344
356static inline int minix_test_bit(int nr, const void *vaddr) 345static inline int test_and_set_bit_le(int nr, void *addr)
357{ 346{
358 const unsigned short *p = vaddr; 347 return test_and_set_bit(nr ^ 24, addr);
359 return (p[nr >> 4] & (1U << (nr & 15))) != 0;
360} 348}
361 349
362/* Bitmap functions for the ext2 filesystem. */ 350static inline int __test_and_clear_bit_le(int nr, void *addr)
351{
352 return __test_and_clear_bit(nr ^ 24, addr);
353}
363 354
364#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) 355static inline int test_and_clear_bit_le(int nr, void *addr)
365#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) 356{
366#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) 357 return test_and_clear_bit(nr ^ 24, addr);
367#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) 358}
368#define ext2_find_next_zero_bit(addr, size, offset) \
369 generic_find_next_zero_le_bit((unsigned long *)addr, size, offset)
370#define ext2_find_next_bit(addr, size, offset) \
371 generic_find_next_le_bit((unsigned long *)addr, size, offset)
372 359
373static inline int ext2_test_bit(int nr, const void *vaddr) 360static inline int test_bit_le(int nr, const void *vaddr)
374{ 361{
375 const unsigned char *p = vaddr; 362 const unsigned char *p = vaddr;
376 return (p[nr >> 3] & (1U << (nr & 7))) != 0; 363 return (p[nr >> 3] & (1U << (nr & 7))) != 0;
377} 364}
378 365
379static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size) 366static inline int find_first_zero_bit_le(const void *vaddr, unsigned size)
380{ 367{
381 const unsigned long *p = vaddr, *addr = vaddr; 368 const unsigned long *p = vaddr, *addr = vaddr;
382 int res; 369 int res;
@@ -393,33 +380,36 @@ static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
393 380
394 --p; 381 --p;
395 for (res = 0; res < 32; res++) 382 for (res = 0; res < 32; res++)
396 if (!ext2_test_bit (res, p)) 383 if (!test_bit_le(res, p))
397 break; 384 break;
398 return (p - addr) * 32 + res; 385 return (p - addr) * 32 + res;
399} 386}
400 387
401static inline unsigned long generic_find_next_zero_le_bit(const unsigned long *addr, 388static inline unsigned long find_next_zero_bit_le(const void *addr,
402 unsigned long size, unsigned long offset) 389 unsigned long size, unsigned long offset)
403{ 390{
404 const unsigned long *p = addr + (offset >> 5); 391 const unsigned long *p = addr;
405 int bit = offset & 31UL, res; 392 int bit = offset & 31UL, res;
406 393
407 if (offset >= size) 394 if (offset >= size)
408 return size; 395 return size;
409 396
397 p += offset >> 5;
398
410 if (bit) { 399 if (bit) {
400 offset -= bit;
411 /* Look for zero in first longword */ 401 /* Look for zero in first longword */
412 for (res = bit; res < 32; res++) 402 for (res = bit; res < 32; res++)
413 if (!ext2_test_bit (res, p)) 403 if (!test_bit_le(res, p))
414 return (p - addr) * 32 + res; 404 return offset + res;
415 p++; 405 p++;
406 offset += 32;
416 } 407 }
417 /* No zero yet, search remaining full bytes for a zero */ 408 /* No zero yet, search remaining full bytes for a zero */
418 res = ext2_find_first_zero_bit (p, size - 32 * (p - addr)); 409 return offset + find_first_zero_bit_le(p, size - offset);
419 return (p - addr) * 32 + res;
420} 410}
421 411
422static inline int ext2_find_first_bit(const void *vaddr, unsigned size) 412static inline int find_first_bit_le(const void *vaddr, unsigned size)
423{ 413{
424 const unsigned long *p = vaddr, *addr = vaddr; 414 const unsigned long *p = vaddr, *addr = vaddr;
425 int res; 415 int res;
@@ -435,32 +425,42 @@ static inline int ext2_find_first_bit(const void *vaddr, unsigned size)
435 425
436 --p; 426 --p;
437 for (res = 0; res < 32; res++) 427 for (res = 0; res < 32; res++)
438 if (ext2_test_bit(res, p)) 428 if (test_bit_le(res, p))
439 break; 429 break;
440 return (p - addr) * 32 + res; 430 return (p - addr) * 32 + res;
441} 431}
442 432
443static inline unsigned long generic_find_next_le_bit(const unsigned long *addr, 433static inline unsigned long find_next_bit_le(const void *addr,
444 unsigned long size, unsigned long offset) 434 unsigned long size, unsigned long offset)
445{ 435{
446 const unsigned long *p = addr + (offset >> 5); 436 const unsigned long *p = addr;
447 int bit = offset & 31UL, res; 437 int bit = offset & 31UL, res;
448 438
449 if (offset >= size) 439 if (offset >= size)
450 return size; 440 return size;
451 441
442 p += offset >> 5;
443
452 if (bit) { 444 if (bit) {
445 offset -= bit;
453 /* Look for one in first longword */ 446 /* Look for one in first longword */
454 for (res = bit; res < 32; res++) 447 for (res = bit; res < 32; res++)
455 if (ext2_test_bit(res, p)) 448 if (test_bit_le(res, p))
456 return (p - addr) * 32 + res; 449 return offset + res;
457 p++; 450 p++;
451 offset += 32;
458 } 452 }
459 /* No set bit yet, search remaining full bytes for a set bit */ 453 /* No set bit yet, search remaining full bytes for a set bit */
460 res = ext2_find_first_bit(p, size - 32 * (p - addr)); 454 return offset + find_first_bit_le(p, size - offset);
461 return (p - addr) * 32 + res;
462} 455}
463 456
457/* Bitmap functions for the ext2 filesystem. */
458
459#define ext2_set_bit_atomic(lock, nr, addr) \
460 test_and_set_bit_le(nr, addr)
461#define ext2_clear_bit_atomic(lock, nr, addr) \
462 test_and_clear_bit_le(nr, addr)
463
464#endif /* __KERNEL__ */ 464#endif /* __KERNEL__ */
465 465
466#endif /* _M68K_BITOPS_H */ 466#endif /* _M68K_BITOPS_H */
diff --git a/arch/m68k/include/asm/bitops_no.h b/arch/m68k/include/asm/bitops_no.h
index 9d3cbe5fad1e..7d3779fdc5b6 100644
--- a/arch/m68k/include/asm/bitops_no.h
+++ b/arch/m68k/include/asm/bitops_no.h
@@ -196,7 +196,19 @@ static __inline__ int __test_bit(int nr, const volatile unsigned long * addr)
196#include <asm-generic/bitops/hweight.h> 196#include <asm-generic/bitops/hweight.h>
197#include <asm-generic/bitops/lock.h> 197#include <asm-generic/bitops/lock.h>
198 198
199static __inline__ int ext2_set_bit(int nr, volatile void * addr) 199#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
200
201static inline void __set_bit_le(int nr, void *addr)
202{
203 __set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
204}
205
206static inline void __clear_bit_le(int nr, void *addr)
207{
208 __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
209}
210
211static inline int __test_and_set_bit_le(int nr, volatile void *addr)
200{ 212{
201 char retval; 213 char retval;
202 214
@@ -215,7 +227,7 @@ static __inline__ int ext2_set_bit(int nr, volatile void * addr)
215 return retval; 227 return retval;
216} 228}
217 229
218static __inline__ int ext2_clear_bit(int nr, volatile void * addr) 230static inline int __test_and_clear_bit_le(int nr, volatile void *addr)
219{ 231{
220 char retval; 232 char retval;
221 233
@@ -238,7 +250,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
238 ({ \ 250 ({ \
239 int ret; \ 251 int ret; \
240 spin_lock(lock); \ 252 spin_lock(lock); \
241 ret = ext2_set_bit((nr), (addr)); \ 253 ret = __test_and_set_bit_le((nr), (addr)); \
242 spin_unlock(lock); \ 254 spin_unlock(lock); \
243 ret; \ 255 ret; \
244 }) 256 })
@@ -247,12 +259,12 @@ static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
247 ({ \ 259 ({ \
248 int ret; \ 260 int ret; \
249 spin_lock(lock); \ 261 spin_lock(lock); \
250 ret = ext2_clear_bit((nr), (addr)); \ 262 ret = __test_and_clear_bit_le((nr), (addr)); \
251 spin_unlock(lock); \ 263 spin_unlock(lock); \
252 ret; \ 264 ret; \
253 }) 265 })
254 266
255static __inline__ int ext2_test_bit(int nr, const volatile void * addr) 267static inline int test_bit_le(int nr, const volatile void *addr)
256{ 268{
257 char retval; 269 char retval;
258 270
@@ -271,10 +283,10 @@ static __inline__ int ext2_test_bit(int nr, const volatile void * addr)
271 return retval; 283 return retval;
272} 284}
273 285
274#define ext2_find_first_zero_bit(addr, size) \ 286#define find_first_zero_bit_le(addr, size) \
275 ext2_find_next_zero_bit((addr), (size), 0) 287 find_next_zero_bit_le((addr), (size), 0)
276 288
277static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) 289static inline unsigned long find_next_zero_bit_le(void *addr, unsigned long size, unsigned long offset)
278{ 290{
279 unsigned long *p = ((unsigned long *) addr) + (offset >> 5); 291 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
280 unsigned long result = offset & ~31UL; 292 unsigned long result = offset & ~31UL;
@@ -324,10 +336,6 @@ found_middle:
324 return result + ffz(__swab32(tmp)); 336 return result + ffz(__swab32(tmp));
325} 337}
326 338
327#define ext2_find_next_bit(addr, size, off) \
328 generic_find_next_le_bit((unsigned long *)(addr), (size), (off))
329#include <asm-generic/bitops/minix.h>
330
331#endif /* __KERNEL__ */ 339#endif /* __KERNEL__ */
332 340
333#include <asm-generic/bitops/fls.h> 341#include <asm-generic/bitops/fls.h>
diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h
index bdc1a4ac4fe9..e518f5a575b7 100644
--- a/arch/m68k/include/asm/bootstd.h
+++ b/arch/m68k/include/asm/bootstd.h
@@ -31,7 +31,7 @@
31#define __BN_flash_write_range 20 31#define __BN_flash_write_range 20
32 32
33/* Calling conventions compatible to (uC)linux/68k 33/* Calling conventions compatible to (uC)linux/68k
34 * We use simmilar macros to call into the bootloader as for uClinux 34 * We use similar macros to call into the bootloader as for uClinux
35 */ 35 */
36 36
37#define __bsc_return(type, res) \ 37#define __bsc_return(type, res) \
diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h
index edf5eb6c08d2..a73998528d26 100644
--- a/arch/m68k/include/asm/commproc.h
+++ b/arch/m68k/include/asm/commproc.h
@@ -88,7 +88,7 @@ typedef struct cpm_buf_desc {
88 88
89 89
90/* rx bd status/control bits */ 90/* rx bd status/control bits */
91#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 91#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ 92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ 94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
@@ -96,7 +96,7 @@ typedef struct cpm_buf_desc {
96#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ 96#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
97#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ 97#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
98 98
99#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 99#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
100#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ 100#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
101 101
102#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ 102#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
diff --git a/arch/m68k/include/asm/delay_no.h b/arch/m68k/include/asm/delay_no.h
index 55cbd6294ab6..c3a0edc90f21 100644
--- a/arch/m68k/include/asm/delay_no.h
+++ b/arch/m68k/include/asm/delay_no.h
@@ -16,7 +16,7 @@ static inline void __delay(unsigned long loops)
16 * long word alignment which is the faster version. 16 * long word alignment which is the faster version.
17 * The 0x4a8e is of course a 'tstl %fp' instruction. This is better 17 * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
18 * than using a NOP (0x4e71) instruction because it executes in one 18 * than using a NOP (0x4e71) instruction because it executes in one
19 * cycle not three and doesn't allow for an arbitary delay waiting 19 * cycle not three and doesn't allow for an arbitrary delay waiting
20 * for bus cycles to finish. Also fp/a6 isn't likely to cause a 20 * for bus cycles to finish. Also fp/a6 isn't likely to cause a
21 * stall waiting for the register to become valid if such is added 21 * stall waiting for the register to become valid if such is added
22 * to the coldfire at some stage. 22 * to the coldfire at some stage.
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index c64c7b74cf86..b2046839f4b2 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -31,7 +31,7 @@
31 * GPIOs in a single control area, others have some GPIOs implemented in 31 * GPIOs in a single control area, others have some GPIOs implemented in
32 * different modules. 32 * different modules.
33 * 33 *
34 * This implementation attempts accomodate the differences while presenting 34 * This implementation attempts accommodate the differences while presenting
35 * a generic interface that will optimize to as few instructions as possible. 35 * a generic interface that will optimize to as few instructions as possible.
36 */ 36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 55d5a4c5fe0b..b6bf2c518bac 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -157,7 +157,7 @@
157#define MCFFEC_SIZE 0x800 /* Register set size */ 157#define MCFFEC_SIZE 0x800 /* Register set size */
158 158
159/* 159/*
160 * Reset Controll Unit. 160 * Reset Control Unit.
161 */ 161 */
162#define MCF_RCR 0xFC0A0000 162#define MCF_RCR 0xFC0A0000
163#define MCF_RSR 0xFC0A0001 163#define MCF_RSR 0xFC0A0001
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 8996df62ede4..6235921eca4e 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -48,7 +48,7 @@
48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
49 49
50/* 50/*
51 * Reset Controll Unit (relative to IPSBAR). 51 * Reset Control Unit (relative to IPSBAR).
52 */ 52 */
53#define MCF_RCR 0x110000 53#define MCF_RCR 0x110000
54#define MCF_RSR 0x110001 54#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 74855a66c050..758810ef91ec 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -283,7 +283,7 @@
283#endif 283#endif
284 284
285/* 285/*
286 * Reset Controll Unit (relative to IPSBAR). 286 * Reset Control Unit (relative to IPSBAR).
287 */ 287 */
288#define MCF_RCR 0x110000 288#define MCF_RCR 0x110000
289#define MCF_RSR 0x110001 289#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 4c94c01f36c4..8f8609fcc9b8 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -29,7 +29,7 @@
29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
32#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ 32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 762c58c89050..51e00b00b8a6 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -29,7 +29,7 @@
29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
32#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ 32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h
index 6d40f4d18e10..59414cc108d3 100644
--- a/arch/m68k/include/asm/m68360_quicc.h
+++ b/arch/m68k/include/asm/m68360_quicc.h
@@ -32,7 +32,7 @@ struct user_data {
32 /* BASE + 0x000: user data memory */ 32 /* BASE + 0x000: user data memory */
33 volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ 33 volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
34 volatile unsigned char udata_bd[0x200]; /*user data Ucode */ 34 volatile unsigned char udata_bd[0x200]; /*user data Ucode */
35 volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */ 35 volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */
36 volatile unsigned char RESERVED1[0x500]; /* Reserved area */ 36 volatile unsigned char RESERVED1[0x500]; /* Reserved area */
37}; 37};
38#else 38#else
diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h
index 7221f7251934..3cf2b6ed685a 100644
--- a/arch/m68k/include/asm/mac_oss.h
+++ b/arch/m68k/include/asm/mac_oss.h
@@ -61,7 +61,7 @@
61/* 61/*
62 * OSS Interrupt levels for various sub-systems 62 * OSS Interrupt levels for various sub-systems
63 * 63 *
64 * This mapping is layed out with two things in mind: first, we try to keep 64 * This mapping is laid out with two things in mind: first, we try to keep
65 * things on their own levels to avoid having to do double-dispatches. Second, 65 * things on their own levels to avoid having to do double-dispatches. Second,
66 * the levels match as closely as possible the alternate IRQ mapping mode (aka 66 * the levels match as closely as possible the alternate IRQ mapping mode (aka
67 * "A/UX mode") available on some VIA machines. 67 * "A/UX mode") available on some VIA machines.
diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h
index 39afb438b656..a59665e1d41b 100644
--- a/arch/m68k/include/asm/mac_via.h
+++ b/arch/m68k/include/asm/mac_via.h
@@ -204,7 +204,7 @@
204#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 204#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
205#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 205#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
206#define vSR 0x1400 /* [VIA only] Shift register. */ 206#define vSR 0x1400 /* [VIA only] Shift register. */
207#define vACR 0x1600 /* [VIA only] Auxilary control register. */ 207#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
208#define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 208#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
209 /* CHRP sez never ever to *write* this. 209 /* CHRP sez never ever to *write* this.
210 * Mac family says never to *change* this. 210 * Mac family says never to *change* this.
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h
index 50db3591ca15..c2a1c5eac1a6 100644
--- a/arch/m68k/include/asm/macintosh.h
+++ b/arch/m68k/include/asm/macintosh.h
@@ -14,7 +14,7 @@ extern void mac_init_IRQ(void);
14extern int mac_irq_pending(unsigned int); 14extern int mac_irq_pending(unsigned int);
15 15
16/* 16/*
17 * Floppy driver magic hook - probably shouldnt be here 17 * Floppy driver magic hook - probably shouldn't be here
18 */ 18 */
19 19
20extern void via1_set_head(int); 20extern void via1_set_head(int);
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 92b276fe8240..351c27237874 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -27,7 +27,7 @@
27 27
28/* 28/*
29 * Bit definitions for the Timer Mode Register (TMR). 29 * Bit definitions for the Timer Mode Register (TMR).
30 * Register bit flags are common accross ColdFires. 30 * Register bit flags are common across ColdFires.
31 */ 31 */
32#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ 32#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
33#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ 33#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h
index 6441cb5f8e7c..b17fd115a4e7 100644
--- a/arch/m68k/include/asm/types.h
+++ b/arch/m68k/include/asm/types.h
@@ -23,15 +23,6 @@ typedef unsigned short umode_t;
23 23
24#define BITS_PER_LONG 32 24#define BITS_PER_LONG 32
25 25
26#ifndef __ASSEMBLY__
27
28/* DMA addresses are always 32-bits wide */
29
30typedef u32 dma_addr_t;
31typedef u32 dma64_addr_t;
32
33#endif /* __ASSEMBLY__ */
34
35#endif /* __KERNEL__ */ 26#endif /* __KERNEL__ */
36 27
37#endif /* _M68K_TYPES_H */ 28#endif /* _M68K_TYPES_H */
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 26d851d385bb..29e17907d9f2 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -343,10 +343,14 @@
343#define __NR_fanotify_init 337 343#define __NR_fanotify_init 337
344#define __NR_fanotify_mark 338 344#define __NR_fanotify_mark 338
345#define __NR_prlimit64 339 345#define __NR_prlimit64 339
346#define __NR_name_to_handle_at 340
347#define __NR_open_by_handle_at 341
348#define __NR_clock_adjtime 342
349#define __NR_syncfs 343
346 350
347#ifdef __KERNEL__ 351#ifdef __KERNEL__
348 352
349#define NR_syscalls 340 353#define NR_syscalls 344
350 354
351#define __ARCH_WANT_IPC_PARSE_VERSION 355#define __ARCH_WANT_IPC_PARSE_VERSION
352#define __ARCH_WANT_OLD_READDIR 356#define __ARCH_WANT_OLD_READDIR