m68k,m68knommu: merge header files

Merge header files for m68k and m68knommu to the single location:

    arch/m68k/include/asm

The majority of this patch was the result of the
script that is included in the changelog below.

The script was originally written by Arnd Bergman and
exten by me to cover a few more files.

When the header files differed the script uses the following:

The original m68k file is named <file>_mm.h  [mm for memory manager]
The m68knommu file is named <file>_no.h [no for no memory manager]

The files uses the following include guard:

This include gaurd works as the m68knommu toolchain set
the __uClinux__ symbol - so this should work in userspace too.

Merging the header files for m68k and m68knommu exposes the
(unexpected?) ABI differences thus it is easier to actually
identify these and thus to fix them.

The commit has been build tested with both a m68k and
a m68knommu toolchain - with success.

The commit has also been tested with "make headers_check"
and this patch fixes make headers_check for m68knommu.

The script used:
TARGET=arch/m68k/include/asm
SOURCE=arch/m68knommu/include/asm

INCLUDE="cachectl.h errno.h fcntl.h hwtest.h ioctls.h ipcbuf.h \
linkage.h math-emu.h md.h mman.h movs.h msgbuf.h openprom.h \
oplib.h poll.h posix_types.h resource.h rtc.h sembuf.h shmbuf.h \
shm.h shmparam.h socket.h sockios.h spinlock.h statfs.h stat.h \
termbits.h termios.h tlb.h types.h user.h"

EQUAL="auxvec.h cputime.h device.h emergency-restart.h futex.h \
ioctl.h irq_regs.h kdebug.h local.h mutex.h percpu.h \
sections.h topology.h"

NOMUUFILES="anchor.h bootstd.h coldfire.h commproc.h dbg.h \
elia.h flat.h m5206sim.h m520xsim.h m523xsim.h m5249sim.h \
m5272sim.h m527xsim.h m528xsim.h m5307sim.h m532xsim.h \
m5407sim.h m68360_enet.h m68360.h m68360_pram.h m68360_quicc.h \
m68360_regs.h MC68328.h MC68332.h MC68EZ328.h MC68VZ328.h \
mcfcache.h mcfdma.h mcfmbus.h mcfne.h mcfpci.h mcfpit.h \
mcfsim.h mcfsmc.h mcftimer.h mcfuart.h mcfwdebug.h \
nettel.h quicc_simple.h smp.h"

FILES="atomic.h bitops.h bootinfo.h bug.h bugs.h byteorder.h cache.h \
cacheflush.h checksum.h current.h delay.h div64.h \
dma-mapping.h dma.h elf.h entry.h fb.h fpu.h hardirq.h hw_irq.h io.h \
irq.h kmap_types.h machdep.h mc146818rtc.h mmu.h mmu_context.h \
module.h page.h page_offset.h param.h pci.h pgalloc.h \
pgtable.h processor.h ptrace.h scatterlist.h segment.h \
setup.h sigcontext.h siginfo.h signal.h string.h system.h swab.h \
thread_info.h timex.h tlbflush.h traps.h uaccess.h ucontext.h \
unaligned.h unistd.h"

mergefile() {
	BASE=${1%.h}
	git mv ${SOURCE}/$1 ${TARGET}/${BASE}_no.h
	git mv ${TARGET}/$1 ${TARGET}/${BASE}_mm.h

cat << EOF > ${TARGET}/$1
EOF

	git add ${TARGET}/$1
}

set -e

mkdir -p ${TARGET}

git mv include/asm-m68k/* ${TARGET}
rmdir include/asm-m68k

git rm ${SOURCE}/Kbuild
for F in $INCLUDE $EQUAL; do
	git rm ${SOURCE}/$F
done

for F in $NOMUUFILES; do
	git mv ${SOURCE}/$F ${TARGET}/$F
done

for F in $FILES ; do
	mergefile $F
done

rmdir arch/m68knommu/include/asm
rmdir arch/m68knommu/include

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 150 insertions, 0 deletions

diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
new file mode 100644
index 000000000000..c042634fadaa
--- /dev/null
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -0,0 +1,150 @@
+/****************************************************************************/
+
+/*
+ *      mcfcache.h -- ColdFire CPU cache support code
+ *
+ *      (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef __M68KNOMMU_MCFCACHE_H
+#define __M68KNOMMU_MCFCACHE_H
+/****************************************************************************/
+
+
+/*
+ *      The different ColdFire families have different cache arrangments.
+ *      Everything from a small instruction only cache, to configurable
+ *      data and/or instruction cache, to unified instruction/data, to 
+ *      harvard style separate instruction and data caches.
+ */
+
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
+/*
+ *      Simple version 2 core cache. These have instruction cache only,
+ *      we just need to invalidate it and enable it.
+ */
+.macro CACHE_ENABLE
+        movel   #0x01000000,%d0         /* invalidate cache cmd */
+        movec   %d0,%CACR               /* do invalidate cache */
+        movel   #0x80000100,%d0         /* setup cache mask */
+        movec   %d0,%CACR               /* enable cache */
+.endm
+#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
+
+#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
+/*
+ *      New version 2 cores have a configurable split cache arrangement.
+ *      For now I am just enabling instruction cache - but ultimately I
+ *      think a split instruction/data cache would be better.
+ */
+.macro CACHE_ENABLE
+        movel   #0x01400000,%d0
+        movec   %d0,%CACR               /* invalidate cache */
+        nop
+        movel   #0x0000c000,%d0         /* set SDRAM cached only */
+        movec   %d0,%ACR0
+        movel   #0x00000000,%d0         /* no other regions cached */
+        movec   %d0,%ACR1
+        movel   #0x80400100,%d0         /* configure cache */
+        movec   %d0,%CACR               /* enable cache */
+        nop
+.endm
+#endif /* CONFIG_M523x || CONFIG_M527x */
+
+#if defined(CONFIG_M528x)
+.macro CACHE_ENABLE
+        nop
+        movel   #0x01000000, %d0
+        movec   %d0, %CACR              /* Invalidate cache */
+        nop
+        movel   #0x0000c020, %d0        /* Set SDRAM cached only */
+        movec   %d0, %ACR0
+        movel   #0x00000000, %d0        /* No other regions cached */
+        movec   %d0, %ACR1
+        movel   #0x80000200, %d0        /* Setup cache mask */
+        movec   %d0, %CACR              /* Enable cache */
+        nop
+.endm
+#endif /* CONFIG_M528x */
+
+#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
+/*
+ *      The version 3 core cache. Oddly enough the version 2 core 5249
+ *      has the same SDRAM and cache setup as the version 3 cores.
+ *      This is a single unified instruction/data cache.
+ */
+.macro CACHE_ENABLE
+        movel   #0x01000000,%d0         /* invalidate whole cache */
+        movec   %d0,%CACR
+        nop
+#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
+        movel   #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
+#else
+        movel   #0x0000c020,%d0         /* set SDRAM cached (copyback) */
+#endif
+        movec   %d0,%ACR0
+        movel   #0x00000000,%d0         /* no other regions cached */
+        movec   %d0,%ACR1
+        movel   #0xa0000200,%d0         /* enable cache */
+        movec   %d0,%CACR
+        nop
+.endm
+#endif /* CONFIG_M5249 || CONFIG_M5307 */
+
+#if defined(CONFIG_M532x)
+.macro CACHE_ENABLE
+        movel   #0x01000000,%d0         /* invalidate cache cmd */
+        movec   %d0,%CACR               /* do invalidate cache */
+        nop
+        movel   #0x4001C000,%d0         /* set SDRAM cached (write-thru) */
+        movec   %d0,%ACR0
+        movel   #0x00000000,%d0         /* no other regions cached */
+        movec   %d0,%ACR1
+        movel   #0x80000200,%d0         /* setup cache mask */
+        movec   %d0,%CACR               /* enable cache */
+        nop
+.endm
+#endif /* CONFIG_M532x */
+
+#if defined(CONFIG_M5407)
+/*
+ *      Version 4 cores have a true harvard style separate instruction
+ *      and data cache. Invalidate and enable cache, also enable write
+ *      buffers and branch accelerator.
+ */
+.macro CACHE_ENABLE
+        movel   #0x01040100,%d0         /* invalidate whole cache */
+        movec   %d0,%CACR
+        nop
+        movel   #0x000fc000,%d0         /* set SDRAM cached only */
+        movec   %d0, %ACR0
+        movel   #0x00000000,%d0         /* no other regions cached */
+        movec   %d0, %ACR1
+        movel   #0x000fc000,%d0         /* set SDRAM cached only */
+        movec   %d0, %ACR2
+        movel   #0x00000000,%d0         /* no other regions cached */
+        movec   %d0, %ACR3
+        movel   #0xb6088400,%d0         /* enable caches */
+        movec   %d0,%CACR
+        nop
+.endm
+#endif /* CONFIG_M5407 */
+
+#if defined(CONFIG_M520x)
+.macro CACHE_ENABLE
+        move.l  #0x01000000,%d0         /* invalidate whole cache */
+        movec   %d0,%CACR
+        nop
+        move.l  #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
+        movec   %d0,%ACR0
+        move.l  #0x00000000,%d0         /* no other regions cached */
+        movec   %d0,%ACR1
+        move.l  #0x80400000,%d0         /* enable 8K instruction cache */
+        movec   %d0,%CACR
+        nop
+.endm
+#endif /* CONFIG_M520x */
+
+/****************************************************************************/
+#endif  /* __M68KNOMMU_MCFCACHE_H */