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authorIngo Molnar <mingo@elte.hu>2009-01-27 06:01:51 -0500
committerIngo Molnar <mingo@elte.hu>2009-01-27 06:01:51 -0500
commit3ddeb51d9c83931c1ca6abf76a38934c5a1ed918 (patch)
treefc2efb59d627135ea2199a8a68415b162646b121 /arch/m68k/include/asm/mcfcache.h
parent5a611268b69f05262936dd177205acbce4471358 (diff)
parent5ee810072175042775e39bdd3eaaa68884c27805 (diff)
Merge branch 'linus' into core/percpu
Conflicts: arch/x86/kernel/setup_percpu.c
Diffstat (limited to 'arch/m68k/include/asm/mcfcache.h')
-rw-r--r--arch/m68k/include/asm/mcfcache.h150
1 files changed, 150 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
new file mode 100644
index 000000000000..c042634fadaa
--- /dev/null
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -0,0 +1,150 @@
1/****************************************************************************/
2
3/*
4 * mcfcache.h -- ColdFire CPU cache support code
5 *
6 * (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
7 */
8
9/****************************************************************************/
10#ifndef __M68KNOMMU_MCFCACHE_H
11#define __M68KNOMMU_MCFCACHE_H
12/****************************************************************************/
13
14
15/*
16 * The different ColdFire families have different cache arrangments.
17 * Everything from a small instruction only cache, to configurable
18 * data and/or instruction cache, to unified instruction/data, to
19 * harvard style separate instruction and data caches.
20 */
21
22#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
23/*
24 * Simple version 2 core cache. These have instruction cache only,
25 * we just need to invalidate it and enable it.
26 */
27.macro CACHE_ENABLE
28 movel #0x01000000,%d0 /* invalidate cache cmd */
29 movec %d0,%CACR /* do invalidate cache */
30 movel #0x80000100,%d0 /* setup cache mask */
31 movec %d0,%CACR /* enable cache */
32.endm
33#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
34
35#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
36/*
37 * New version 2 cores have a configurable split cache arrangement.
38 * For now I am just enabling instruction cache - but ultimately I
39 * think a split instruction/data cache would be better.
40 */
41.macro CACHE_ENABLE
42 movel #0x01400000,%d0
43 movec %d0,%CACR /* invalidate cache */
44 nop
45 movel #0x0000c000,%d0 /* set SDRAM cached only */
46 movec %d0,%ACR0
47 movel #0x00000000,%d0 /* no other regions cached */
48 movec %d0,%ACR1
49 movel #0x80400100,%d0 /* configure cache */
50 movec %d0,%CACR /* enable cache */
51 nop
52.endm
53#endif /* CONFIG_M523x || CONFIG_M527x */
54
55#if defined(CONFIG_M528x)
56.macro CACHE_ENABLE
57 nop
58 movel #0x01000000, %d0
59 movec %d0, %CACR /* Invalidate cache */
60 nop
61 movel #0x0000c020, %d0 /* Set SDRAM cached only */
62 movec %d0, %ACR0
63 movel #0x00000000, %d0 /* No other regions cached */
64 movec %d0, %ACR1
65 movel #0x80000200, %d0 /* Setup cache mask */
66 movec %d0, %CACR /* Enable cache */
67 nop
68.endm
69#endif /* CONFIG_M528x */
70
71#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
72/*
73 * The version 3 core cache. Oddly enough the version 2 core 5249
74 * has the same SDRAM and cache setup as the version 3 cores.
75 * This is a single unified instruction/data cache.
76 */
77.macro CACHE_ENABLE
78 movel #0x01000000,%d0 /* invalidate whole cache */
79 movec %d0,%CACR
80 nop
81#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
82 movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
83#else
84 movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */
85#endif
86 movec %d0,%ACR0
87 movel #0x00000000,%d0 /* no other regions cached */
88 movec %d0,%ACR1
89 movel #0xa0000200,%d0 /* enable cache */
90 movec %d0,%CACR
91 nop
92.endm
93#endif /* CONFIG_M5249 || CONFIG_M5307 */
94
95#if defined(CONFIG_M532x)
96.macro CACHE_ENABLE
97 movel #0x01000000,%d0 /* invalidate cache cmd */
98 movec %d0,%CACR /* do invalidate cache */
99 nop
100 movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
101 movec %d0,%ACR0
102 movel #0x00000000,%d0 /* no other regions cached */
103 movec %d0,%ACR1
104 movel #0x80000200,%d0 /* setup cache mask */
105 movec %d0,%CACR /* enable cache */
106 nop
107.endm
108#endif /* CONFIG_M532x */
109
110#if defined(CONFIG_M5407)
111/*
112 * Version 4 cores have a true harvard style separate instruction
113 * and data cache. Invalidate and enable cache, also enable write
114 * buffers and branch accelerator.
115 */
116.macro CACHE_ENABLE
117 movel #0x01040100,%d0 /* invalidate whole cache */
118 movec %d0,%CACR
119 nop
120 movel #0x000fc000,%d0 /* set SDRAM cached only */
121 movec %d0, %ACR0
122 movel #0x00000000,%d0 /* no other regions cached */
123 movec %d0, %ACR1
124 movel #0x000fc000,%d0 /* set SDRAM cached only */
125 movec %d0, %ACR2
126 movel #0x00000000,%d0 /* no other regions cached */
127 movec %d0, %ACR3
128 movel #0xb6088400,%d0 /* enable caches */
129 movec %d0,%CACR
130 nop
131.endm
132#endif /* CONFIG_M5407 */
133
134#if defined(CONFIG_M520x)
135.macro CACHE_ENABLE
136 move.l #0x01000000,%d0 /* invalidate whole cache */
137 movec %d0,%CACR
138 nop
139 move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
140 movec %d0,%ACR0
141 move.l #0x00000000,%d0 /* no other regions cached */
142 movec %d0,%ACR1
143 move.l #0x80400000,%d0 /* enable 8K instruction cache */
144 movec %d0,%CACR
145 nop
146.endm
147#endif /* CONFIG_M520x */
148
149/****************************************************************************/
150#endif /* __M68KNOMMU_MCFCACHE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 12:44:13 -0500