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authorSam Ravnborg <sam@ravnborg.org>2009-01-16 06:58:10 -0500
committerGreg Ungerer <gerg@uclinux.org>2009-01-16 06:58:10 -0500
commit49148020bcb6910ce71417bd990a5ce7017f9bd3 (patch)
treee410cc433a69075a0254ee4000cb10d71df3a641 /arch/m68k/include/asm/m68360_pram.h
parentae04d1401577bb63151480a053057de58b8e10bb (diff)
m68k,m68knommu: merge header files
Merge header files for m68k and m68knommu to the single location: arch/m68k/include/asm The majority of this patch was the result of the script that is included in the changelog below. The script was originally written by Arnd Bergman and exten by me to cover a few more files. When the header files differed the script uses the following: The original m68k file is named <file>_mm.h [mm for memory manager] The m68knommu file is named <file>_no.h [no for no memory manager] The files uses the following include guard: This include gaurd works as the m68knommu toolchain set the __uClinux__ symbol - so this should work in userspace too. Merging the header files for m68k and m68knommu exposes the (unexpected?) ABI differences thus it is easier to actually identify these and thus to fix them. The commit has been build tested with both a m68k and a m68knommu toolchain - with success. The commit has also been tested with "make headers_check" and this patch fixes make headers_check for m68knommu. The script used: TARGET=arch/m68k/include/asm SOURCE=arch/m68knommu/include/asm INCLUDE="cachectl.h errno.h fcntl.h hwtest.h ioctls.h ipcbuf.h \ linkage.h math-emu.h md.h mman.h movs.h msgbuf.h openprom.h \ oplib.h poll.h posix_types.h resource.h rtc.h sembuf.h shmbuf.h \ shm.h shmparam.h socket.h sockios.h spinlock.h statfs.h stat.h \ termbits.h termios.h tlb.h types.h user.h" EQUAL="auxvec.h cputime.h device.h emergency-restart.h futex.h \ ioctl.h irq_regs.h kdebug.h local.h mutex.h percpu.h \ sections.h topology.h" NOMUUFILES="anchor.h bootstd.h coldfire.h commproc.h dbg.h \ elia.h flat.h m5206sim.h m520xsim.h m523xsim.h m5249sim.h \ m5272sim.h m527xsim.h m528xsim.h m5307sim.h m532xsim.h \ m5407sim.h m68360_enet.h m68360.h m68360_pram.h m68360_quicc.h \ m68360_regs.h MC68328.h MC68332.h MC68EZ328.h MC68VZ328.h \ mcfcache.h mcfdma.h mcfmbus.h mcfne.h mcfpci.h mcfpit.h \ mcfsim.h mcfsmc.h mcftimer.h mcfuart.h mcfwdebug.h \ nettel.h quicc_simple.h smp.h" FILES="atomic.h bitops.h bootinfo.h bug.h bugs.h byteorder.h cache.h \ cacheflush.h checksum.h current.h delay.h div64.h \ dma-mapping.h dma.h elf.h entry.h fb.h fpu.h hardirq.h hw_irq.h io.h \ irq.h kmap_types.h machdep.h mc146818rtc.h mmu.h mmu_context.h \ module.h page.h page_offset.h param.h pci.h pgalloc.h \ pgtable.h processor.h ptrace.h scatterlist.h segment.h \ setup.h sigcontext.h siginfo.h signal.h string.h system.h swab.h \ thread_info.h timex.h tlbflush.h traps.h uaccess.h ucontext.h \ unaligned.h unistd.h" mergefile() { BASE=${1%.h} git mv ${SOURCE}/$1 ${TARGET}/${BASE}_no.h git mv ${TARGET}/$1 ${TARGET}/${BASE}_mm.h cat << EOF > ${TARGET}/$1 EOF git add ${TARGET}/$1 } set -e mkdir -p ${TARGET} git mv include/asm-m68k/* ${TARGET} rmdir include/asm-m68k git rm ${SOURCE}/Kbuild for F in $INCLUDE $EQUAL; do git rm ${SOURCE}/$F done for F in $NOMUUFILES; do git mv ${SOURCE}/$F ${TARGET}/$F done for F in $FILES ; do mergefile $F done rmdir arch/m68knommu/include/asm rmdir arch/m68knommu/include Cc: Arnd Bergmann <arnd@arndb.de> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m68360_pram.h')
-rw-r--r--arch/m68k/include/asm/m68360_pram.h431
1 files changed, 431 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m68360_pram.h b/arch/m68k/include/asm/m68360_pram.h
new file mode 100644
index 000000000000..e6088bbce93d
--- /dev/null
+++ b/arch/m68k/include/asm/m68360_pram.h
@@ -0,0 +1,431 @@
1/***********************************
2 * $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions of the parameter area RAM.
7 * Note that different structures are overlaid
8 * at the same offsets for the different modes
9 * of operation.
10 ***************************************
11 */
12
13#ifndef __PRAM_H
14#define __PRAM_H
15
16/* Time slot assignment table */
17#define VALID_SLOT 0x8000
18#define WRAP_SLOT 0x4000
19
20/*****************************************************************
21 Global Multichannel parameter RAM
22*****************************************************************/
23struct global_multi_pram {
24 /*
25 * Global Multichannel parameter RAM
26 */
27 unsigned long mcbase; /* Multichannel Base pointer */
28 unsigned short qmcstate; /* Multichannel Controller state */
29 unsigned short mrblr; /* Maximum Receive Buffer Length */
30 unsigned short tx_s_ptr; /* TSTATx Pointer */
31 unsigned short rxptr; /* Current Time slot entry in TSATRx */
32 unsigned short grfthr; /* Global Receive frame threshold */
33 unsigned short grfcnt; /* Global Receive Frame Count */
34 unsigned long intbase; /* Multichannel Base address */
35 unsigned long iintptr; /* Pointer to interrupt queue */
36 unsigned short rx_s_ptr; /* TSTARx Pointer */
37
38 unsigned short txptr; /* Current Time slot entry in TSATTx */
39 unsigned long c_mask32; /* CRC Constant (debb20e3) */
40 unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */
41 unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */
42 unsigned short c_mask16; /* CRC Constant (f0b8) */
43};
44
45/*****************************************************************
46 Quicc32 HDLC parameter RAM
47*****************************************************************/
48struct quicc32_pram {
49
50 unsigned short tbase; /* Tx Buffer Descriptors Base Address */
51 unsigned short chamr; /* Channel Mode Register */
52 unsigned long tstate; /* Tx Internal State */
53 unsigned long txintr; /* Tx Internal Data Pointer */
54 unsigned short tbptr; /* Tx Buffer Descriptor Pointer */
55 unsigned short txcntr; /* Tx Internal Byte Count */
56 unsigned long tupack; /* (Tx Temp) */
57 unsigned long zistate; /* Zero Insertion machine state */
58 unsigned long tcrc; /* Temp Transmit CRC */
59 unsigned short intmask; /* Channel's interrupt mask flags */
60 unsigned short bdflags;
61 unsigned short rbase; /* Rx Buffer Descriptors Base Address */
62 unsigned short mflr; /* Max Frame Length Register */
63 unsigned long rstate; /* Rx Internal State */
64 unsigned long rxintr; /* Rx Internal Data Pointer */
65 unsigned short rbptr; /* Rx Buffer Descriptor Pointer */
66 unsigned short rxbyc; /* Rx Internal Byte Count */
67 unsigned long rpack; /* (Rx Temp) */
68 unsigned long zdstate; /* Zero Deletion machine state */
69 unsigned long rcrc; /* Temp Transmit CRC */
70 unsigned short maxc; /* Max_length counter */
71 unsigned short tmp_mb; /* Temp */
72};
73
74
75/*****************************************************************
76 HDLC parameter RAM
77*****************************************************************/
78
79struct hdlc_pram {
80 /*
81 * SCC parameter RAM
82 */
83 unsigned short rbase; /* RX BD base address */
84 unsigned short tbase; /* TX BD base address */
85 unsigned char rfcr; /* Rx function code */
86 unsigned char tfcr; /* Tx function code */
87 unsigned short mrblr; /* Rx buffer length */
88 unsigned long rstate; /* Rx internal state */
89 unsigned long rptr; /* Rx internal data pointer */
90 unsigned short rbptr; /* rb BD Pointer */
91 unsigned short rcount; /* Rx internal byte count */
92 unsigned long rtemp; /* Rx temp */
93 unsigned long tstate; /* Tx internal state */
94 unsigned long tptr; /* Tx internal data pointer */
95 unsigned short tbptr; /* Tx BD pointer */
96 unsigned short tcount; /* Tx byte count */
97 unsigned long ttemp; /* Tx temp */
98 unsigned long rcrc; /* temp receive CRC */
99 unsigned long tcrc; /* temp transmit CRC */
100
101 /*
102 * HDLC specific parameter RAM
103 */
104 unsigned char RESERVED1[4]; /* Reserved area */
105 unsigned long c_mask; /* CRC constant */
106 unsigned long c_pres; /* CRC preset */
107 unsigned short disfc; /* discarded frame counter */
108 unsigned short crcec; /* CRC error counter */
109 unsigned short abtsc; /* abort sequence counter */
110 unsigned short nmarc; /* nonmatching address rx cnt */
111 unsigned short retrc; /* frame retransmission cnt */
112 unsigned short mflr; /* maximum frame length reg */
113 unsigned short max_cnt; /* maximum length counter */
114 unsigned short rfthr; /* received frames threshold */
115 unsigned short rfcnt; /* received frames count */
116 unsigned short hmask; /* user defined frm addr mask */
117 unsigned short haddr1; /* user defined frm address 1 */
118 unsigned short haddr2; /* user defined frm address 2 */
119 unsigned short haddr3; /* user defined frm address 3 */
120 unsigned short haddr4; /* user defined frm address 4 */
121 unsigned short tmp; /* temp */
122 unsigned short tmp_mb; /* temp */
123};
124
125
126
127/*****************************************************************
128 UART parameter RAM
129*****************************************************************/
130
131/*
132 * bits in uart control characters table
133 */
134#define CC_INVALID 0x8000 /* control character is valid */
135#define CC_REJ 0x4000 /* don't store char in buffer */
136#define CC_CHAR 0x00ff /* control character */
137
138/* UART */
139struct uart_pram {
140 /*
141 * SCC parameter RAM
142 */
143 unsigned short rbase; /* RX BD base address */
144 unsigned short tbase; /* TX BD base address */
145 unsigned char rfcr; /* Rx function code */
146 unsigned char tfcr; /* Tx function code */
147 unsigned short mrblr; /* Rx buffer length */
148 unsigned long rstate; /* Rx internal state */
149 unsigned long rptr; /* Rx internal data pointer */
150 unsigned short rbptr; /* rb BD Pointer */
151 unsigned short rcount; /* Rx internal byte count */
152 unsigned long rx_temp; /* Rx temp */
153 unsigned long tstate; /* Tx internal state */
154 unsigned long tptr; /* Tx internal data pointer */
155 unsigned short tbptr; /* Tx BD pointer */
156 unsigned short tcount; /* Tx byte count */
157 unsigned long ttemp; /* Tx temp */
158 unsigned long rcrc; /* temp receive CRC */
159 unsigned long tcrc; /* temp transmit CRC */
160
161 /*
162 * UART specific parameter RAM
163 */
164 unsigned char RESERVED1[8]; /* Reserved area */
165 unsigned short max_idl; /* maximum idle characters */
166 unsigned short idlc; /* rx idle counter (internal) */
167 unsigned short brkcr; /* break count register */
168
169 unsigned short parec; /* Rx parity error counter */
170 unsigned short frmer; /* Rx framing error counter */
171 unsigned short nosec; /* Rx noise counter */
172 unsigned short brkec; /* Rx break character counter */
173 unsigned short brkln; /* Reaceive break length */
174
175 unsigned short uaddr1; /* address character 1 */
176 unsigned short uaddr2; /* address character 2 */
177 unsigned short rtemp; /* temp storage */
178 unsigned short toseq; /* Tx out of sequence char */
179 unsigned short cc[8]; /* Rx control characters */
180 unsigned short rccm; /* Rx control char mask */
181 unsigned short rccr; /* Rx control char register */
182 unsigned short rlbc; /* Receive last break char */
183};
184
185
186
187/*****************************************************************
188 BISYNC parameter RAM
189*****************************************************************/
190
191struct bisync_pram {
192 /*
193 * SCC parameter RAM
194 */
195 unsigned short rbase; /* RX BD base address */
196 unsigned short tbase; /* TX BD base address */
197 unsigned char rfcr; /* Rx function code */
198 unsigned char tfcr; /* Tx function code */
199 unsigned short mrblr; /* Rx buffer length */
200 unsigned long rstate; /* Rx internal state */
201 unsigned long rptr; /* Rx internal data pointer */
202 unsigned short rbptr; /* rb BD Pointer */
203 unsigned short rcount; /* Rx internal byte count */
204 unsigned long rtemp; /* Rx temp */
205 unsigned long tstate; /* Tx internal state */
206 unsigned long tptr; /* Tx internal data pointer */
207 unsigned short tbptr; /* Tx BD pointer */
208 unsigned short tcount; /* Tx byte count */
209 unsigned long ttemp; /* Tx temp */
210 unsigned long rcrc; /* temp receive CRC */
211 unsigned long tcrc; /* temp transmit CRC */
212
213 /*
214 * BISYNC specific parameter RAM
215 */
216 unsigned char RESERVED1[4]; /* Reserved area */
217 unsigned long crcc; /* CRC Constant Temp Value */
218 unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
219 unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
220 unsigned short parec; /* Receive Parity Error Counter */
221 unsigned short bsync; /* BISYNC SYNC Character */
222 unsigned short bdle; /* BISYNC DLE Character */
223 unsigned short cc[8]; /* Rx control characters */
224 unsigned short rccm; /* Receive Control Character Mask */
225};
226
227/*****************************************************************
228 IOM2 parameter RAM
229 (overlaid on tx bd[5] of SCC channel[2])
230*****************************************************************/
231struct iom2_pram {
232 unsigned short ci_data; /* ci data */
233 unsigned short monitor_data; /* monitor data */
234 unsigned short tstate; /* transmitter state */
235 unsigned short rstate; /* receiver state */
236};
237
238/*****************************************************************
239 SPI/SMC parameter RAM
240 (overlaid on tx bd[6,7] of SCC channel[2])
241*****************************************************************/
242
243#define SPI_R 0x8000 /* Ready bit in BD */
244
245struct spi_pram {
246 unsigned short rbase; /* Rx BD Base Address */
247 unsigned short tbase; /* Tx BD Base Address */
248 unsigned char rfcr; /* Rx function code */
249 unsigned char tfcr; /* Tx function code */
250 unsigned short mrblr; /* Rx buffer length */
251 unsigned long rstate; /* Rx internal state */
252 unsigned long rptr; /* Rx internal data pointer */
253 unsigned short rbptr; /* rb BD Pointer */
254 unsigned short rcount; /* Rx internal byte count */
255 unsigned long rtemp; /* Rx temp */
256 unsigned long tstate; /* Tx internal state */
257 unsigned long tptr; /* Tx internal data pointer */
258 unsigned short tbptr; /* Tx BD pointer */
259 unsigned short tcount; /* Tx byte count */
260 unsigned long ttemp; /* Tx temp */
261};
262
263struct smc_uart_pram {
264 unsigned short rbase; /* Rx BD Base Address */
265 unsigned short tbase; /* Tx BD Base Address */
266 unsigned char rfcr; /* Rx function code */
267 unsigned char tfcr; /* Tx function code */
268 unsigned short mrblr; /* Rx buffer length */
269 unsigned long rstate; /* Rx internal state */
270 unsigned long rptr; /* Rx internal data pointer */
271 unsigned short rbptr; /* rb BD Pointer */
272 unsigned short rcount; /* Rx internal byte count */
273 unsigned long rtemp; /* Rx temp */
274 unsigned long tstate; /* Tx internal state */
275 unsigned long tptr; /* Tx internal data pointer */
276 unsigned short tbptr; /* Tx BD pointer */
277 unsigned short tcount; /* Tx byte count */
278 unsigned long ttemp; /* Tx temp */
279 unsigned short max_idl; /* Maximum IDLE Characters */
280 unsigned short idlc; /* Temporary IDLE Counter */
281 unsigned short brkln; /* Last Rx Break Length */
282 unsigned short brkec; /* Rx Break Condition Counter */
283 unsigned short brkcr; /* Break Count Register (Tx) */
284 unsigned short r_mask; /* Temporary bit mask */
285};
286
287struct smc_trnsp_pram {
288 unsigned short rbase; /* rx BD Base Address */
289 unsigned short tbase; /* Tx BD Base Address */
290 unsigned char rfcr; /* Rx function code */
291 unsigned char tfcr; /* Tx function code */
292 unsigned short mrblr; /* Rx buffer length */
293 unsigned long rstate; /* Rx internal state */
294 unsigned long rptr; /* Rx internal data pointer */
295 unsigned short rbptr; /* rb BD Pointer */
296 unsigned short rcount; /* Rx internal byte count */
297 unsigned long rtemp; /* Rx temp */
298 unsigned long tstate; /* Tx internal state */
299 unsigned long tptr; /* Tx internal data pointer */
300 unsigned short tbptr; /* Tx BD pointer */
301 unsigned short tcount; /* Tx byte count */
302 unsigned long ttemp; /* Tx temp */
303 unsigned short reserved[5]; /* Reserved */
304};
305
306struct idma_pram {
307 unsigned short ibase; /* IDMA BD Base Address */
308 unsigned short ibptr; /* IDMA buffer descriptor pointer */
309 unsigned long istate; /* IDMA internal state */
310 unsigned long itemp; /* IDMA temp */
311};
312
313struct ethernet_pram {
314 /*
315 * SCC parameter RAM
316 */
317 unsigned short rbase; /* RX BD base address */
318 unsigned short tbase; /* TX BD base address */
319 unsigned char rfcr; /* Rx function code */
320 unsigned char tfcr; /* Tx function code */
321 unsigned short mrblr; /* Rx buffer length */
322 unsigned long rstate; /* Rx internal state */
323 unsigned long rptr; /* Rx internal data pointer */
324 unsigned short rbptr; /* rb BD Pointer */
325 unsigned short rcount; /* Rx internal byte count */
326 unsigned long rtemp; /* Rx temp */
327 unsigned long tstate; /* Tx internal state */
328 unsigned long tptr; /* Tx internal data pointer */
329 unsigned short tbptr; /* Tx BD pointer */
330 unsigned short tcount; /* Tx byte count */
331 unsigned long ttemp; /* Tx temp */
332 unsigned long rcrc; /* temp receive CRC */
333 unsigned long tcrc; /* temp transmit CRC */
334
335 /*
336 * ETHERNET specific parameter RAM
337 */
338 unsigned long c_pres; /* preset CRC */
339 unsigned long c_mask; /* constant mask for CRC */
340 unsigned long crcec; /* CRC error counter */
341 unsigned long alec; /* alighnment error counter */
342 unsigned long disfc; /* discard frame counter */
343 unsigned short pads; /* short frame PAD characters */
344 unsigned short ret_lim; /* retry limit threshold */
345 unsigned short ret_cnt; /* retry limit counter */
346 unsigned short mflr; /* maximum frame length reg */
347 unsigned short minflr; /* minimum frame length reg */
348 unsigned short maxd1; /* maximum DMA1 length reg */
349 unsigned short maxd2; /* maximum DMA2 length reg */
350 unsigned short maxd; /* rx max DMA */
351 unsigned short dma_cnt; /* rx dma counter */
352 unsigned short max_b; /* max bd byte count */
353 unsigned short gaddr1; /* group address filter 1 */
354 unsigned short gaddr2; /* group address filter 2 */
355 unsigned short gaddr3; /* group address filter 3 */
356 unsigned short gaddr4; /* group address filter 4 */
357 unsigned long tbuf0_data0; /* save area 0 - current frm */
358 unsigned long tbuf0_data1; /* save area 1 - current frm */
359 unsigned long tbuf0_rba0;
360 unsigned long tbuf0_crc;
361 unsigned short tbuf0_bcnt;
362 union {
363 unsigned char b[6];
364 struct {
365 unsigned short high;
366 unsigned short middl;
367 unsigned short low;
368 } w;
369 } paddr;
370 unsigned short p_per; /* persistence */
371 unsigned short rfbd_ptr; /* rx first bd pointer */
372 unsigned short tfbd_ptr; /* tx first bd pointer */
373 unsigned short tlbd_ptr; /* tx last bd pointer */
374 unsigned long tbuf1_data0; /* save area 0 - next frame */
375 unsigned long tbuf1_data1; /* save area 1 - next frame */
376 unsigned long tbuf1_rba0;
377 unsigned long tbuf1_crc;
378 unsigned short tbuf1_bcnt;
379 unsigned short tx_len; /* tx frame length counter */
380 unsigned short iaddr1; /* individual address filter 1*/
381 unsigned short iaddr2; /* individual address filter 2*/
382 unsigned short iaddr3; /* individual address filter 3*/
383 unsigned short iaddr4; /* individual address filter 4*/
384 unsigned short boff_cnt; /* back-off counter */
385 unsigned short taddr_h; /* temp address (MSB) */
386 unsigned short taddr_m; /* temp address */
387 unsigned short taddr_l; /* temp address (LSB) */
388};
389
390struct transparent_pram {
391 /*
392 * SCC parameter RAM
393 */
394 unsigned short rbase; /* RX BD base address */
395 unsigned short tbase; /* TX BD base address */
396 unsigned char rfcr; /* Rx function code */
397 unsigned char tfcr; /* Tx function code */
398 unsigned short mrblr; /* Rx buffer length */
399 unsigned long rstate; /* Rx internal state */
400 unsigned long rptr; /* Rx internal data pointer */
401 unsigned short rbptr; /* rb BD Pointer */
402 unsigned short rcount; /* Rx internal byte count */
403 unsigned long rtemp; /* Rx temp */
404 unsigned long tstate; /* Tx internal state */
405 unsigned long tptr; /* Tx internal data pointer */
406 unsigned short tbptr; /* Tx BD pointer */
407 unsigned short tcount; /* Tx byte count */
408 unsigned long ttemp; /* Tx temp */
409 unsigned long rcrc; /* temp receive CRC */
410 unsigned long tcrc; /* temp transmit CRC */
411
412 /*
413 * TRANSPARENT specific parameter RAM
414 */
415 unsigned long crc_p; /* CRC Preset */
416 unsigned long crc_c; /* CRC constant */
417};
418
419struct timer_pram {
420 /*
421 * RISC timers parameter RAM
422 */
423 unsigned short tm_base; /* RISC timer table base adr */
424 unsigned short tm_ptr; /* RISC timer table pointer */
425 unsigned short r_tmr; /* RISC timer mode register */
426 unsigned short r_tmv; /* RISC timer valid register */
427 unsigned long tm_cmd; /* RISC timer cmd register */
428 unsigned long tm_cnt; /* RISC timer internal cnt */
429};
430
431#endif
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